From d2a0b0c1617c8bef53a08f7924cc93b7446512f8 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Wed, 14 Feb 2018 14:51:38 -0600 Subject: FIR + RAS XML updates p9_sbe_scominit.C mask PBCENT FIR bit 5, rely on action of unit master specific FIR bits to drive attention generation on any cresp address error condition Change-Id: I3c23aeecd426687fe91d37aadfd5ca6243c4a4b3 CQ: SW417475 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54067 Reviewed-by: Daniel J. Henderson Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Caleb N. Palmer Reviewed-by: Brian J. Stegmiller Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54082 Reviewed-by: Sachin Gupta --- src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/import/chips') diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index 29698fd9..0e2a0854 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -66,8 +66,8 @@ const uint64_t LPC_BAR_MASK = 0xFF000000FFFFFFFFULL; // FBC FIR constants const uint64_t FBC_CENT_FIR_ACTION0 = 0x0000000000000000ULL; -const uint64_t FBC_CENT_FIR_ACTION1 = 0x0440000000000000ULL; -const uint64_t FBC_CENT_FIR_MASK = 0x111FC00000000000ULL; +const uint64_t FBC_CENT_FIR_ACTION1 = 0x0040000000000000ULL; +const uint64_t FBC_CENT_FIR_MASK = 0x151FC00000000000ULL; const uint64_t FBC_WEST_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t FBC_WEST_FIR_ACTION1 = 0x0000000000000000ULL; const uint64_t FBC_WEST_FIR_MASK = 0x0000FFFFC0000000ULL; -- cgit v1.2.1