From 8e6447a0500a78445fe8ce5652c9979292962f3f Mon Sep 17 00:00:00 2001
From: Stephen Glancy <sglancy@us.ibm.com>
Date: Mon, 27 Nov 2017 14:47:16 -0600
Subject: Updates WR VREF for characterization results

Change-Id: I9803ee77afa2ebc32e12d9d528ac4ae6a6c947f8
CQ:SW411492
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50709
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69809
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
---
 .../procedures/xml/attribute_info/memory_mcs_attributes.xml | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/import/chips')

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index e29d37cf..2a6633d8 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -3281,4 +3281,17 @@
         <mssAccessorName>phy_seq_refresh</mssAccessorName>
     </attribute>
 
+    <attribute>
+      <id>ATTR_MSS_WR_VREF_OFFSET</id>
+      <targetType>TARGET_TYPE_MCBIST</targetType>
+      <description>
+        Offsets the WR VREF value from the VPD when creating the eff config WR VREF attributes.
+      </description>
+      <default>0</default>
+      <valueType>int8</valueType>
+      <writeable/>
+      <platInit/>
+      <mssAccessorName>wr_vref_offset</mssAccessorName>
+    </attribute>
+
 </attributes>
-- 
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