From 2dab7d4053aa119f11d8c98ca7413d5fc50e0339 Mon Sep 17 00:00:00 2001 From: Amit Tendolkar Date: Mon, 4 Dec 2017 00:29:09 -0600 Subject: Cache/Core stop clocks: add shut down of Power Management to remove contentions Ported changes from https://ralgit01.raleigh.ibm.com/gerrit1/#/c/44781/25 to simplify auto mirror conflicts and reuse existing SBE HWP files - Halt SGPE, PGPE and CMEs assocatiated within the targeted EQ - Clear the PCB atomic lock that may be in place by SGPE - Add core stopclocks changes - Fixed cache stop clocks XML callout - Fix atomic lock library dependencies - Only enable function on DD2 - Halt PPE only if not already in halt - Enhance PPE Halt FFDC Key_Cronus_Test=PM_REGRESS Change-Id: Id6c11176d222213bf1a01b91cade41de989f04c6 RTC: 180317 CQ: SW406569 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50415 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: Cronus HW CI Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: Brian T. Vanderpool Reviewed-by: Gregory S. Still Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50420 Reviewed-by: Hostboot Team Reviewed-by: Sachin Gupta --- .../procedures/hwp/cache/p9_hcd_cache_stopclocks.C | 64 +++++++++++++++++----- .../procedures/hwp/core/p9_hcd_core_stopclocks.C | 51 ++++++++++++++++- .../chips/p9/procedures/hwp/lib/p9_ppe_utils.C | 63 ++++++++++++++------- .../chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C | 29 +++++++--- .../error_info/p9_hcd_cache_stopclocks_errors.xml | 48 ++++++++++++++++ .../error_info/p9_hcd_core_stopclocks_errors.xml | 50 ++++++++++++++++- .../xml/error_info/p9_ppe_state_errors.xml | 8 ++- .../procedures/xml/error_info/p9_sbe_ppe_utils.xml | 6 +- 8 files changed, 269 insertions(+), 50 deletions(-) (limited to 'src/import/chips') diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C index 56475f70..66087497 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C @@ -40,11 +40,18 @@ //------------------------------------------------------------------------------ #include #include +#include #include #include #include #include -#include +#include +#ifdef __PPE__ + #include +#else + #include +#endif +#include //------------------------------------------------------------------------------ // Constant Definitions @@ -88,6 +95,9 @@ p9_hcd_cache_stopclocks( auto l_core_functional_vector = i_target.getChildren (fapi2::TARGET_STATE_FUNCTIONAL); + auto l_ex_vector = + i_target.getChildren + (fapi2::TARGET_STATE_FUNCTIONAL); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, l_sys, l_is_mpipl)); @@ -163,6 +173,45 @@ p9_hcd_cache_stopclocks( if (!l_data64.getBit()) { FAPI_DBG("Gracefully turn off power management, if fail, continue anyways"); + +#ifdef DD2 + FAPI_DBG("Halting the PGPE ..."); + l_rc = ppe_halt(l_chip, PGPE_BASE_ADDRESS); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CACHE_STOPCLKS_PGPE_HALT_TIMEOUT() + .set_CHIP(l_chip), + "PSTATE GPE Halt timeout"); + + FAPI_DBG("Halting the SGPE ..."); + l_rc = ppe_halt(l_chip, SGPE_BASE_ADDRESS); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CACHE_STOPCLKS_SGPE_HALT_TIMEOUT() + .set_CHIP(l_chip), + "STOP GPE Halt timeout"); + + FAPI_DBG("Clear the atomic lock on EQ %d", l_attr_chip_unit_pos); + l_rc = p9_clear_atomic_lock(i_target); + FAPI_DBG("AFter the atomic lock %u", (uint32_t)l_rc); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CACHE_STOPCLKS_ATOMIC_LOCK_FAIL() + .set_EQ(i_target), + "EQ Atomic Halt timeout"); + + for ( auto& ex : l_ex_vector ) + { + fapi2::ATTR_CHIP_UNIT_POS_Type l_cme_id = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, ex, l_cme_id)); + + FAPI_DBG("Halting CME %d", l_cme_id ); + uint64_t l_cme_base_address = getCmeBaseAddress (l_cme_id); + l_rc = ppe_halt(l_chip, l_cme_base_address); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CACHE_STOPCLKS_CME_HALT_TIMEOUT() + .set_EX(ex), + "CME Halt timeout"); + } + +#endif } FAPI_DBG("Check cache clock controller status"); @@ -302,19 +351,6 @@ p9_hcd_cache_stopclocks( FAPI_TRY(putScom(l_chip, l_scom_addr, DATA_SET(7))); } -// // ------------------------------- -// // Disable VDM -// // ------------------------------- -// -// if (l_attr_vdm_enabled == fapi2::ENUM_ATTR_VDM_ENABLED_TRUE) -// { -// FAPI_DBG("Clear Jump Protect Enable via DPLL_CTRL[1] (no need to poll DPLL_STAT)"); -// FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(1))); -// FAPI_DBG("Set VDM Disable via QPPM_VDMCR[1]"); -// FAPI_TRY(putScom(i_target, EQ_PPM_VDMCR_OR, MASK_SET(1))); -// FAPI_DBG("Drop VDM Poweron via QPPM_VDMCR[0]"); -// FAPI_TRY(putScom(i_target, EQ_PPM_VDMCR_CLEAR, MASK_SET(0))); -// } // ------------------------------- // Shutdown edram diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C index f401258a..a9967879 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C @@ -43,7 +43,15 @@ #include #include #include -#include "p9_hcd_core_stopclocks.H" +#include +#include +#include +#ifdef __PPE__ + #include +#else + #include +#endif +#include //------------------------------------------------------------------------------ // Constant Definitions @@ -82,6 +90,9 @@ p9_hcd_core_stopclocks( auto l_perv = i_target.getParent(); auto l_chip = i_target.getParent(); + auto l_ex_vector = l_quad.getChildren + (fapi2::TARGET_STATE_FUNCTIONAL); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip, l_attr_sdisn_setup)); @@ -132,8 +143,44 @@ p9_hcd_core_stopclocks( if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0) { - //halt cme(poll for halted, if timeout, print warnning keep going). +#ifdef DD2 + FAPI_DBG("Halting the PGPE ..."); + l_rc = ppe_halt(l_chip, PGPE_BASE_ADDRESS); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CORE_STOPCLKS_PGPE_HALT_TIMEOUT() + .set_CHIP(l_chip), + "PSTATE GPE Halt timeout"); + + FAPI_DBG("Halting the SGPE ..."); + l_rc = ppe_halt(l_chip, SGPE_BASE_ADDRESS); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CORE_STOPCLKS_SGPE_HALT_TIMEOUT() + .set_CHIP(l_chip), + "STOP GPE Halt timeout"); + + FAPI_DBG("Clear the atomic lock on EQ %d", l_attr_chip_unit_pos); + l_rc = p9_clear_atomic_lock(l_quad); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CORE_STOPCLKS_ATOMIC_LOCK_FAIL() + .set_EQ(l_quad), + "EQ Atomic Halt timeout"); + + for ( auto& ex : l_ex_vector ) + { + fapi2::ATTR_CHIP_UNIT_POS_Type l_cme_id = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, ex, l_cme_id)); + + FAPI_DBG("Halting CME %d", l_cme_id ); + uint64_t l_cme_base_address = getCmeBaseAddress (l_cme_id); + l_rc = ppe_halt(l_chip, l_cme_base_address); + FAPI_ASSERT_NOEXIT(!l_rc, + fapi2::CACHE_STOPCLKS_CME_HALT_TIMEOUT() + .set_EX(ex), + "CME Halt timeout"); + } + +#endif FAPI_DBG("Assert Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]"); FAPI_TRY(putScom(l_quad, (l_attr_chip_unit_pos < 2) ? diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C index 6395f761..15bd9e35 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C +++ b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C @@ -28,10 +28,10 @@ /// /// *HWP HW Owner : Ashish More /// *HWP HW Backup Owner : Brian Vanderpool -/// *HWP FW Owner : Sangeetha T S +/// *HWP FW Owner : Amit Tendolkar /// *HWP Team : PM -/// *HWP Level : 2 -/// *HWP Consumed by : SBE, Cronus +/// *HWP Level : 3 +/// *HWP Consumed by : Hostboot, FSP /// /// @verbatim /// @@ -43,12 +43,9 @@ #include #include #include +#include #include - - - - //// Vector defining the special acceess egisters //const std::map v_ppe_special_num_name = //{ @@ -198,13 +195,15 @@ fapi2::ReturnCode ppe_pollHaltState( { FAPI_TRY(getScom(i_target, i_base_address + PPE_XIRAMDBG, l_data64), "Error in GETSCOM"); } - while (! l_data64.getBit<0>() && + while (! l_data64.getBit() && --l_timeout_count != 0); - FAPI_ASSERT(l_data64.getBit<0>(), fapi2::P9_PPE_STATE_HALT_TIMEOUT_ERR(), - "PPE Halt Timeout"); - + FAPI_ASSERT ( l_data64.getBit(), + fapi2::PPE_STATE_HALT_TIMEOUT_ERR() + .set_TARGET(i_target) + .set_ADDRESS(i_base_address), + "PPE Halt Timeout" ); fapi_try_exit: return fapi2::current_err; @@ -218,12 +217,24 @@ fapi2::ReturnCode ppe_halt( { fapi2::buffer l_data64; - FAPI_INF(" Send HALT command via XCR..."); - l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3); - - FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), "Error in PUTSCOM in XCR to generate Halt condition"); + FAPI_TRY ( getScom ( i_target, + i_base_address + PPE_XIRAMDBG, + l_data64 ), + "Error reading PPE Halt State" ); - FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + // Halt the PPE only if it is not already halted + if (! l_data64.getBit()) + { + FAPI_INF(" Send HALT command via XCR..."); + l_data64.flush<0>().insertFromRight(p9hcd::HALT, PU_PPE_XIXCR_XCR, + PU_PPE_XIXCR_XCR_LEN); + + FAPI_TRY ( putScom ( i_target, + i_base_address + PPE_XIXCR, + l_data64 ), + "Error in PUTSCOM in XCR to generate Halt condition" ); + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + } fapi_try_exit: return fapi2::current_err; @@ -236,13 +247,23 @@ fapi2::ReturnCode ppe_force_halt( { fapi2::buffer l_data64; - FAPI_INF(" Send FORCE HALT command via XCR..."); - l_data64.flush<0>().insertFromRight(p9hcd::FORCE_HALT, 1, 3); + FAPI_TRY ( getScom ( i_target, + i_base_address + PPE_XIRAMDBG, + l_data64 ), + "Error reading PPE Halt State" ); - FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), - "Error in PUTSCOM in XCR to generate Force Halt condition"); + // Force Halt PPE only is it is not already Halted + if (! l_data64.getBit()) + { + FAPI_INF(" Send FORCE HALT command via XCR..."); + l_data64.flush<0>().insertFromRight(p9hcd::FORCE_HALT, PU_PPE_XIXCR_XCR, + PU_PPE_XIXCR_XCR_LEN); - FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), + "Error in PUTSCOM in XCR to generate Force Halt condition"); + + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + } fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C index c7f523e8..8c7dc4e7 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C +++ b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C @@ -43,6 +43,8 @@ #include #include #include +#include + //----------------------------------------------------------------------------- uint32_t ppe_getMxsprInstruction ( const uint32_t i_opcode, @@ -77,11 +79,13 @@ fapi2::ReturnCode ppe_pollHaltState( l_data64 ), "Failed reading XIRAMDBG register!" ); } - while ((! l_data64.getBit<0>()) && + while ((! l_data64.getBit()) && (--l_timeout_count != 0)); - FAPI_ASSERT ((l_data64.getBit<0>()), - fapi2::SBE_PPE_UTILS_HALT_TIMEOUT_ERR(), + FAPI_ASSERT ((l_data64.getBit()), + fapi2::SBE_PPE_UTILS_HALT_TIMEOUT_ERR() + .set_TARGET(i_target) + .set_ADDRESS(i_base_address), "PPE Halt Timeout!"); fapi_try_exit: @@ -94,14 +98,23 @@ fapi2::ReturnCode ppe_halt( const uint64_t i_base_address) { fapi2::buffer l_data64; + FAPI_TRY ( getScom ( i_target, + i_base_address + PPE_XIRAMDBG, + l_data64 ), + "Error reading PPE Halt State" ); - FAPI_INF(" Send HALT command via XCR..."); - l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3); + // Halt the PPE only if it is not already halted + if (! l_data64.getBit()) + { + FAPI_INF(" Send HALT command via XCR..."); + l_data64.flush<0>().insertFromRight(p9hcd::HALT, PU_PPE_XIXCR_XCR, + PU_PPE_XIXCR_XCR_LEN); - FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), - "Error in PUTSCOM in XCR to generate Halt condition"); + FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), + "Error in PUTSCOM in XCR to generate Halt condition"); - FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + } fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml index f611af50..020e7195 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml @@ -140,4 +140,52 @@ + + RC_CACHE_STOPCLKS_PGPE_HALT_TIMEOUT + + A timeout occured while waiting the PGPE to halt + + CHIP + + CHIP + HIGH + + + + + RC_CACHE_STOPCLKS_SGPE_HALT_TIMEOUT + + A timeout occured while waiting the SGPE to halt + + CHIP + + CHIP + HIGH + + + + + RC_CACHE_STOPCLKS_ATOMIC_LOCK_FAIL + + Failed attempt to clear the atomic lock to the cache chiplet + + EQ + + EQ + HIGH + + + + + RC_CACHE_STOPCLKS_CME_HALT_TIMEOUT + + A timeout occured while waiting a CME to halt + + EX + + EX + HIGH + + + diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_stopclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_stopclocks_errors.xml index 942abe31..b043f6d1 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_stopclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_stopclocks_errors.xml @@ -5,7 +5,7 @@ - + @@ -57,4 +57,52 @@ CORECPLTSTAT + + RC_CORE_STOPCLKS_PGPE_HALT_TIMEOUT + + A timeout occured while waiting the PGPE to halt + + CHIP + + CHIP + HIGH + + + + + RC_CORE_STOPCLKS_SGPE_HALT_TIMEOUT + + A timeout occured while waiting the SGPE to halt + + CHIP + + CHIP + HIGH + + + + + RC_CORE_STOPCLKS_ATOMIC_LOCK_FAIL + + Failed attempt to clear the atomic lock to the cache chiplet + + EQ + + EQ + HIGH + + + + + RC_CORE_STOPCLKS_CME_HALT_TIMEOUT + + A timeout occured while waiting a CME to halt + + EX + + EX + HIGH + + + diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_ppe_state_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_ppe_state_errors.xml index 71efdfcb..0672b1d4 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_ppe_state_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_ppe_state_errors.xml @@ -26,12 +26,14 @@ - RC_P9_PPE_STATE_HALT_TIMEOUT_ERR + RC_PPE_STATE_HALT_TIMEOUT_ERR - Procedure: p9_ppe_state - HALT Timedout. + A HALT operation to a PPE timed out. This is indicative of hardware error. TARGET + ADDRESS + + diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml index 1c62688c..93d4d8e5 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml @@ -28,8 +28,12 @@ RC_SBE_PPE_UTILS_HALT_TIMEOUT_ERR - PPE Halt timed out + A HALT operation to a PPE timed out. This is indicative of hardware error. + TARGET + ADDRESS + + -- cgit v1.2.1