From 2e4607a018b70e3019155e642d7f07ab2c9d4905 Mon Sep 17 00:00:00 2001 From: Santosh Puranik Date: Tue, 17 Jan 2017 10:39:05 -0600 Subject: Make plat init attributes non-writable Change-Id: I382948a4083293e4ecc42a9759559a060444f5f0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34997 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Sachin Gupta Reviewed-by: SRINIVAS V. POLISETTY Reviewed-by: Matt K. Light Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35043 Reviewed-by: Hostboot Team --- .../p9/procedures/hwp/perv/p9_sbe_attr_setup.C | 243 +-------------------- .../xml/attribute_info/nest_attributes.xml | 23 +- .../p9_sbe_load_bootloader_attributes.xml | 1 - .../xml/attribute_info/pervasive_attributes.xml | 52 ----- 4 files changed, 8 insertions(+), 311 deletions(-) (limited to 'src/import/chips/p9') diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index 223b063c..697978f1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -110,14 +110,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const fapi2::buffer l_read_scratch8 = 0; fapi2::buffer l_read_1 = 0; fapi2::buffer l_read_2 = 0; - fapi2::buffer l_read_3 = 0; fapi2::buffer l_read_4 = 0; fapi2::buffer l_read_5 = 0; fapi2::buffer l_read_6 = 0; const fapi2::Target FAPI_SYSTEM; fapi2::buffer l_data64; - bool sbe_slave_chip = false; - fapi2::buffer l_read_device_reg = 0; FAPI_INF("p9_sbe_attr_setup: Entering ..."); FAPI_DBG("Read Scratch8 for validity of Scratch register"); @@ -164,33 +161,10 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_secure_settings.secureAccessBit = l_read_reg.getBit<4>(); FAPI_DBG("Setting up ATTR_SECURITY_SETTINGS"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURE_SETTINGS, FAPI_SYSTEM, l_secure_settings.data8)); - - l_read_1 = 0; - l_read_1.writeBit<7>(l_read_reg.getBit<4>()); - - FAPI_DBG("Setting ATTR_SECURITY_ENABLE with the SAB state"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURITY_ENABLE, FAPI_SYSTEM, l_read_1)); } //read_scratch1_reg { - if ( l_read_scratch8.getBit<0>() ) - { - FAPI_DBG("Reading Scratch_reg1"); - //Getting SCRATCH_REGISTER_1 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_1 - - l_read_scratch_reg.extract<0, 6>(l_read_1); - l_read_scratch_reg.extract<8, 24>(l_read_5); - - FAPI_DBG("Setting up ATTR_EQ_GARD, ATTR_EC_GARD"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5)); - - l_read_1 = 0; - l_read_5 = 0; - } - else + if ( !l_read_scratch8.getBit<0>() ) { l_read_scratch_reg.flush<0>(); @@ -219,65 +193,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const uint8_t l_ob2_pll_bucket = 0; uint8_t l_ob3_pll_bucket = 0; - if ( l_read_scratch8.getBit<1>() ) - { - uint8_t l_ndl_meshctrl_setup = 0x0; - - FAPI_DBG("Reading Scratch_reg2"); - //Getting SCRATCH_REGISTER_2 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2 - - l_read_scratch_reg.extractToRight<0, 16>(l_read_4); - - l_read_scratch_reg.extractToRight(l_ob0_pll_bucket); - l_read_scratch_reg.extractToRight(l_ob1_pll_bucket); - l_read_scratch_reg.extractToRight(l_ob2_pll_bucket); - l_read_scratch_reg.extractToRight(l_ob3_pll_bucket); - l_read_scratch_reg.extractToRight(l_read_1); - - // Workaround to handle backward compatibilty - // Old drivers will keep MBX OBUS PLL bucket value as zero. So - // change it to 1 to make old drivers compatible with new SBE - // image - if( 0 == l_ob0_pll_bucket ) - { - l_ob0_pll_bucket = 1; - } - - if( 0 == l_ob1_pll_bucket ) - { - l_ob1_pll_bucket = 1; - } - - if( 0 == l_ob2_pll_bucket ) - { - l_ob2_pll_bucket = 1; - } - - if( 0 == l_ob3_pll_bucket ) - { - l_ob3_pll_bucket = 1; - } - - FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); - - l_read_scratch_reg.extractToRight<16, 4>(l_ndl_meshctrl_setup); - l_ndl_meshctrl_setup = (~l_ndl_meshctrl_setup) & 0x0F; - FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_ndl_meshctrl_setup)); - - FAPI_DBG("Setting up ATTR_MC_PLL_BUCKET"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); - - FAPI_DBG("Setting up ATTR_OBX_PLL_BUCKET"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket)); - } - else + if ( !l_read_scratch8.getBit<1>() ) { l_read_scratch_reg.flush<0>(); @@ -316,27 +232,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const //read_scratch3_reg { - uint8_t l_is_mpipl = 0; - uint8_t l_is_sp_mode = 0; - - if ( l_read_scratch8.getBit<2>() ) - { - FAPI_DBG("Reading Scratch_reg3"); - //Getting SCRATCH_REGISTER_3 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_3_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_3 - - l_read_scratch_reg.extractToRight<2, 1>(l_is_mpipl); - - FAPI_DBG("Setting up ATTR_IS_MPIPL"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl)); - - l_read_scratch_reg.extractToRight<3, 1>(l_is_sp_mode); - - FAPI_DBG("Setting up ATTR_IS_SP_MODE"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_SP_MODE, i_target_chip, l_is_sp_mode)); - } - else + if ( !l_read_scratch8.getBit<2>() ) { l_read_scratch_reg.flush<0>(); @@ -364,39 +260,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const uint8_t l_nest_mem_x_o_pci_bypass = 0; uint8_t l_attr_obus_ratio = 0; - if ( l_read_scratch8.getBit<3>() ) - { - FAPI_DBG("Reading Scratch_Reg4"); - //Getting SCRATCH_REGISTER_4 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_4 - - l_read_scratch_reg.extractToRight<0, 16>(l_read_4); - l_read_scratch_reg.extractToRight<16, 1>(l_cp_filter_bypass); - l_read_scratch_reg.extractToRight<17, 1>(l_ss_filter_bypass); - l_read_scratch_reg.extractToRight<18, 1>(l_io_filter_bypass); - l_read_scratch_reg.extractToRight<19, 1>(l_dpll_bypass); - l_read_scratch_reg.extractToRight<20, 1>(l_nest_mem_x_o_pci_bypass); - l_read_scratch_reg.extractToRight(l_attr_obus_ratio); - l_read_scratch_reg.extractToRight(l_read_1); - - FAPI_DBG("Setting up PLL bypass attributes"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, l_ss_filter_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, l_io_filter_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DPLL_BYPASS, i_target_chip, l_dpll_bypass)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_mem_x_o_pci_bypass)); - FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); - - FAPI_DBG("Setting up ATTR_OBUS_RATIO_VALUE"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, l_attr_obus_ratio)); - - l_read_1 = 0; - l_read_4 = 0; - } - else + if ( !l_read_scratch8.getBit<3>() ) { l_read_scratch_reg.flush<0>(); @@ -449,7 +313,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const uint8_t l_mc_sync_mode = 0; uint8_t l_slow_pci_ref_clock = 0; - if ( l_read_scratch8.getBit<4>() ) + if( l_read_scratch8.getBit<4>() ) { FAPI_DBG("Reading Scratch_reg5"); //Getting SCRATCH_REGISTER_5 register value @@ -465,47 +329,8 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_system_ipl_phase = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL; } - l_read_scratch_reg.extract<1, 1, 7>(l_force_all_cores); - - if (l_read_scratch_reg.getBit<2>()) - { - l_risk_level = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE; - } - else - { - l_risk_level = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE; - } - - if (l_read_scratch_reg.getBit<3>()) - { - l_disable_hbbl_vectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE; - } - else - { - l_disable_hbbl_vectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE; - } - - l_read_scratch_reg.extract<4, 1, 7>(l_mc_sync_mode); - - if (l_read_scratch_reg.getBit()) - { - l_slow_pci_ref_clock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_NORMAL; - } - else - { - l_slow_pci_ref_clock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW; - } - - l_read_scratch_reg.extract<12, 20, 0>(l_pll_mux); - - FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES"); + FAPI_DBG("Setting up SYSTEM_IPL_PHASE"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux)); } else { @@ -596,61 +421,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const { uint8_t l_pump_mode; - if ( l_read_scratch8.getBit<5>() ) - { - FAPI_DBG("Reading Scratch_reg6"); - //Getting SCRATCH_REGISTER_6 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_6 - - l_read_1 = 0; - sbe_slave_chip = l_read_scratch_reg.getBit<24>(); - - if ( !sbe_slave_chip ) // 0b0 == master - { - FAPI_DBG("Reading DEVICE_ID_REG value"); - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_DEVICE_ID_REG, l_read_device_reg)); - - if (!l_read_device_reg.getBit<40>()) - { - l_read_1.setBit<7>(); - } - } - - if (l_read_scratch_reg.getBit()) - { - l_pump_mode = fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP; - } - else - { - l_pump_mode = fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE; - } - - l_read_scratch_reg.extractToRight<26, 3>(l_read_2); - l_read_scratch_reg.extractToRight<29, 3>(l_read_3); - - FAPI_DBG("Setting up PUMP MODE"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, - fapi2::Target(), - l_pump_mode)); - - FAPI_DBG("Setting up MASTER_CHIP, FABRIC_GROUP_ID and CHIP_ID"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip, - l_read_1)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip, - l_read_2)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip, - l_read_3)); - - l_read_scratch_reg.extractToRight<17, 3>(l_read_2); - l_read_scratch_reg.extractToRight<20, 3>(l_read_3); - - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target_chip, - l_read_2)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip, - l_read_3)); - } - else + if ( !l_read_scratch8.getBit<5>() ) { l_read_scratch_reg.flush<0>(); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 15cabe12..850cb305 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -193,7 +193,6 @@ SLOW = 0x01 - @@ -291,7 +290,6 @@ CHIP_IS_GROUP = 0x02 - @@ -421,10 +419,6 @@ uint8 - - @@ -438,10 +432,6 @@ uint8 - - @@ -454,10 +444,6 @@ uint8 - - @@ -781,11 +767,8 @@ uint8 HB_IPL = 0x1,HB_RUNTIME = 0x2,CACHE_CONTAINED = 0x4,CHIP_CONTAINED = 0x8,NONHB_IPL = 0x10 - - + @@ -800,10 +783,6 @@ TRUE = 0x1 - - diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml index a69a44f8..0fd5d891 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml @@ -107,7 +107,6 @@ uint64 - diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 06009e70..2a8e04d1 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -34,10 +34,6 @@ setup clock mux settings uint32 - - @@ -55,7 +51,6 @@ uint16 - @@ -65,7 +60,6 @@ uint8 - @@ -75,7 +69,6 @@ uint32 - @@ -106,7 +99,6 @@ FSP_LESS = 0x0,FSP = 0x1 - @@ -137,7 +129,6 @@ uint8 - @@ -147,7 +138,6 @@ uint8 - @@ -157,7 +147,6 @@ uint8 - @@ -167,7 +156,6 @@ uint8 - @@ -177,7 +165,6 @@ uint8 - @@ -196,7 +183,6 @@ uint16 - @@ -208,7 +194,6 @@ FALSE = 0x0,TRUE = 0x1 - @@ -220,7 +205,6 @@ FALSE = 0x0,TRUE = 0x1 - @@ -239,7 +223,6 @@ uint32 - @@ -384,7 +367,6 @@ FALSE = 0x0,TRUE = 0x1 - @@ -464,7 +446,6 @@ uint8 - @@ -474,7 +455,6 @@ uint8 - @@ -486,7 +466,6 @@ uint8 - @@ -496,7 +475,6 @@ Holds the state of Security Access Bit (SAB) uint8 - @@ -512,7 +490,6 @@ uint8 - @@ -525,9 +502,6 @@ - ATTR_OBUS_RATIO_VALUE TARGET_TYPE_PROC_CHIP @@ -538,7 +512,6 @@ uint8 - @@ -547,7 +520,6 @@ Pibmem repair attribute 0 uint64 - @@ -557,7 +529,6 @@ Pibmem repair attribute 1 uint64 - @@ -567,7 +538,6 @@ Pibmem repair attribute 2 uint64 - @@ -585,10 +555,6 @@ To skip the locking sequence and check for lock of CP filter PLL uint8 - - @@ -597,10 +563,6 @@ To skip the locking sequence and check for lock of SS filter PLL uint8 - - @@ -609,10 +571,6 @@ To skip the locking sequence and check for lock of IO filter PLL uint8 - - @@ -621,10 +579,6 @@ Skip locking sequence and check for lock of DPLL uint8 - - @@ -633,10 +587,6 @@ Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs uint8 - - @@ -675,7 +625,6 @@ System Configurtion information - 1 indicates a chip present uint64 - @@ -784,7 +733,6 @@ uint8 - -- cgit v1.2.1