From 5e83bcb5cf9d400739cfb2beaab1a3173e8cafb2 Mon Sep 17 00:00:00 2001 From: Shakeeb Date: Thu, 1 Sep 2016 06:24:44 -0500 Subject: SBE move import` Change-Id: I726951318cdb19fd445af2f7910e0d6872eff18c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29086 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta Reviewed-by: AMIT J. TENDOLKAR --- src/import/chips/p9/sw_simulation/chip.act | 283 +++++++++++++++++++++++++++++ 1 file changed, 283 insertions(+) create mode 100644 src/import/chips/p9/sw_simulation/chip.act (limited to 'src/import/chips/p9/sw_simulation/chip.act') diff --git a/src/import/chips/p9/sw_simulation/chip.act b/src/import/chips/p9/sw_simulation/chip.act new file mode 100644 index 00000000..1abe32a4 --- /dev/null +++ b/src/import/chips/p9/sw_simulation/chip.act @@ -0,0 +1,283 @@ +# This file will contain all the Chip Actions +# ============================================================================= +# Simics action for p9_sbe_fabricinit +# ============================================================================= +CAUSE_EFFECT { +LABEL=[Fabric Init via ADU] +WATCH=[REG(0x00090001] #PU_ALTD_CMD_REG +CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #PU_ALTD_CMD_REG, ALTD_CMD_START_OP_BIT +EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #PU_ALTD_STATUS_REG, ALTD_STATUS_ADDR_DONE_BIT +EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[61] #PU_ALTD_STATUS_REG, ALTD_STATUS_CRESP_ACK_DONE +#EFFECT: TARGET=[REG(0x05011C0A)] OP=[BIT,ON] BIT=[0] #PU_FBC_MODE_REG, PU_FBC_MODE_PB_INITIALIZED_BIT +} + +# ============================================================================= +# Action file not necessary for procedures: +# p9_sbe_scominit +# p9_sbe_mcs_setup +# p9_sbe_instruct_start (default 0's work) +# ============================================================================= + +# ============================================================================= +# Actions for p9_pba_access and p9_pba_setup procedures +# ============================================================================= +#If a reset is done need to unset the PBA_SLVRST_SLVCTL3_IN_PROG bit +CAUSE_EFFECT{ + LABEL=[PBA Reset set] + # Watch the PBASLVRST register for bits 0:2 to go to 0b111 + WATCH=[REG(0x068001)] #PBASLVRST + + CAUSE: TARGET=[REG(0x068001)] OP=[BIT,ON] BIT=[0] + CAUSE: TARGET=[REG(0x068001)] OP=[BIT,ON] BIT=[1] + CAUSE: TARGET=[REG(0x068001)] OP=[BIT,ON] BIT=[2] + + #If the reset is set unset bit 7 to show that the PBA Slave reset is no longer in progress + EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7] + +} + +#If a read or write is done need to set the PBARBUFVAL[0,1,2,3,4,5] bits 33:39 to 0b0000001 +#set the PBAWBUFVAL[0,1] bits 35:39 to 0b00001 +#set the PBASLVRST to appropriate value +CAUSE_EFFECT { + LABEL=[PBA Read or Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST] + #If the data register is read or write + WATCH_READ=[REG(0x0006D075)] #OCBDR3 + WATCH=[REG(0x0006D075)] + CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11] + + #set PBARBUFVAL0[buffer_status] to 0b0000001 + EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[33] + EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[34] + EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,ON] BIT=[39] + #set PBARBUFVAL1[buffer_status] to 0b0000001 + EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[33] + EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[34] + EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,ON] BIT=[39] + #set PBARBUFVAL2[buffer_status] to 0b0000001 + EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[33] + EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[34] + EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,ON] BIT=[39] + + #set PBARBUFVAL3[buffer_status] to 0b0000001 + EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[33] + EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[34] + EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,ON] BIT=[39] + #set PBARBUFVAL4[buffer_status] to 0b0000001 + EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[33] + EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[34] + EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,ON] BIT=[39] + #set PBARBUFVAL5[buffer_status] to 0b0000001 + EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[33] + EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[34] + EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,ON] BIT=[39] + + #set PBAWBUFVAL0[buffer_status] to 0b00001 + EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,ON] BIT=[39] + + #set PBAWBUFVAL0[buffer_status] to 0b00001 + EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[35] + EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[36] + EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[37] + EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[38] + EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,ON] BIT=[39] + + #unset PBASLVRST[in_prog] bit + EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7] + #set PBASLVRST[busy_status] to 0b0000 bits 8:11 + EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[8] + EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[9] + EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[10] + EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[11] +} + +#Basabjit had me separate these into the read and write because of their read/writeMainstore modules +#If a read is done do the read from memory +CAUSE_EFFECT{ + LABEL=[PBA Read to set the PBARBUFVAL PBAWBUFVAL and PBASLVRST] + #If the data register is read + WATCH_READ=[REG(0x0006D075)] #OCBDR3 + CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11] + + #Basabjit had me add these + # Read from the Memory + EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of address + EFFECT: TARGET=[MODULE(readMainstore, 0x00068FFF)] OP=[MODULECALL] DATA=[REG(0x0006D075)] + EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)] +} + +#If a write is done do the write into memory +CAUSE_EFFECT{ + LABEL=[PBA Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST] + #If the data register is written + WATCH=[REG(0x0006D075)] #OCBDR3 + CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11] + + # Write into from the Memory + EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of PBA address + EFFECT: TARGET=[MODULE(writeMainstore, 0x00068FFF)] OP=[MODULECALL] DATA=[REG(0x0006D075)] + EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)] +} + +# PBA ADDRESS CALC +CAUSE_EFFECT{ + LABEL=[PBA ADDR Calculation] + #If the data register is read + WATCH=[REG(0x00068FFE)] + + #Determine PBA Address + EFFECT: TARGET=[REG(0x00068FFF)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)] + EFFECT: TARGET=[REG(0x00068FFF)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x0006D070)] MASK=[LITERAL(64,00000000 000FFFFF)] SHIFT=[32] + + #bits 37:43 if PBA mask set + EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF,SHIFT] DATA=[REG(0x0006D070)] SHIFT=[32] + EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[REG(0x05012B07)] + EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[LITERAL(64,00000000 07F00000)] + EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)] + + #bits 23:43 if PBA mask set + EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x00068007)] MASK=[LITERAL(64,00000000 0FFFC000)] SHIFT=[-13] + EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[REG(0x05012B07)] + EFFECT: TARGET=[REG(0x00068FFF))] OP=[OR,BUF] DATA=[PBAADDR(0x1)] + + #bits 23:43 if PBA mask clear + EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF] DATA=[REG(0x05012B03)] + EFFECT: TARGET=[PBAADDR(0x0)] OP=[EQUALTO,BUF,INVERT] DATA=[REG(0x05012B07)] + EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[PBAADDR(0x0)] + EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[LITERAL(64,000001FF FFF00000)] + EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)] + + #bits 8:22 always based on PBA BAR + EFFECT: TARGET=[PBAADDR(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x05012B03)] + EFFECT: TARGET=[PBAADDR(0x0)] OP=[AND,BUF] DATA=[LITERAL(64,00FFFE00 00000000)] + EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)] +} + +# ========================================================================== +# Actions for p9_adu_access and p9_adu_setup procedures +# ========================================================================== +#If a read/write is done to the ALTD_DATA Register set the ALTD_STATUS Register so things are as expected +CAUSE_EFFECT{ + LABEL=[ADU Read or write to set ALTD_STATUS Register] + #If the data register is read + WATCH_READ=[REG(0x00090004)] + #If the data register is written + WATCH=[REG(0x00090004)] + + #Set the ALTD_STATUS Register so these bits are set: + #FBC_ALTD_BUSY = WAIT_CMD_ARBIT = WAIT_RESP = OVERRUN_ERR = AUTOINC_ERR = COMMAND_ERR = ADDRESS_ERR = COMMAND_HANG_ERR = DATA_HANG_ERR = PBINIT_MISSING = ECC_CE = ECC_UE = ECC_SUE = 0 + EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,AND] DATA=[LITERAL(64,001FDFFF FFFF1FFF)] + EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,OR] DATA=[LITERAL(64,30000000 00000000)] +} + +#If a read/write is done to the ALTD_DATA Register and the Address only bit is not set then set the DATA_DONE bit to 1 +CAUSE_EFFECT{ + LABEL=[ADU Read or write to set ALTD_STATUS[DATA_DONE] bit] + #If the data register is read + WATCH_READ=[REG(0x00090004)] + #If the data register is written + WATCH=[REG(0x00090004)] + CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] + + #Set the DATA_DONE bit + EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] +} + +#If a read/write is done to the ALTD_DATA Register and the Data only bit is not set then set the ADDR_DONE bit to 1 +CAUSE_EFFECT{ + LABEL=[ADU Read or write to set ALTD_STATUS[ADDR_DONE] bit] + #If the data register is read + WATCH_READ=[REG(0x00090004)] + #If the data register is written + WATCH=[REG(0x00090004)] + CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] + + #Set the ADDR_DONE bit + EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] +} + +#If a read is done to the ALTD_CMD Register and it sets the lock set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set +CAUSE_EFFECT{ + LABEL=[ADU Write to set ALTD_STATUS_BUSY] + WATCH=[REG(0x00090001)] + CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[11] + + #Set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set + EFFECT: TARGET=[REG(0x090003)] OP=[BIT,ON] BIT=[0] +} +#If a write is done to the ALD_CMD_REG to set the FBC_ALTD_START_OP bit it should turn FBC_ALTD_BUSY off +CAUSE_EFFECT{ + LABEL=[ADU Write to ALTD_CMD_REG to unset set ALTD_STATUS FBC_ALTD_BUSY bit] + WATCH=[REG(0x00090001)] + CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] + + #Unset the ALTD_STATUS Register so the ALTD_STATUS_BUSY is unset + EFFECT: TARGET=[REG(0x090003)] OP=[BIT,OFF] BIT=[0] +} + + +# ============================================================================= +# Actions for p9_ram_core procedures +# ============================================================================= +# TODO: RTC 150507 +# MYCHIPLET is supposed to work, but for core chiplets, it only works on core 0 +# because of a bug in SUET. Infrastructure team will fix it using the above RTC. +CAUSE_EFFECT CHIPLETS ec { + LABEL=[p9_ram_core reads Thread Info Register] + # If bit 0 of C_RAM_MODEREG is set (Enable RAM) + WATCH=[REG(MYCHIPLET,0x00010A4E)] + CAUSE: TARGET=[REG(MYCHIPLET, 0x00010A4E)] OP=[BIT,ON] BIT=[0] + # Set all threads active in C_THREAD_INFO + EFFECT: TARGET=[REG(MYCHIPLET, 0x00010A9B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xFFFFFFFF 0xFFFFFFFF)] +} + +CAUSE_EFFECT CHIPLETS ec { + LABEL=[p9_ram_core - C_RAM_CTRL write] + # Any write to RAM CTRL reg (thread, opcode, etc...) + WATCH=[REG(MYCHIPLET, 0x00010A4F)] + # Set C_RAM_STATUS + # - Clear RAM recovery status bit 0 + # - Clear RAM exception status bit 2 + # - Set PPC complete status bit 1 + # - Set LSU is empty status bit 3 + EFFECT: TARGET=[REG(MYCHIPLET, 0x00010A50)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x50000000 0x00000000)] +} + +# ============================================================================= +# Actions for p9_tod_setup and p9_tod_init +# ============================================================================= +#If a write is done to start the state machine set the FSM_REG_IS_RUNNING bit +CAUSE_EFFECT{ + LABEL=[TOD statem machine is running] + WATCH=[REG(0x00040022)] + CAUSE: TARGET[REG(0x00040022)] OP=[BIT,ON] BIT=[0] + EFFECT: TARGET=[REG(0x00040024)] OP=[BIT,ON] BIT=[4] +} -- cgit v1.2.1