From 338653266e2a4b4bf2218616e210c825975c1889 Mon Sep 17 00:00:00 2001 From: Yue Du Date: Thu, 6 Oct 2016 14:59:16 -0500 Subject: Cache HWP: DD1 VCS Workaround Change-Id: I9634a767878904f810cb1e6a0767ba4bbad241cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30827 Reviewed-by: Joachim Fenkes Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: James N. Klazynski Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30888 Reviewed-by: Hostboot Team Reviewed-by: Sachin Gupta --- .../hwp/cache/p9_hcd_cache_chiplet_reset.C | 173 +++++++++++++++++++++ .../hwp/cache/p9_hcd_cache_chiplet_reset.H | 6 +- .../p9/procedures/hwp/cache/p9_hcd_cache_poweron.C | 22 +++ .../p9/procedures/hwp/lib/p9_common_poweronoff.C | 17 +- .../p9/procedures/hwp/lib/p9_common_poweronoff.H | 4 +- .../chips/p9/procedures/hwp/lib/p9_hcd_common.H | 23 ++- .../xml/attribute_info/chip_ec_attributes.xml | 18 +++ 7 files changed, 255 insertions(+), 8 deletions(-) (limited to 'src/import/chips/p9/procedures') diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C index eeee6c65..46dd119e 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -52,6 +52,11 @@ #include #include "p9_hcd_cache_chiplet_reset.H" +#ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX + #include + #include +#endif + //------------------------------------------------------------------------------ // Constant Definitions //------------------------------------------------------------------------------ @@ -77,6 +82,15 @@ enum P9_HCD_CACHE_CHIPLET_RESET_CONSTANTS CACHE_GLSMUX_RESET_DELAY_REF_CYCLES = 40 }; +/// @todo RTC 162433 +/// This is going to break on Nimbus DD2.0 and Cumulus SoA testing. +/// need more discussion in HW/FW interlock on how to handle this. +enum HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX_CONSTATNS +{ + // Eq_fure + Ex_l2_fure(ex0) + Ex_l2_fure(ex1) + DD1_EQ_FURE_RING_LENGTH = (46532 + 119192 + 119192) +}; + //------------------------------------------------------------------------------ // Procedure: Cache Chiplet Reset //------------------------------------------------------------------------------ @@ -91,6 +105,9 @@ p9_hcd_cache_chiplet_reset( uint64_t l_l2gmux_input = 0; uint64_t l_l2gmux_reset = 0; uint8_t l_attr_chip_unit_pos = 0; +#ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX + fapi2::buffer l_attr_dd1_vcs_workaround; +#endif fapi2::Target l_chip = i_target.getParent(); fapi2::Target l_perv = @@ -213,6 +230,19 @@ p9_hcd_cache_chiplet_reset( l_region_scan0, p9hcd::SCAN0_TYPE_GPTR_REPR_TIME)); +#ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX + FAPI_TRY(FAPI_ATTR_GET( + fapi2::ATTR_CHIP_EC_FEATURE_VCS_POWER_ON_IN_CHIPLET_RESET, + l_chip, l_attr_dd1_vcs_workaround)); + + if (l_attr_dd1_vcs_workaround) + { + FAPI_DBG("Enable DD1 VCS workaround"); + FAPI_TRY(p9_hcd_dd1_vcs_workaround(i_target)); + } + +#endif + FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings"); for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) @@ -235,3 +265,146 @@ fapi_try_exit: return fapi2::current_err; } +#ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX +fapi2::ReturnCode +p9_hcd_dd1_vcs_workaround( + const fapi2::Target& i_target) +{ + FAPI_INF(">>p9_hcd_dd1_vcs_workaround"); + fapi2::buffer l_data64; + uint64_t l_regions; + uint32_t l_timeout; + uint32_t l_loop; + + l_regions = p9hcd::CLK_REGION_PERV | + p9hcd::CLK_REGION_EX0_L2 | + p9hcd::CLK_REGION_EX1_L2; + + // ---------------------------------------------------- + // Scan1 initialize region:Perv/L20/L21 type:Fure rings + // Note: must also scan partial good "bad" L2 rings, + // and clock start&stop their latches, as well + // ---------------------------------------------------- + + FAPI_DBG("Assert Vital clock regional fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3))); + + FAPI_DBG("Assert regional fences of scanned regions via CPLT_CTRL1[4,8,9]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, l_regions)); + + FAPI_DBG("Clear clock region register via CLK_REGION"); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, MASK_ZERO)); + + FAPI_DBG("Setup scan select register via SCAN_REGION_TYPE[4,8,9,48,51]"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, + (l_regions | p9hcd::SCAN_TYPE_FUNC | p9hcd::SCAN_TYPE_REGF))); + + FAPI_DBG("Write scan data register via 0x1003E040"); + + for (l_loop = 0; l_loop <= DD1_EQ_FURE_RING_LENGTH / 64; l_loop++) + { + FAPI_DBG("Loop Count: %d", l_loop); + FAPI_TRY(putScom(i_target, 0x1003E040, MASK_ALL)); + } + + // ------------------------------- + // Start Perv/L20/L21 clocks + // ------------------------------- + + FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); + + FAPI_DBG("Start cache clocks(perv/l20/l21) via CLK_REGION"); + l_data64 = (p9hcd::CLK_START_CMD | l_regions | p9hcd::CLK_THOLD_ARY); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); + + FAPI_DBG("Poll for perv/l20/l21 clocks running via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP); + + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), + "perv/l20/l21 Clock Start Timeout"); + + FAPI_DBG("Check perv/l20/l21 clocks running"); + FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_ARY, l_data64)); + + FAPI_ASSERT(((l_data64 & l_regions) == 0), + fapi2::PMPROC_CACHECLKSTART_FAILED().set_EQCLKSTAT(l_data64), + "perv/l20/l21 Clock Start Failed"); + FAPI_DBG("perv/l20/l21 clocks running now"); + + // ------------------------------- + // Turn on power headers for VCS + // ------------------------------- + + FAPI_TRY(p9_common_poweronoff(i_target, p9power::POWER_ON_VCS)); + + // Because common module raises those fences, we need to lower them here. + FAPI_DBG("Drop vital thold via NET_CTRL0[16]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(16))); + + FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(26))); + + FAPI_DBG("Drop PCB fence via NET_CTRL0[25]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25))); + + // ------------------------------- + // Stop Perv/L20/L21 clocks + // ------------------------------- + + FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); + + FAPI_DBG("Stop perv/l20/l21 clocks via CLK_REGION"); + l_data64 = (p9hcd::CLK_STOP_CMD | l_regions | p9hcd::CLK_THOLD_ARY); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); + + FAPI_DBG("Poll for perv/l20/l21 clocks stopped via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP); + + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECLKSTOP_TIMEOUT() + .set_EQ_TARGET(i_target) + .set_EQCPLTSTAT(l_data64), + "perv/l20/l21 Clock Stop Timeout"); + + FAPI_DBG("Check perv/l20/l21 clocks stopped"); + FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_ARY, l_data64)); + + FAPI_ASSERT((((~l_data64) & l_regions) == 0), + fapi2::PMPROC_CACHECLKSTOP_FAILED() + .set_EQ_TARGET(i_target) + .set_EQCLKSTAT(l_data64), + "perv/l20/l21 Clock Stop Failed"); + FAPI_DBG("perv/l20/l21 clocks stopped now"); + + // ------------------------------- + // Clean up + // ------------------------------- + + FAPI_DBG("Drop Vital clock regional fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(3))); + + FAPI_DBG("Drop Perv/L20/L21 regional fences via CPLT_CTRL1[4,8,9]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, l_regions)); + +fapi_try_exit: + + FAPI_INF("<& i_target); - +#if HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX + fapi2::ReturnCode + p9_hcd_dd1_vcs_workaround( + const fapi2::Target& i_target); +#endif } #endif // __P9_HCD_CACHE_CHIPLET_RESET_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C index e6130a8a..855e66ea 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C @@ -64,6 +64,11 @@ p9_hcd_cache_poweron( { FAPI_INF(">>p9_hcd_cache_poweron"); fapi2::buffer l_data64; +#ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX + fapi2::buffer l_attr_dd1_vcs_workaround; + fapi2::Target l_chip = + i_target.getParent(); +#endif //-------------------------- // Prepare to power on cache @@ -83,7 +88,24 @@ p9_hcd_cache_poweron( //----------------------- FAPI_DBG("Power on cache chiplet"); +#ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX + FAPI_TRY(FAPI_ATTR_GET( + fapi2::ATTR_CHIP_EC_FEATURE_VCS_POWER_ON_IN_CHIPLET_RESET, + l_chip, l_attr_dd1_vcs_workaround)); + + if (l_attr_dd1_vcs_workaround) + { + FAPI_TRY(p9_common_poweronoff(i_target, p9power::POWER_ON_VDD)); + } + else + { + FAPI_TRY(p9_common_poweronoff(i_target, p9power::POWER_ON)); + } + +#else FAPI_TRY(p9_common_poweronoff(i_target, p9power::POWER_ON)); +#endif + fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C index 2ec24c73..3049363f 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C @@ -446,6 +446,7 @@ p9_common_poweronoff( { case p9power::POWER_ON: case p9power::POWER_ON_VDD: + case p9power::POWER_ON_VCS: { // 4.3.8.1 Power-on via Hardware FSM @@ -471,14 +472,17 @@ p9_common_poweronoff( // 2) Set bits to program HW to enable VDD PFET, and // 3) Poll state bit until Pfet sequence is complete - FAPI_TRY(powerOnVdd()); + if (i_operation != p9power::POWER_ON_VCS) + { + FAPI_TRY(powerOnVdd()); + } // 4) Set bits to program HW to enable VCS PFET, and // 5) Poll state bit until Pfet sequence is complete // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work. // Created a POWER_*_VDD label to delineate Vcs and Vdd - if (i_operation == p9power::POWER_ON) + if (i_operation != p9power::POWER_ON_VDD) { FAPI_TRY(powerOnVcs()); } @@ -488,6 +492,7 @@ p9_common_poweronoff( case p9power::POWER_OFF: case p9power::POWER_OFF_VDD: + case p9power::POWER_OFF_VCS: { // 4.3.8.2 Power-off via Hardware FSM // 1) Read PFETCNTLSTAT_REG: check for bits 0:3 being 0b0000 @@ -508,15 +513,17 @@ p9_common_poweronoff( // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work. // Created a POWER_*_VDD label to delineate Vcs and Vdd - if (i_operation == p9power::POWER_OFF) + if (i_operation != p9power::POWER_OFF_VDD) { FAPI_TRY(powerOffVcs()); } // 4) Set bits to program HW to turn off VDD PFET, and // 5) Poll state bit until Pfet sequence is complete - FAPI_TRY(powerOffVdd()); - + if (i_operation != p9power::POWER_OFF_VCS) + { + FAPI_TRY(powerOffVdd()); + } } break; } diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H index 6d529928..56c20414 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H @@ -46,7 +46,9 @@ enum powerOperation_t POWER_ON = 0x0, POWER_OFF = 0xFF, POWER_ON_VDD = 0x1, - POWER_OFF_VDD = 0xFE + POWER_OFF_VDD = 0xFE, + POWER_ON_VCS = 0x2, + POWER_OFF_VCS = 0xFD }; diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H index cb3364d4..75f1c674 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H @@ -171,6 +171,7 @@ enum P9_HCD_CLK_CTRL_CONSTANTS { CLK_STOP_CMD = BIT64(0), CLK_START_CMD = BIT64(1), + CLK_REGION_PERV = BIT64(4), CLK_REGION_ANEP = BIT64(10), CLK_REGION_DPLL = BIT64(14), CLK_REGION_REFR = BITS64(12, 2), @@ -191,7 +192,27 @@ enum P9_HCD_CLK_CTRL_CONSTANTS CLK_REGION_ALL_BUT_PLL = BITS64(4, 10), CLK_REGION_ALL_BUT_PLL_REFR = BITS64(4, 8), CLK_REGION_ALL = BITS64(4, 11), - CLK_THOLD_ALL = BITS64(48, 3) + CLK_THOLD_ALL = BITS64(48, 3), + CLK_THOLD_SL = BIT64(48), + CLK_THOLD_NSL = BIT64(49), + CLK_THOLD_ARY = BIT64(50) +}; + +// Scan Type Constants +enum P9_HCD_SCAN_TYPE_CONSTANTS +{ + SCAN_TYPE_FUNC = BIT64(48), + SCAN_TYPE_CFG = BIT64(49), + SCAN_TYPE_CCFG_GPTR = BIT64(50), + SCAN_TYPE_REGF = BIT64(51), + SCAN_TYPE_LBIST = BIT64(52), + SCAN_TYPE_ABIST = BIT64(53), + SCAN_TYPE_REPR = BIT64(54), + SCAN_TYPE_TIME = BIT64(55), + SCAN_TYPE_BNDY = BIT64(56), + SCAN_TYPE_FARR = BIT64(57), + SCAN_TYPE_CMSK = BIT64(58), + SCAN_TYPE_INEX = BIT64(59) }; // Scan Flush Constants diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 1520a140..88943072 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -181,4 +181,22 @@ + + + ATTR_CHIP_EC_FEATURE_VCS_POWER_ON_IN_CHIPLET_RESET + TARGET_TYPE_PROC_CHIP + + DD1 only: enable VCS workaround in istep4 cache hwp. This is used by + the procedure for p9_hcd_cache_poweron and p9_hcd_cache_chiplet_reset. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + -- cgit v1.2.1