From 1afdc244e2205bd9f8c541a438ae294fe4b6bde9 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Mon, 26 Mar 2018 09:10:49 -0500 Subject: move xlink psave configuration to SBE 55058 added inits to prime the PPE for xlink psave the register touched is in the blacklist, so it can't be touched on slave chips via FSI in the ioe tl SCOM initifle -- this was triggering HW CI failures this commit simply shifts the register setup into the SBE, where it can be performed securely Change-Id: I57504ccfe4c5f7e71397d11c7468da42ec09f059 CQ: SW421691 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56252 Reviewed-by: DANIEL C. HOWE Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56256 Reviewed-by: Sachin Gupta --- .../chips/p9/procedures/hwp/nest/p9_sbe_scominit.C | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'src/import/chips/p9/procedures') diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index 0e2a0854..0664c7f9 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -99,6 +99,13 @@ const uint64_t OB_PPE_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t OB_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL; const uint64_t OB_PPE_FIR_MASK = 0x0E38000000000000ULL; +// FBC XBUS PPE psave constants +const uint8_t PB_PSAVE_CFG_HUT = 0x3; +const uint8_t PB_PSAVE_CFG_LUT = 0x1; +const uint8_t PB_PSAVE_CFG_HUC = 0x1; +const uint8_t PB_PSAVE_CFG_LUC = 0xff; +const uint8_t PB_PSAVE_CFG_WSIZE = 0x1; + // nest trace setup constants const uint8_t N1_PROBE1_SEL = 0x11; @@ -612,9 +619,10 @@ p9_sbe_scominit(const fapi2::Target& i_target) FAPI_TRY(putScom(i_target, PERV_N3_THERM_MODE_REG, l_data)); } - // configure XBUS FIRs + // configure XBUS FIRs & PPE { bool l_xbus_chiplet_good = false; + fapi2::buffer l_psave_cfg; fapi2::buffer l_zero = 0; fapi2::buffer l_ones; l_ones.flush<1>(); @@ -713,6 +721,26 @@ p9_sbe_scominit(const fapi2::Target& i_target) FAPI_TRY(putScom(i_target, PU_PB_IOE_FIR_MASK_REG, (l_xbus_chiplet_good) ? (FBC_IOE_TL_FIR_MASK) : (l_ones())), "Error from putScom (PU_PB_IOE_FIR_MASK_REG)"); + + // PPE psave config + FAPI_TRY(fapi2::getScom(i_target, + PU_PB_PSAVE_CFG, + l_psave_cfg), + "Error from getScom (PU_PB_PSAVE_CFG)"); + + l_psave_cfg.setBit() + .setBit() + .setBit(); + l_psave_cfg.insertFromRight(0x3); + l_psave_cfg.insertFromRight(0x1); + l_psave_cfg.insertFromRight(0x1); + l_psave_cfg.insertFromRight(0xff); + l_psave_cfg.insertFromRight(0x1); + + FAPI_TRY(fapi2::putScom(i_target, + PU_PB_PSAVE_CFG, + l_psave_cfg), + "Error from putScom (PU_PB_PSAVE_CFG)"); } fapi_try_exit: -- cgit v1.2.1