From 63b18ac1cc2cc13ba60eced75f363c5ec3f30ec2 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Fri, 19 May 2017 08:11:55 -0500 Subject: future proof EC feature attributes, add missing P9N DD2 inits redefine EC feature attributes, using inverse logic where required, to qualify inits specific to P9N DD1 where possible, to eliminate need for updates for future chips in plan attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES attributes added to support initial P9NDD2 engineering data -- several spies were not being set as a result ----------------- initfile updates: ----------------- p9.cme.scan.initfile add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes p9.core.common.scan.initfile remove fused core init, it was applying scan default for P9N DD1 and is not needed for P9N DD2+ given fuse controls p9.core.scan.initfile add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and dial programming replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1 and inverse, to pick up initial pass at P9C DD1 inits p9.cxa.scom.initfile add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.ddrphy.scom.initfile add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.dpll.scan.initfile remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS attribute and inverse to drive inits p9.l2.scan.initfile invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes p9.l3.scan.initfile p9.l3.scom.initifle remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes use HW386657, HW396230 attributes to drive inits p9.mca.scom.initfile add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing programming and dial name differences between P9N DD1, P9N DD2 p9.mmu.scan.initfile p9.mmu.scom.initfile invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes p9.ncu.scan.initfile p9.ncu.scom.initifle remove HW396230_SCOM, use HW396230 attribute to drive inits p9.npu.scom.initfile remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification to work for both P9NDD1, P9NDD2 ENGD p9.obus.scan.initfile remove EC qualification of OBUS FIR mask for simulation sample.ec.scan.initfile remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of testcase are covered by other tests ----------------- HWP updates: ----------------- p9_xip_customize add customization of epsilon attributes for NMMU application p9_chiplet_scominit invert definition of P9_NDL_IOVALID feature attribute remove usage of P9N_DD1_SPY_NAMES p9_npu_scominit replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR p9_sbe_tracearray invert definition of CORE_TRACE_SCOMABLE feature attribute p9_sim_get_nia remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes (ok as this HWP is used for VBU sim only and not consumed by FW) Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911 Reviewed-by: SHELTON LEUNG Reviewed-by: LUKE MURRAY Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran Reviewed-by: Matt K. Light Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40915 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../p9/procedures/hwp/initfiles/p9_mmu_scom.C | 28 +++++++++++----------- .../p9/procedures/hwp/perv/p9_sbe_tracearray.C | 10 ++++---- 2 files changed, 19 insertions(+), 19 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp') diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C index 8acd3c72..f1308e10 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C @@ -55,8 +55,8 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target& fapi2::ATTR_NAME_Type l_chip_id; FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id)); FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec)); - fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2)); + fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1)); fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE)); fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1; @@ -67,11 +67,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target& { FAPI_TRY(fapi2::getScom( TGT0, 0x5012c03ull, l_scom_buffer )); - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0)) + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0)) { l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04047C0000000000 ); } - else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0)) + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0)) { l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04247C0000000000 ); } @@ -87,11 +87,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target& { FAPI_TRY(fapi2::getScom( TGT0, 0x5012c07ull, l_scom_buffer )); - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0)) + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0)) { l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x409B000000000000 ); } - else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0)) + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0)) { l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x40FB000000000000 ); } @@ -134,11 +134,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target& { FAPI_TRY(fapi2::getScom( TGT0, 0x5012c43ull, l_scom_buffer )); - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0)) + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0)) { l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAF800FF ); } - else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0)) + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0)) { l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAFC00FB ); } @@ -154,11 +154,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target& { FAPI_TRY(fapi2::getScom( TGT0, 0x5012c47ull, l_scom_buffer )); - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0)) + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0)) { l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x910000040F00 ); } - else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0)) + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0)) { l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x9D1100000F04 ); } @@ -171,11 +171,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target& l_scom_buffer.insert<30, 1, 59, uint64_t>(literal_0b11111 ); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b11111 ); - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0)) + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0)) { l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x00E ); } - else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0)) + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0)) { l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x000 ); } @@ -227,12 +227,12 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target& l_scom_buffer.insert<44, 8, 56, uint64_t>(l_NMMU_MM_MPSS_MODE_MPSS_ENA_PREF_PGSZ_ENA_G_64KB_H_64KB ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0)) + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0)) { constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON = 0x1; l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON ); } - else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0)) + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0)) { constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF = 0x0; l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF ); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C index 4f1e4ca6..8502501c 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C @@ -249,16 +249,16 @@ fapi2::ReturnCode p9_sbe_tracearray( * Check an EC feature to see if that's fixed. */ if (ta_type == fapi2::TARGET_TYPE_CORE) { - uint8_t l_core_trace_scomable = 0; + uint8_t l_core_trace_not_scomable = 0; fapi2::Target proc_target = i_target.getParent(); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE, - proc_target, l_core_trace_scomable), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE, + proc_target, l_core_trace_not_scomable), "Failed to query chip EC feature " - "ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE"); + "ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE"); - if (!l_core_trace_scomable) + if (l_core_trace_not_scomable) { FAPI_ERR("Core arrays cannot be dumped in this chip EC; " "please use fastarray instead."); -- cgit v1.2.1