From 234c3bcaa7cb7dced78d9885be4cebc7ab6b0a3d Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Thu, 29 Dec 2016 15:53:03 -0600 Subject: FIR updates -- pervasive/core/PPE p9_obus_scom_address_fixes.H add OBUS IO PPE address constants p9.cme.scan.initfile align EQ pervasive LFIR/XFIR settings with RAS XML docs p9.core.scan.initfile align EC pervasive LFIR/XFIR settings with RAS XML docs p9.core.scom.initfile p9_hcd_core_scominit.c adjust core FIR action settings for bits 1,12:13 to match RAS XML doc p9_sbe_scominit.C mask PBA FIR bit 1 to match RAS XML doc initialize FBC/XBUS/OBUS PPE FIR registers p9_sbe_common.C align non-EQ/EC pervasive LFIR/XFIR settings with RAS XML docs CMVC-prereq:1014393 CMVC-prereq:1014431 Change-Id: Ifbc6a47eb2dbe268a7ea832e55986d46a1870420 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34271 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran Reviewed-by: Kevin F. Reick Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34336 Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../common/include/p9_obus_scom_addresses_fixes.H | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'src/import/chips/p9/common') diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H index 1cadbddf..fb076562 100644 --- a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H +++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -61,4 +61,32 @@ REG64( OBUS_2_LL2_IOOL_CONTROL, REG64( OBUS_2_LL2_LL2_LL2_PB_IOOL_FIR_REG, RULL(0x0B010800), SH_UNT_OBUS_2, SH_ACS_SCOM ); +REG64( OBUS_0_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x09011046), SH_UNT_OBUS_0, SH_ACS_SCOM ); +REG64( OBUS_0_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x09011047), SH_UNT_OBUS_0, SH_ACS_SCOM ); +REG64( OBUS_0_IOPPE_PPE_FIR_MASK_REG, + RULL(0x09011043), SH_UNT_OBUS_0, SH_ACS_SCOM ); + +REG64( OBUS_1_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x0A011046), SH_UNT_OBUS_1, SH_ACS_SCOM ); +REG64( OBUS_1_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x0A011047), SH_UNT_OBUS_1, SH_ACS_SCOM ); +REG64( OBUS_1_IOPPE_PPE_FIR_MASK_REG, + RULL(0x0A011043), SH_UNT_OBUS_1, SH_ACS_SCOM ); + +REG64( OBUS_2_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x0B011046), SH_UNT_OBUS_2, SH_ACS_SCOM ); +REG64( OBUS_2_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x0B011047), SH_UNT_OBUS_2, SH_ACS_SCOM ); +REG64( OBUS_2_IOPPE_PPE_FIR_MASK_REG, + RULL(0x0B011043), SH_UNT_OBUS_2, SH_ACS_SCOM ); + +REG64( OBUS_3_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x0C011046), SH_UNT_OBUS_3, SH_ACS_SCOM ); +REG64( OBUS_3_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x0C011047), SH_UNT_OBUS_3, SH_ACS_SCOM ); +REG64( OBUS_3_IOPPE_PPE_FIR_MASK_REG, + RULL(0x0C011043), SH_UNT_OBUS_3, SH_ACS_SCOM ); + #endif -- cgit v1.2.1