From 02632c435f420892f94ecf1a39785ed39e6fd62f Mon Sep 17 00:00:00 2001
From: "Sunil.Kumar" <skumar8j@in.ibm.com>
Date: Tue, 1 Dec 2015 06:32:53 -0600
Subject: Makefile Infra

Change-Id: I541cbf57945ab77f7e2575745dc2cc6b839687b5
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22362
Tested-by: Jenkins Server
Reviewed-by: Basabjit Sengupta <basengup@in.ibm.com>
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>
---
 sbe/test/test.xml     | 5 +++++
 sbe/test/testScom.xml | 5 -----
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'sbe/test')

diff --git a/sbe/test/test.xml b/sbe/test/test.xml
index 1b23623a..505a875e 100755
--- a/sbe/test/test.xml
+++ b/sbe/test/test.xml
@@ -18,6 +18,11 @@
               <simcmd>sim->frontend_current_processor = p9Proc0.sbe.ppe</simcmd>
               <exitonerror>yes</exitonerror>
           </testcase>
+          <!-- Workaround to set clock regs. Once simics have fix, we can remove it -->
+          <testcase>
+            <simcmd>p9Proc0.proc_chip.invoke parallel_store LOGIC 0xffc50000 \"00000000_00000001\" 64</simcmd>
+          </testcase>
+      <!-- Write value to a register and than read it back -->
            <!-- Register SBE tools -->
           <testcase>
               <simcmd>run-python-file targets/p9_nimbus/sbeTest/simics-debug-framework.py</simcmd>
diff --git a/sbe/test/testScom.xml b/sbe/test/testScom.xml
index 01228e2a..2e4bf051 100755
--- a/sbe/test/testScom.xml
+++ b/sbe/test/testScom.xml
@@ -1,10 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
 
-      <!-- Workaround to set clock regs. Once simics have fix, we can remove it -->
-      <testcase>
-          <simcmd>p9Proc0.proc_chip.invoke parallel_store LOGIC 0xffc50000 \"00000000_00000001\" 64</simcmd>
-      </testcase>
-      <!-- Write value to a register and than read it back -->
       <testcase>
           <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd>
           <exitonerror>yes</exitonerror>
-- 
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