From fe7353cd3d3658f507cf665f76d45d76f17d528d Mon Sep 17 00:00:00 2001 From: Santosh Puranik Date: Thu, 3 Mar 2016 11:14:15 +0530 Subject: Continuous IPL support Class for register access Beginnings of SBE states RTC: 120752 Change-Id: I6d5ceedd34dc311a352c3d9a638b8fc7f2bef291 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21693 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta Reviewed-by: AMIT J. TENDOLKAR --- sbe/build/simics/sbe_startup.simics | 3 +++ 1 file changed, 3 insertions(+) (limited to 'sbe/build') diff --git a/sbe/build/simics/sbe_startup.simics b/sbe/build/simics/sbe_startup.simics index 15cd9e91..2ada47a1 100755 --- a/sbe/build/simics/sbe_startup.simics +++ b/sbe/build/simics/sbe_startup.simics @@ -7,5 +7,8 @@ try { python "os.environ['SBE_TOOLS_PATH'] = \""+$sbe_script_location+"\"" echo $sbe_script_location; run-python-file (lookup-file sbfw/simics-debug-framework.py) + # Set mailbox scratch registers so that the SBE starts in istep mode + p9Proc0.proc_chip.invoke parallel_store SCOM 0x5003F "20000000_00000000" 64 + p9Proc0.proc_chip.invoke parallel_store SCOM 0x5003A "90000000_00000000" 64 } except { echo "ERROR: Failed to load SBE debug tools." } -- cgit v1.2.1