From c948acbcb058b8fdb062f449106cf99350e8e8c6 Mon Sep 17 00:00:00 2001 From: "Sunil.Kumar" Date: Mon, 28 Sep 2015 05:07:12 -0500 Subject: Level 2 Procedure -p9_sbe_chiplet_init Change-Id: I7d7033599eef969694c60bb0e01fa06f61446061 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20793 Tested-by: Jenkins Server Reviewed-by: Soma Bhanutej Reviewed-by: Jennifer A. Stofer Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21851 Reviewed-by: Amit J. Tendolkar --- .../p9/procedures/hwp/perv/p9_sbe_chiplet_init.C | 99 ++++++++++++++++++++-- .../p9/procedures/hwp/perv/p9_sbe_chiplet_init.H | 16 ++-- .../xml/error_info/p9_sbe_chiplet_init_errors.xml | 31 +++++++ 3 files changed, 128 insertions(+), 18 deletions(-) create mode 100644 import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml (limited to 'import') diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C index 199de527..aeec4823 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C @@ -20,30 +20,111 @@ /// @file p9_sbe_chiplet_init.C /// /// @brief init procedure for all enabled chiplets -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : Email: //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal -// *HWP FW Owner : Brian Silver -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HW Owner : Abhishek Agarwal +// *HWP HW Backup Owner : Srinivas V Naga +// *HWP FW Owner : sunil kumar +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ //## auto_generated #include "p9_sbe_chiplet_init.H" +#include "p9_perv_scom_addresses.H" +#include "p9_perv_sbe_cmn.H" +enum P9_SBE_CHIPLET_INIT_Private_Constants +{ + REGIONS_EXCEPT_VITAL = 0x7FF, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE +}; + +static fapi2::ReturnCode p9_sbe_chiplet_init_scan0_module_function( + const fapi2::Target& i_target_chiplet); + fapi2::ReturnCode p9_sbe_chiplet_init(const fapi2::Target& i_target_chip) { + bool l_read_reg = false; + auto l_perv_functional_vector = + i_target_chip.getChildren + (fapi2::TARGET_STATE_FUNCTIONAL); + fapi2::buffer l_data64; FAPI_DBG("Entering ..."); + for (auto l_chplt_trgt : l_perv_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, + l_attr_chip_unit_pos)); + + if (!((l_attr_chip_unit_pos == 0x07 + || l_attr_chip_unit_pos == 0x08/* McChiplet */) || + (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03 + || l_attr_chip_unit_pos == 0x04 + || l_attr_chip_unit_pos == 0x05/* NestChiplet */) || + (l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A + || l_attr_chip_unit_pos == 0x0B + || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) || + (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E + || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) || + (l_attr_chip_unit_pos == 0x06/* XbusChiplet */))) + { + continue; + } + + FAPI_INF("Call sbe_chiplet_init_scan0_module_function"); + FAPI_TRY(p9_sbe_chiplet_init_scan0_module_function(l_chplt_trgt)); + } + + FAPI_INF("Check for XSTOP Bit"); + //Getting INTERRUPT_TYPE_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, l_data64)); + //l_read_reg = PIB.INTERRUPT_TYPE_REG.CHECKSTOP + l_read_reg = l_data64.getBit<2>(); + + FAPI_ASSERT(!(l_read_reg), + fapi2::CHECKSTOP_ERR() + .set_READ_CHECKSTOP(l_read_reg), + "ERROR:CHECKSTOP BIT GET SET "); + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Scan 0 all rings (except time, repair, gptr) on all enabled chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_init_scan0_module_function( + const fapi2::Target& i_target_chiplet) +{ + bool l_read_reg = false; + fapi2::buffer l_data64; + FAPI_DBG("Entering ..."); + + FAPI_INF("Check for chiplet enable"); + //Getting NET_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); + l_read_reg = l_data64.getBit<0>(); //l_read_reg = NET_CTRL0.CHIPLET_ENABLE + + if ( l_read_reg ) + { + FAPI_INF("run scan0 module for region except vital and scan types except GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, REGIONS_EXCEPT_VITAL, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + } + FAPI_DBG("Exiting ..."); - return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H index 305b5405..f719dc5c 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H @@ -20,15 +20,13 @@ /// @file p9_sbe_chiplet_init.H /// /// @brief init procedure for all enabled chiplets -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : Email: //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal -// *HWP FW Owner : Brian Silver -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HW Owner : Abhishek Agarwal +// *HWP HW Backup Owner : Srinivas V Naga +// *HWP FW Owner : sunil kumar +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ @@ -42,7 +40,7 @@ typedef fapi2::ReturnCode (*p9_sbe_chiplet_init_FP_t)(const fapi2::Target&); -/// @brief Scan 0 all rings (except time, repair, gptr) on all enabled chiplets +/// @brief chiplet init function call on all enabled chiplets /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target /// @return FAPI2_RC_SUCCESS if success, else error code. diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml new file mode 100644 index 00000000..6ed12a0b --- /dev/null +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + RC_CHECKSTOP_ERR + Checkstop error after scan0 + READ_CHECKSTOP + + + -- cgit v1.2.1