From adbbce5842c157dc4ca641d857bf560f7c1842eb Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Fri, 27 May 2016 13:43:53 +0200 Subject: Level 2 HWP for p9_sbe_nest_startclocks,p9_sbe_startclock_chiplets Change-Id: Ife07787240042354d7072f5c4674b14318cb0a71 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25116 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej Reviewed-by: Sunil Kumar Reviewed-by: PARVATHI RACHAKONDA Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25150 Reviewed-by: Sachin Gupta --- .../chips/p9/procedures/hwp/perv/p9_sbe_common.C | 289 +++++++++++++++++ .../chips/p9/procedures/hwp/perv/p9_sbe_common.H | 20 ++ .../procedures/hwp/perv/p9_sbe_nest_startclocks.C | 345 ++------------------- .../hwp/perv/p9_sbe_startclock_chiplets.C | 195 ++++-------- .../xml/attribute_info/p9_sbe_attributes.xml | 3 + .../xml/attribute_info/pervasive_attributes.xml | 8 + .../xml/error_info/p9_sbe_common_errors.xml | 26 +- .../error_info/p9_sbe_nest_startclocks_errors.xml | 28 +- .../p9_sbe_startclock_chiplets_errors.xml | 8 +- 9 files changed, 445 insertions(+), 477 deletions(-) (limited to 'import') diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index 5952d1ee..8c061da1 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -132,6 +132,177 @@ fapi_try_exit: } +/// @brief To do check on Clock controller status for chiplets +/// +/// @param[in] i_target Reference to TARGET_TYPE_PERV target Reference to TARGET_TYPE_PERV target +/// @param[in] i_clock_cmd Issue clock controller command (START/STOP) +/// @param[in] i_regions Enable required REGIONS +/// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_cc_status_function( + const fapi2::Target& i_target, + const fapi2::buffer i_clock_cmd, + const fapi2::buffer i_regions, + const fapi2::buffer i_clock_types) +{ + bool l_reg_sl = false; + bool l_reg_nsl = false; + bool l_reg_ary = false; + fapi2::buffer l_sl_clock_status; + fapi2::buffer l_nsl_clock_status; + fapi2::buffer l_ary_clock_status; + fapi2::buffer l_sl_clkregion_status; + fapi2::buffer l_nsl_clkregion_status; + fapi2::buffer l_ary_clkregion_status; + fapi2::buffer l_regions; + FAPI_INF("Entering ..."); + + l_reg_sl = i_clock_types.getBit<5>(); + l_reg_nsl = i_clock_types.getBit<6>(); + l_reg_ary = i_clock_types.getBit<7>(); + i_regions.extractToRight<5, 11>(l_regions); + + if ( l_reg_sl ) + { + FAPI_DBG("Check for Clocks running SL"); + //Getting CLOCK_STAT_SL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, + l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL + FAPI_DBG("SL Clock status register is %#018lX", l_sl_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_sl_clkregion_status.flush<1>(); + l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); + l_sl_clkregion_status.invert(); + l_sl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_sl_clkregion_status == l_regions, + fapi2::NEST_SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "Clock running for sl type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_sl_clkregion_status.flush<0>(); + l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); + l_sl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_sl_clkregion_status == l_regions, + fapi2::NEST_SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "Clock running for sl type not matching with expected values"); + } + } + + if ( l_reg_nsl ) + { + FAPI_DBG("Check for clocks running NSL"); + //Getting CLOCK_STAT_NSL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, + l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL + FAPI_DBG("NSL Clock status register is %#018lX", l_nsl_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_nsl_clkregion_status.flush<1>(); + l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); + l_nsl_clkregion_status.invert(); + l_nsl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_nsl_clkregion_status == l_regions, + fapi2::NEST_NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "Clock running for nsl type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_nsl_clkregion_status.flush<0>(); + l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); + l_nsl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_nsl_clkregion_status == l_regions, + fapi2::NEST_NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "Clock running for nsl type not matching with expected values"); + } + } + + if ( l_reg_ary ) + { + FAPI_DBG("Check for clocks running ARY"); + //Getting CLOCK_STAT_ARY register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, + l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY + FAPI_DBG("ARY Clock status register is %#018lX", l_ary_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_ary_clkregion_status.flush<1>(); + l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); + l_ary_clkregion_status.invert(); + l_ary_clkregion_status &= l_regions; + + FAPI_ASSERT(l_ary_clkregion_status == l_regions, + fapi2::NEST_ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "Clock running for ary type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_ary_clkregion_status.flush<0>(); + l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); + l_ary_clkregion_status &= l_regions; + + FAPI_ASSERT(l_ary_clkregion_status == l_regions, + fapi2::NEST_ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "Clock running for ary type not matching with expected values"); + } + } + + FAPI_INF("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --check checkstop register +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_checkstop_function( + const fapi2::Target& i_target_chiplet) +{ + fapi2::buffer l_read_reg; + FAPI_INF("Entering ..."); + + FAPI_DBG("Check checkstop register"); + //Getting XFIR register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_XFIR, + l_read_reg)); //l_read_reg = XFIR + + FAPI_ASSERT(l_read_reg == 0, + fapi2::READ_ALL_CHECKSTOP_ERR() + .set_READ_ALL_CHECKSTOP(l_read_reg), + "ERROR: COMBINE ALL CHECKSTOP ERROR"); + + FAPI_INF("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + /// @brief check clocks status /// /// @param[in] i_regions regions from upper level input @@ -363,6 +534,124 @@ fapi_try_exit: } +/// @brief --drop vital fence +/// --reset abstclk muxsel,syncclk_muxsel +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr_pg ATTR_PG for the corresponding chiplet +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( + const fapi2::Target& i_target_chiplet, + const fapi2::buffer i_attr_pg) +{ + // Local variable and constant definition + fapi2::buffer l_cplt_ctrl_init; + fapi2::buffer l_attr_pg; + fapi2::buffer l_data64; + FAPI_INF("Entering ..."); + + l_attr_pg = i_attr_pg; + l_attr_pg.invert(); + l_attr_pg.extractToRight<20, 11>(l_cplt_ctrl_init); + + // Not needed as have only nest chiplet (no dual clock controller) Bit 62 ->0 + // + FAPI_DBG("Drop partial good fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + l_data64.writeBit + (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_cplt_ctrl_init + l_data64.insertFromRight<4, 11>(l_cplt_ctrl_init); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_DBG("reset abistclk_muxsel and syncclk_muxsel"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 + l_data64.setBit(); + //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 + l_data64.setBit(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief will force all chiplets out of flush +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_flushmode(const + fapi2::Target& i_target_chiplet) +{ + fapi2::buffer l_data64; + FAPI_INF("Entering ..."); + + FAPI_DBG("Clear flush_inhibit to go in to flush mode"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 0 + l_data64.setBit(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief get children for all chiplets : Perv, Nest +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[out] o_pg_vector vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_get_pg_vector(const + fapi2::Target& i_target_chip, + fapi2::buffer& o_pg_vector) +{ + fapi2::buffer l_read_attrunitpos; + FAPI_INF("Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chip, + l_read_attrunitpos)); + + if ( l_read_attrunitpos == 0x01 ) + { + o_pg_vector.setBit<0>(); + } + + if ( l_read_attrunitpos == 0x02 ) + { + o_pg_vector.setBit<1>(); + } + + if ( l_read_attrunitpos == 0x03 ) + { + o_pg_vector.setBit<2>(); + } + + if ( l_read_attrunitpos == 0x04 ) + { + o_pg_vector.setBit<3>(); + } + + if ( l_read_attrunitpos == 0x05 ) + { + o_pg_vector.setBit<4>(); + } + + FAPI_INF("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + /// @brief --Setting Scan ratio /// /// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H index 92e97fc6..53aa24cf 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H @@ -40,6 +40,15 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const fapi2::Target& i_target_chiplets); +fapi2::ReturnCode p9_sbe_common_check_cc_status_function( + const fapi2::Target& i_target, + const fapi2::buffer i_clock_cmd, + const fapi2::buffer i_regions, + const fapi2::buffer i_clock_types); + +fapi2::ReturnCode p9_sbe_common_check_checkstop_function( + const fapi2::Target& i_target_chiplet); + fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer i_regions, const fapi2::buffer i_clock_status, @@ -58,6 +67,17 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const const fapi2::buffer i_regions, const fapi2::buffer i_clock_types); +fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( + const fapi2::Target& i_target_chiplet, + const fapi2::buffer i_attr_pg); + +fapi2::ReturnCode p9_sbe_common_flushmode(const + fapi2::Target& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_common_get_pg_vector(const + fapi2::Target& i_target_chip, + fapi2::buffer& o_pg_vector); + fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const fapi2::Target& i_target_chiplets); diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C index 081d6954..4b53c6e2 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C @@ -37,7 +37,6 @@ #include #include -#include #include #include @@ -57,24 +56,9 @@ static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop( const fapi2::Target& i_target_chip, const fapi2::buffer i_pg_vector); -static fapi2::ReturnCode p9_sbe_nest_startclocks_check_cc_status_function( - const fapi2::Target& i_target, - const fapi2::buffer i_clock_cmd, - const fapi2::buffer i_regions, - const fapi2::buffer i_clock_types); - -static fapi2::ReturnCode p9_sbe_nest_startclocks_check_checkstop_function( - const fapi2::Target& i_target_chiplet); - -static fapi2::ReturnCode p9_sbe_nest_startclocks_cplt_ctrl_action_function( - const fapi2::Target& i_target_chiplet); - -static fapi2::ReturnCode p9_sbe_nest_startclocks_flushmode( - const fapi2::Target& i_target_chiplet); - -static fapi2::ReturnCode p9_sbe_nest_startclocks_get_pg_vector( +static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( const fapi2::Target& i_target_chip, - fapi2::buffer& o_pg_vector); + fapi2::buffer& o_attr_pg); static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( const fapi2::Target& i_target_chip, @@ -88,6 +72,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const fapi2::Target& i_target_chip) { uint8_t l_read_attr = 0; + fapi2::buffer l_attr_pg; fapi2::buffer l_pg_vector; fapi2::buffer l_clock_regions; fapi2::buffer l_n3_clock_regions; @@ -99,7 +84,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const (static_cast(fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_TRY(p9_sbe_nest_startclocks_get_pg_vector(l_target_cplt, l_pg_vector)); + FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector)); FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); } @@ -115,7 +100,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); } - FAPI_DBG("Switch MC meshs to Nest mesh"); + FAPI_INF("Reading ATTR_MC_SYNC_MODE "); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); fapi2::TargetFilter l_nest_filter, l_nest_tp_filter; @@ -163,8 +148,10 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const for (auto l_trgt_chplt : i_target_chip.getChildren (l_nest_filter, fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_DBG("Call p9_sbe_nest_startclocks_cplt_ctrl_action_function for Nest and Mc chiplets"); - FAPI_TRY(p9_sbe_nest_startclocks_cplt_ctrl_action_function(l_trgt_chplt)); + FAPI_TRY(p9_sbe_nest_startclocks_get_attr_pg(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Call p9_sbe_common_cplt_ctrl_action_function for Nest and Mc chiplets"); + FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg)); } for (auto l_trgt_chplt : i_target_chip.getChildren @@ -206,15 +193,16 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const FAPI_DBG("Regions value: %#018lX", l_ccstatus_regions); FAPI_DBG("Call clockstatus check function for N0,N1,N2"); - FAPI_TRY(p9_sbe_nest_startclocks_check_cc_status_function(l_trgt_chplt, - CLOCK_CMD, l_ccstatus_regions, CLOCK_TYPES)); + FAPI_TRY(p9_sbe_common_check_cc_status_function(l_trgt_chplt, CLOCK_CMD, + l_ccstatus_regions, CLOCK_TYPES)); } for (auto l_target_cplt : i_target_chip.getChildren (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_TRY(p9_sbe_nest_startclocks_check_cc_status_function(l_target_cplt, - CLOCK_CMD, l_n3_ccstatus_regions, CLOCK_TYPES)); + FAPI_DBG("Call clockstatus check function for N3"); + FAPI_TRY(p9_sbe_common_check_cc_status_function(l_target_cplt, CLOCK_CMD, + l_n3_ccstatus_regions, CLOCK_TYPES)); FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); } @@ -236,14 +224,14 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const for (auto l_trgt_chplt : i_target_chip.getChildren (l_nest_filter, fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_DBG("Call sbe_nest_startclocks_check_checkstop_function for Nest and Mc chiplets "); - FAPI_TRY(p9_sbe_nest_startclocks_check_checkstop_function(l_trgt_chplt)); + FAPI_DBG("Call sbe_common_check_checkstop_function for Nest and Mc chiplets "); + FAPI_TRY(p9_sbe_common_check_checkstop_function(l_trgt_chplt)); } for (auto l_trgt_chplt : i_target_chip.getChildren (l_nest_tp_filter, fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_TRY(p9_sbe_nest_startclocks_flushmode(l_trgt_chplt)); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); } FAPI_INF("Exiting ..."); @@ -253,7 +241,7 @@ fapi_try_exit: } -/// @brief Drop chiplet fence for OB chiplet +/// @brief Drop chiplet fence for N3 chiplet /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target /// @param[in] i_pg_vector Pg vector of targets @@ -267,10 +255,10 @@ static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop( if ( i_pg_vector.getBit<0>() == 1 ) { - FAPI_DBG("Drop chiplet fence"); + FAPI_INF("Drop chiplet fence"); //Setting NET_CTRL0 register value l_data64.flush<1>(); - l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 + l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); } @@ -281,287 +269,18 @@ fapi_try_exit: } -/// @brief To do check on Clock controller status for Nest chiplets -/// -/// @param[in] i_target Reference to TARGET_TYPE_PERV target Reference to TARGET_TYPE_PERV target -/// @param[in] i_clock_cmd Issue clock controller command (START/STOP) -/// @param[in] i_regions Enable required REGIONS -/// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) -/// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_nest_startclocks_check_cc_status_function( - const fapi2::Target& i_target, - const fapi2::buffer i_clock_cmd, - const fapi2::buffer i_regions, - const fapi2::buffer i_clock_types) -{ - bool l_reg_sl = false; - bool l_reg_nsl = false; - bool l_reg_ary = false; - fapi2::buffer l_sl_clock_status; - fapi2::buffer l_nsl_clock_status; - fapi2::buffer l_ary_clock_status; - fapi2::buffer l_sl_clkregion_status; - fapi2::buffer l_nsl_clkregion_status; - fapi2::buffer l_ary_clkregion_status; - fapi2::buffer l_regions; - FAPI_INF("Entering ..."); - - l_reg_sl = i_clock_types.getBit<5>(); - l_reg_nsl = i_clock_types.getBit<6>(); - l_reg_ary = i_clock_types.getBit<7>(); - i_regions.extractToRight<5, 11>(l_regions); - - if ( l_reg_sl ) - { - FAPI_DBG("Check for Clocks running SL"); - //Getting CLOCK_STAT_SL register value - FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, - l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL - FAPI_DBG("SL Clock status register is %#018lX", l_sl_clock_status); - - if ( i_clock_cmd == 0b01 ) - { - FAPI_DBG("Checking for clock start command"); - l_sl_clkregion_status.flush<1>(); - l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); - l_sl_clkregion_status.invert(); - l_sl_clkregion_status &= l_regions; - - FAPI_ASSERT(l_sl_clkregion_status == l_regions, - fapi2::NEST_SL_ERR() - .set_READ_CLK_SL(l_sl_clock_status), - "Clock running for sl type not matching with expected values"); - } - - if ( i_clock_cmd == 0b10 ) - { - FAPI_DBG("Checking for clock stop command"); - l_sl_clkregion_status.flush<0>(); - l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); - l_sl_clkregion_status &= l_regions; - - FAPI_ASSERT(l_sl_clkregion_status == l_regions, - fapi2::NEST_SL_ERR() - .set_READ_CLK_SL(l_sl_clock_status), - "Clock running for sl type not matching with expected values"); - } - } - - if ( l_reg_nsl ) - { - FAPI_DBG("Check for clocks running NSL"); - //Getting CLOCK_STAT_NSL register value - FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, - l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL - FAPI_DBG("NSL Clock status register is %#018lX", l_nsl_clock_status); - - if ( i_clock_cmd == 0b01 ) - { - FAPI_DBG("Checking for clock start command"); - l_nsl_clkregion_status.flush<1>(); - l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); - l_nsl_clkregion_status.invert(); - l_nsl_clkregion_status &= l_regions; - - FAPI_ASSERT(l_nsl_clkregion_status == l_regions, - fapi2::NEST_NSL_ERR() - .set_READ_CLK_NSL(l_nsl_clock_status), - "Clock running for nsl type not matching with expected values"); - } - - if ( i_clock_cmd == 0b10 ) - { - FAPI_DBG("Checking for clock stop command"); - l_nsl_clkregion_status.flush<0>(); - l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); - l_nsl_clkregion_status &= l_regions; - - FAPI_ASSERT(l_nsl_clkregion_status == l_regions, - fapi2::NEST_NSL_ERR() - .set_READ_CLK_NSL(l_nsl_clock_status), - "Clock running for nsl type not matching with expected values"); - } - } - - if ( l_reg_ary ) - { - FAPI_DBG("Check for clocks running ARY"); - //Getting CLOCK_STAT_ARY register value - FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, - l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY - FAPI_DBG("ARY Clock status register is %#018lX", l_ary_clock_status); - - if ( i_clock_cmd == 0b01 ) - { - FAPI_DBG("Checking for clock start command"); - l_ary_clkregion_status.flush<1>(); - l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); - l_ary_clkregion_status.invert(); - l_ary_clkregion_status &= l_regions; - - FAPI_ASSERT(l_ary_clkregion_status == l_regions, - fapi2::NEST_ARY_ERR() - .set_READ_CLK_ARY(l_ary_clock_status), - "Clock running for ary type not matching with expected values"); - } - - if ( i_clock_cmd == 0b10 ) - { - FAPI_DBG("Checking for clock stop command"); - l_ary_clkregion_status.flush<0>(); - l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); - l_ary_clkregion_status &= l_regions; - - FAPI_ASSERT(l_ary_clkregion_status == l_regions, - fapi2::NEST_ARY_ERR() - .set_READ_CLK_ARY(l_ary_clock_status), - "Clock running for ary type not matching with expected values"); - } - } - - FAPI_INF("Exiting ..."); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// @brief --drop chiplet fence -/// --check checkstop register -/// --clear flush inhibit to go into flush mode -/// -/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target -/// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_nest_startclocks_check_checkstop_function( - const fapi2::Target& i_target_chiplet) -{ - fapi2::buffer l_read_reg; - FAPI_INF("Entering ..."); - - FAPI_DBG("Check checkstop register"); - //Getting XFIR register value - FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_XFIR, - l_read_reg)); //l_read_reg = XFIR - - FAPI_ASSERT(l_read_reg == 0, - fapi2::READ_ALL_CHECKSTOP_ERR() - .set_READ_ALL_CHECKSTOP(l_read_reg), - "ERROR: COMBINE ALL CHECKSTOP ERROR"); - - FAPI_INF("Exiting ..."); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// @brief --drop vital fence -/// --reset abstclk muxsel and syncclk muxsel -/// -/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target -/// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_nest_startclocks_cplt_ctrl_action_function( - const fapi2::Target& i_target_chiplet) -{ - // Local variable and constant definition - fapi2::buffer l_attr_pg; - fapi2::buffer l_attr_pg_data; - fapi2::buffer l_data64; - FAPI_INF("Entering ..."); - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); - - l_attr_pg.invert(); - l_attr_pg.extractToRight<20, 11>(l_attr_pg_data); - - FAPI_DBG("Drop partial good fences"); - //Setting CPLT_CTRL1 register value - l_data64.flush<0>(); - //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() - l_data64.writeBit(l_attr_pg.getBit<19>()); - //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_attr_pg_data - l_data64.insertFromRight<4, 11>(l_attr_pg_data); - FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); - - FAPI_DBG("reset abistclk_muxsel and syncclk_muxsel"); - //Setting CPLT_CTRL0 register value - l_data64.flush<0>(); - //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 - l_data64.setBit(); - //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 - l_data64.setBit(); - FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); - - FAPI_INF("Exiting ..."); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// @brief will force all chiplets out of flush -/// -/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target -/// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_nest_startclocks_flushmode( - const fapi2::Target& i_target_chiplet) -{ - fapi2::buffer l_data64; - FAPI_INF("Entering ..."); - - FAPI_DBG("Clear flush_inhibit to go in to flush mode"); - //Setting CPLT_CTRL0 register value - l_data64.flush<0>(); - //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 0 - l_data64.setBit(); - FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); - - FAPI_INF("Exiting ..."); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// @brief get children for all chiplets : Perv, Nest, XB, MC, OB, PCIe +/// @brief get attr_pg for the chiplet /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target -/// @param[out] o_pg_vector vector of targets +/// @param[out] o_attr_pg ATTR_PG for the chiplet /// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_nest_startclocks_get_pg_vector( +static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( const fapi2::Target& i_target_chip, - fapi2::buffer& o_pg_vector) + fapi2::buffer& o_attr_pg) { - fapi2::buffer l_read_attrunitpos; FAPI_INF("Entering ..."); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chip, - l_read_attrunitpos)); - - if ( l_read_attrunitpos == 0x01 ) - { - o_pg_vector.setBit<0>(); - } - - if ( l_read_attrunitpos == 0x02 ) - { - o_pg_vector.setBit<1>(); - } - - if ( l_read_attrunitpos == 0x03 ) - { - o_pg_vector.setBit<2>(); - } - - if ( l_read_attrunitpos == 0x04 ) - { - o_pg_vector.setBit<3>(); - } - - if ( l_read_attrunitpos == 0x05 ) - { - o_pg_vector.setBit<4>(); - } + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chip, o_attr_pg)); FAPI_INF("Exiting ..."); @@ -590,10 +309,10 @@ static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( { if ( i_pg_vector.getBit<4>() == 1 ) { - FAPI_DBG("Drop chiplet fence"); + FAPI_INF("Drop chiplet fence"); //Setting NET_CTRL0 register value l_data64.flush<1>(); - l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 + l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); } } @@ -602,10 +321,10 @@ static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( { if ( i_pg_vector.getBit<2>() == 1 ) { - FAPI_DBG("Drop chiplet fence"); + FAPI_INF("Drop chiplet fence"); //Setting NET_CTRL0 register value l_data64.flush<1>(); - l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 + l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); } } @@ -617,7 +336,7 @@ fapi_try_exit: } -/// @brief Drop chiplet fence for pcie chiplet +/// @brief Drop chiplet fence for N0,N1,N2 chiplet /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target /// @param[in] i_pg_vector Pg vector of targets @@ -631,10 +350,10 @@ static fapi2::ReturnCode p9_sbe_nest_startclocks_nest_fence_drop( if ( i_pg_vector.getBit<4>() == 1 ) { - FAPI_DBG("Drop chiplet fence"); + FAPI_INF("Drop chiplet fence"); //Setting NET_CTRL0 register value l_data64.flush<1>(); - l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 + l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); } diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C index c14d0a57..eef4fb29 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C @@ -50,15 +50,9 @@ enum P9_SBE_STARTCLOCK_CHIPLETS_Private_Constants REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE }; -static fapi2::ReturnCode p9_sbe_startclock_chiplets_check_checkstop_function( - const fapi2::Target& i_target_chiplet); - -static fapi2::ReturnCode p9_sbe_startclock_chiplets_cplt_ctrl_action_function( - const fapi2::Target& i_target_chiplet); - -static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_pg_vector( +static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( const fapi2::Target& i_target_chip, - fapi2::buffer& o_pg_vector); + fapi2::buffer& o_attr_pg); static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop( const fapi2::Target& i_target_chip, @@ -68,6 +62,10 @@ static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop( const fapi2::Target& i_target_chip, const fapi2::buffer i_pg_vector); +static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio( + const fapi2::Target& i_target_chip, + const uint8_t i_attr); + static fapi2::ReturnCode p9_sbe_startclock_chiplets_sync_config( const fapi2::Target& i_target_chiplet); @@ -80,14 +78,26 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const { fapi2::buffer l_pg_vector; fapi2::buffer l_regions; + fapi2::buffer l_attr_obus_ratio; + fapi2::buffer l_attr_pg; FAPI_INF("Entering ..."); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chiplets, + l_attr_obus_ratio)); + + for (auto l_trgt_chplt : i_target_chiplets.getChildren + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_startclock_chiplets_set_ob_ratio(l_trgt_chplt, + l_attr_obus_ratio)); + } + for (auto l_target_cplt : i_target_chiplets.getChildren (static_cast(fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_TRY(p9_sbe_startclock_chiplets_get_pg_vector(l_target_cplt, l_pg_vector)); + FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector)); FAPI_DBG("partial good targets vector: %#018lX", l_pg_vector); } @@ -96,8 +106,10 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_DBG("Call p9_sbe_startclock_chiplets_cplt_ctrl_action_function for xbus, obus, pcie chiplets"); - FAPI_TRY(p9_sbe_startclock_chiplets_cplt_ctrl_action_function(l_trgt_chplt)); + FAPI_TRY(p9_sbe_startclock_chiplets_get_attr_pg(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Call p9_sbe_common_cplt_ctrl_action_function for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg)); FAPI_DBG("Disable listen to sync for all non-master/slave chiplets"); FAPI_TRY(p9_sbe_startclock_chiplets_sync_config(l_trgt_chplt)); @@ -141,92 +153,18 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_DBG("call sbe_startclock_chiplets_check_checkstop_function for xbus, obus, pcie chiplets"); - FAPI_TRY(p9_sbe_startclock_chiplets_check_checkstop_function(l_trgt_chplt)); + FAPI_DBG("call sbe_common_check_checkstop_function for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_check_checkstop_function(l_trgt_chplt)); } - FAPI_INF("Exiting ..."); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// @brief --drop chiplet fence -/// --check checkstop register -/// --clear flush inhibit to go into flush mode -/// -/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target -/// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_startclock_chiplets_check_checkstop_function( - const fapi2::Target& i_target_chiplet) -{ - fapi2::buffer l_read_reg; - fapi2::buffer l_data64; - FAPI_INF("Entering ..."); - - FAPI_DBG("Check checkstop register"); - //Getting XFIR register value - FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_XFIR, - l_read_reg)); //l_read_reg = XFIR - - FAPI_ASSERT(l_read_reg == 0, - fapi2::READ_CHECKSTOP_ERR() - .set_READ_CHECKSTOP(l_read_reg), - "ERROR: COMBINE ALL CHECKSTOP ERROR"); - - FAPI_DBG("Clear flush_inhibit to go in to flush mode"); - //Setting CPLT_CTRL0 register value - l_data64.flush<0>(); - //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 0 - l_data64.setBit(); - FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); - - FAPI_INF("Exiting ..."); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// @brief --drop vital fence -/// --reset abstclk muxsel -/// -/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target -/// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_startclock_chiplets_cplt_ctrl_action_function( - const fapi2::Target& i_target_chiplet) -{ - // Local variable and constant definition - fapi2::buffer l_attr_pg; - fapi2::buffer l_cplt_ctrl_init; - fapi2::buffer l_data64; - FAPI_INF("Entering ..."); - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); - - l_attr_pg.invert(); - l_attr_pg.extractToRight<20, 11>(l_cplt_ctrl_init); - - // Not needed as have only nest chiplet (no dual clock controller) Bit 62 ->0 - // - FAPI_DBG("Drop partial good fences"); - //Setting CPLT_CTRL1 register value - l_data64.flush<0>(); - l_data64.writeBit - (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() - //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_cplt_ctrl_init - l_data64.insertFromRight<4, 11>(l_cplt_ctrl_init); - FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); - - FAPI_DBG("reset abistclk_muxsel and syncclk_muxsel"); - //Setting CPLT_CTRL0 register value - l_data64.flush<0>(); - //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 - l_data64.setBit(); - //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 - l_data64.setBit(); - FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + for (auto l_trgt_chplt : i_target_chiplets.getChildren + (static_cast(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("call sbe_common_flushmode for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); + } FAPI_INF("Exiting ..."); @@ -235,45 +173,18 @@ fapi_try_exit: } -/// @brief get children for all chiplets : Perv, Nest, XB, MC, OB, PCIe +/// @brief get attr_pg for the chiplet /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target -/// @param[out] o_pg_vector vector of targets +/// @param[out] o_attr_pg ATTR_PG for the chiplet /// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_pg_vector( +static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( const fapi2::Target& i_target_chip, - fapi2::buffer& o_pg_vector) + fapi2::buffer& o_attr_pg) { - fapi2::buffer l_read_attrunitpos; FAPI_INF("Entering ..."); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chip, - l_read_attrunitpos)); - - if ( l_read_attrunitpos == 0x01 ) - { - o_pg_vector.setBit<0>(); - } - - if ( l_read_attrunitpos == 0x02 ) - { - o_pg_vector.setBit<1>(); - } - - if ( l_read_attrunitpos == 0x03 ) - { - o_pg_vector.setBit<2>(); - } - - if ( l_read_attrunitpos == 0x04 ) - { - o_pg_vector.setBit<3>(); - } - - if ( l_read_attrunitpos == 0x05 ) - { - o_pg_vector.setBit<4>(); - } + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chip, o_attr_pg)); FAPI_INF("Exiting ..."); @@ -294,7 +205,7 @@ static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop( fapi2::buffer l_data64; FAPI_INF("Entering ..."); - FAPI_DBG("Drop chiplet fence"); + FAPI_INF("Drop chiplet fence"); //Setting NET_CTRL0 register value if (i_pg_vector.getBit<2>() == 1) @@ -324,7 +235,7 @@ static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop( fapi2::buffer l_data64; FAPI_INF("Entering ..."); - FAPI_DBG("Drop chiplet fence"); + FAPI_INF("Drop chiplet fence"); //Setting NET_CTRL0 register value if (i_pg_vector.getBit<3>() == 1) @@ -342,6 +253,30 @@ fapi_try_exit: } +/// @brief set obus ratio +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr Attribute that holds the OBUS ratio value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio( + const fapi2::Target& i_target_chip, + const uint8_t i_attr) +{ + fapi2::buffer l_data64; + FAPI_INF("Entering ..."); + + //Setting CPLT_CONF1 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CPLT_CONF1, l_data64)); + l_data64.insertFromRight<16, 2>(i_attr); //CPLT_CONF1.TC_OB_RATIO_DC = i_attr + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF1, l_data64)); + + FAPI_INF("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + /// @brief Disable listen to sync for all non-master / slave chiplets /// /// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target @@ -376,7 +311,7 @@ static fapi2::ReturnCode p9_sbe_startclock_chiplets_xb_fence_drop( fapi2::buffer l_data64; FAPI_INF("Entering ..."); - FAPI_DBG("Drop chiplet fence"); + FAPI_INF("Drop chiplet fence"); //Setting NET_CTRL0 register value if (i_pg_vector.getBit<1>() == 1) diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index b46f10e6..3804c7db 100644 --- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -625,5 +625,8 @@ ATTR_VITL_CLK_SETUP + + ATTR_OBUS_RATIO_VALUE + diff --git a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index c548b1da..390d2be0 100644 --- a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -695,4 +695,12 @@ + + ATTR_OBUS_RATIO_VALUE + TARGET_TYPE_PROC_CHIP + Holds Obus ratio value + uint8 + + + diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml index 12685941..cdbf36d8 100644 --- a/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml @@ -7,7 +7,7 @@ - + @@ -45,4 +45,28 @@ Chiplet not aligned + + RC_NEST_ARY_ERR + ary_thold status not matching the expected value in clock start stop sequence + READ_CLK_ARY + + + + RC_NEST_NSL_ERR + nsl_thold status not matching the expected value in clock start stop sequence + READ_CLK_NSL + + + + RC_NEST_SL_ERR + sl_thold status not matching the expected value in clock start stop sequence + READ_CLK_SL + + + + RC_READ_ALL_CHECKSTOP_ERR + Read and or all Checkstop error + READ_ALL_CHECKSTOP + + diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml index 51842294..cdece413 100644 --- a/import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml @@ -7,7 +7,7 @@ - + @@ -21,29 +21,5 @@ - - - RC_READ_ALL_CHECKSTOP_ERR - Read and or all Checkstop error - READ_ALL_CHECKSTOP - - - - RC_NEST_SL_ERR - sl_thold status not matching the expected value in clock start stop sequence - READ_CLK_SL - - - - RC_NEST_NSL_ERR - nsl_thold status not matching the expected value in clock start stop sequence - READ_CLK_NSL - - - - RC_NEST_ARY_ERR - ary_thold status not matching the expected value in clock start stop sequence - READ_CLK_ARY - - + diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml index 5324e915..322b385d 100644 --- a/import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml @@ -21,11 +21,5 @@ - - - RC_READ_CHECKSTOP_ERR - Read and or all Checkstop error - READ_CHECKSTOP - - + -- cgit v1.2.1