From 1859c5618995f8c67984373152e5902b9dcc4387 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Sat, 23 Jul 2016 06:54:00 -0500 Subject: scan HWP updates tested via Cronus platform putring implementation p9_sbe_attr_setup p9_setup_sbe_config adjust mailbox write/read logic to properly handle cache contained mode p9_sbe_gptr_time_initf remove unused MC mc_iom[01|23]_time rings add OBUS1/2 scans add PCI pci[0|1|2]_pll_gptr rings add N2 n2_psi_gptr ring p9_sbe_repr_initf remove unused MC mc_iom[01|23]_repr rings add OBUS1/2 scans p9_sbe_nest_initf skip MC iom[01|23]_fure scans which require DETERMINISTIC_TEST_EN p9_sbe_io_initf skip PCI pci[0|1|2]_fure scans which require DETERMINISTIC_TEST_EN remove DETERMINISTIC_TEST_EN application for XB p9_hcd_cache_initf remove explicit initfile invocation/ring caching in wrapper correct putring targeting add EX ex_l2_mode ring scan p9_hcd_core_initf remove explicit initfile invocation/ring caching in wrapper add EC ec_mode ring scan add DBG/ERR trace for all putRing calls remove unused *gptr_time_repr_initf HWPs and wrappers Change-Id: If2e0944c9881cb9d1abc471691bf0242db67ae3f Original-Change-Id: If1f8e9f5b327a6ab4f9b5271c53616ad20163b93 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27400 Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Prachi Gupta Reviewed-by: Kevin F. Reick Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28322 Reviewed-by: Sachin Gupta --- .../hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C | 4 +- .../p9/procedures/hwp/cache/p9_hcd_cache_initf.C | 108 ++++----------------- .../p9/procedures/hwp/core/p9_hcd_core_initf.C | 38 ++------ .../hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C | 105 ++++++++++++++------ .../procedures/hwp/perv/p9_sbe_gptr_time_initf.H | 2 +- .../p9/procedures/hwp/perv/p9_sbe_nest_initf.C | 99 ++++++++++++------- .../p9/procedures/hwp/perv/p9_sbe_repr_initf.H | 2 +- .../hwp/perv/p9_sbe_tp_gptr_time_initf.H | 2 +- .../chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H | 2 +- .../p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H | 2 +- 10 files changed, 175 insertions(+), 189 deletions(-) (limited to 'import/chips') diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C index 96a21ba1..0cf09244 100644 --- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C @@ -51,7 +51,9 @@ fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const uint8_t l_read_attr = 0; FAPI_DBG("Entering ..."); - FAPI_TRY(fapi2::putRing(i_target_chiplet, eq_ana_bndy_l3dcc_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_l3dcc_bucket_26 ring"); + FAPI_TRY(fapi2::putRing(i_target_chiplet, eq_ana_bndy_l3dcc_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_l3dcc_bucket_26)"); FAPI_DBG("Drop L3 DCC bypass"); //Setting NET_CTRL1 register value diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C index 4616a3f1..3eb56747 100644 --- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C @@ -49,20 +49,6 @@ #include "p9_hcd_cache_initf.H" -#ifdef P9_HCD_STOP_SKIP_SCAN - #ifndef __PPE__ - #include - #include - #include - #include - #include - #endif -#endif - -//------------------------------------------------------------------------------ -// Constant Definitions -//------------------------------------------------------------------------------ - //------------------------------------------------------------------------------ // Procedure: EX (non-core) scan init //------------------------------------------------------------------------------ @@ -73,86 +59,30 @@ p9_hcd_cache_initf( { FAPI_INF(">>p9_hcd_cache_initf"); -#ifndef P9_HCD_STOP_SKIP_SCAN - - FAPI_DBG("Scanning Cache FUNC Rings"); - FAPI_TRY(fapi2::putRing(i_target, EQ_FURE, - fapi2::RING_MODE_HEADER_CHECK)); - - FAPI_DBG("Scanning EX L3 FUNC Rings"); - FAPI_TRY(fapi2::putRing(i_target, EX_L3_FURE, - fapi2::RING_MODE_HEADER_CHECK)); - - FAPI_DBG("Scanning EX L2 FUNC Rings"); - FAPI_TRY(fapi2::putRing(i_target, EX_L2_FURE, - fapi2::RING_MODE_HEADER_CHECK)); - - FAPI_DBG("Scanning EX L3 Refresh FUNC Rings"); - FAPI_TRY(fapi2::putRing(i_target, EX_L3_REFR_FURE, - fapi2::RING_MODE_HEADER_CHECK)); - - FAPI_DBG("Scanning Cache Analog FUNC Rings"); - FAPI_TRY(fapi2::putRing(i_target, EQ_ANA_FUNC, - fapi2::RING_MODE_HEADER_CHECK)); -fapi_try_exit: -#else -#ifndef __PPE__ - fapi2::Target FAPI_SYSTEM; - auto l_ex_targets = i_target.getChildren(); - fapi2::ReturnCode l_rc; - - FAPI_EXEC_HWP(l_rc, p9_cme_scan, i_target, FAPI_SYSTEM); + FAPI_DBG("Scan eq_fure ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_fure), + "Error from putRing (eq_fure)"); + FAPI_DBG("Scan eq_ana_func ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_ana_func), + "Error from putRing (eq_ana_func)"); - if (l_rc) + for (auto l_ex_target : i_target.getChildren()) { - FAPI_ERR("Error from p9_cme_scan (p9.cme.scan.initfile)"); - fapi2::current_err = l_rc; - goto fapi_try_exit; - } - - // process configured child EX chiplets - for (auto l_iter = l_ex_targets.begin(); l_iter != l_ex_targets.end(); l_iter++) - { - FAPI_EXEC_HWP(l_rc, p9_core_common_scan, *l_iter, FAPI_SYSTEM); - - if (l_rc) - { - FAPI_ERR("Error from p9_core_common_scan (p9.core.common.scan.initfile)"); - fapi2::current_err = l_rc; - goto fapi_try_exit; - } - - FAPI_EXEC_HWP(l_rc, p9_l3_scan, *l_iter, FAPI_SYSTEM); - - if (l_rc) - { - FAPI_ERR("Error from p9_l3_scan (p9.l3.scan.initfile)"); - fapi2::current_err = l_rc; - goto fapi_try_exit; - } - - FAPI_EXEC_HWP(l_rc, p9_l2_scan, *l_iter, FAPI_SYSTEM); - - if (l_rc) - { - FAPI_ERR("Error from p9_l2_scan (p9.l2.scan.initfile)"); - fapi2::current_err = l_rc; - goto fapi_try_exit; - } - - FAPI_EXEC_HWP(l_rc, p9_ncu_scan, *l_iter, FAPI_SYSTEM); - - if (l_rc) - { - FAPI_ERR("Error from p9_ncu_scan (p9.ncu.scan.initfile)"); - fapi2::current_err = l_rc; - goto fapi_try_exit; - } + FAPI_DBG("Scan ex_l2_fure ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_fure), + "Error from putRing (ex_l2_fure)"); + FAPI_DBG("Scan ex_l2_mode ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_mode), + "Error from putRing (ex_l2_mode)"); + FAPI_DBG("Scan ex_l3_fure ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_fure), + "Error from putRing (ex_l3_fure)"); + FAPI_DBG("Scan ex_l3_refr_fure ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_refr_fure), + "Error from putRing (ex_l3_refr_fure)"); } fapi_try_exit: -#endif -#endif FAPI_INF("< - #endif -#endif - -//----------------------------------------------------------------------------- -// Constant Definitions -//----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Procedure: Core scan init @@ -68,31 +59,14 @@ p9_hcd_core_initf( { FAPI_INF(">>p9_hcd_core_initf"); -#ifndef P9_HCD_STOP_SKIP_SCAN - - FAPI_DBG("Scanning Core FUNC Rings"); - FAPI_TRY(putRing(i_target, EC_FUNC, - fapi2::RING_MODE_HEADER_CHECK)); + FAPI_DBG("Scan ec_func ring"); + FAPI_TRY(putRing(i_target, ec_func), + "Error from putRing (ec_func)"); + FAPI_DBG("Scan ec_mode ring"); + FAPI_TRY(putRing(i_target, ec_mode), + "Error from putRing (ec_mode)"); fapi_try_exit: -#else -#ifndef __PPE__ - fapi2::Target FAPI_SYSTEM; - fapi2::ReturnCode l_rc; - - FAPI_EXEC_HWP(l_rc, p9_core_scan, i_target, FAPI_SYSTEM); - - if (l_rc) - { - FAPI_ERR("Error from p9_core_scan (p9.core.scan.initfile)"); - fapi2::current_err = l_rc; - goto fapi_try_exit; - } - -fapi_try_exit: -#endif -#endif - FAPI_INF("<(); l_data64.clearBit<1>(); FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_14 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_14)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_15 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_15)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_16 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_16)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_17 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_17)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_18 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_18)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_19 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_19)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_20 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_20)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_21 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_21)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_22 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_22)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_23 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_23)"); FAPI_DBG("Release Progdly bypass"); l_data64.flush<1>(); l_data64.clearBit<2>(); FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_24 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_24)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_25 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_25)"); FAPI_DBG("Exiting ..."); fapi_try_exit: diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H index 54a15538..5a048f1d 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H @@ -31,7 +31,7 @@ // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : Sunil Kumar // *HWP Team : Perv -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C index c21ac4d7..434e0137 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C @@ -45,62 +45,91 @@ fapi2::ReturnCode p9_sbe_nest_initf(const fapi2::Target& i_target_chip) { FAPI_INF("Entering ..."); - uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below - fapi2::buffer l_data64; - l_data64.setBit(); + uint8_t l_attr_chip_unit_pos = 0; - for( auto l_chplt_trgt : i_target_chip.getChildren - ( fapi2::TARGET_STATE_FUNCTIONAL)) + for (auto l_chplt_trgt : i_target_chip.getChildren(fapi2::TARGET_STATE_FUNCTIONAL)) { FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); - if ((l_attr_chip_unit_pos == 0x02))/* N0 Chiplet */ + if (l_attr_chip_unit_pos == 0x2)/* N0 Chiplet */ { - FAPI_DBG("Scan N0 chiplet rings"); - FAPI_TRY(fapi2::putRing(i_target_chip, n0_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_fure)); + FAPI_DBG("Scan n0_cxa_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_fure), + "Error from putRing (n0_cxa0_fure)"); + FAPI_DBG("Scan n0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_fure), + "Error from putRing (n0_fure)"); + FAPI_DBG("Scan n0_nx_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_fure), + "Error from putRing (n0_nx_fure)"); } - if ((l_attr_chip_unit_pos == 0x03))/* N1 Chiplet */ + if (l_attr_chip_unit_pos == 0x3)/* N1 Chiplet */ { - FAPI_DBG("Scan N1 chiplet rings"); - FAPI_TRY(fapi2::putRing(i_target_chip, n1_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_fure)); + FAPI_DBG("Scan n1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_fure), + "Error from putRing (n1_fure)"); + FAPI_DBG("Scan n1_ioo0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_fure), + "Error from putRing (n1_ioo0_fure)"); + FAPI_DBG("Scan n1_ioo1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_fure), + "Error from putRing (n1_ioo1_fure)"); + FAPI_DBG("Scan n1_mcs23_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_fure), + "Error from putRing (n1_mcs23_fure)"); } - if ((l_attr_chip_unit_pos == 0x04))/* N2 Chiplet */ + if (l_attr_chip_unit_pos == 0x4)/* N2 Chiplet */ { - FAPI_DBG("Scan N2 chiplet rings"); - FAPI_TRY(fapi2::putRing(i_target_chip, n2_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_fure)); + FAPI_DBG("Scan n2_cxa1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_fure), + "Error from putRing (n2_cxa1_fure)"); + FAPI_DBG("Scan n2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_fure), + "Error from putRing (n2_fure)"); + FAPI_DBG("Scan n2_psi_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_fure), + "Error from putRing (n2_psi_fure)"); } - if ((l_attr_chip_unit_pos == 0x05))/* N3 Chiplet */ + if (l_attr_chip_unit_pos == 0x05)/* N3 Chiplet */ { - FAPI_DBG("Scan N3 chiplet rings"); - FAPI_TRY(fapi2::putRing(i_target_chip, n3_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_fure)); - FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_fure)); + FAPI_DBG("Scan n3_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_fure), + "Error from putRing (n3_fure)"); + FAPI_DBG("Scan n3_mcs01_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_fure), + "Error from putRing (n3_mcs01_fure)"); + FAPI_DBG("Scan n3_np_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_fure), + "Error from putRing (n3_np_fure)"); } } - for( auto l_chplt_trgt : i_target_chip.getChildren - (fapi2::TARGET_STATE_FUNCTIONAL)) + for (auto l_chplt_trgt : i_target_chip.getChildren(fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_DBG("Scan MC chiplet rings"); FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_fure)); - FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_CPLT_CTRL0_OR, l_data64)); - FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_fure)); - FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_fure)); - FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_CPLT_CTRL0_OR, l_data64)); - } +#if 0 + { + // MC IOMxx FURE rings require deterministic scan enable + // no current plan to scan these during mainline IPL, but recipe is below if needed + fapi2::buffer l_data64; + l_data64.setBit(); + FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan mc_iom01_fure ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_fure), + "Error from putRing (mc_iom01_fure)"); + FAPI_DBG("Scan mc_iom23_fure ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_fure), + "Error from putRing (mc_iom23_fure)"); + FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_CLEAR, l_data64)); + } +#endif - FAPI_INF("Exiting ..."); + } fapi_try_exit: + FAPI_INF("Exiting ..."); return fapi2::current_err; } diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H index ce356c3c..b5dbbe99 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H @@ -31,7 +31,7 @@ // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : Sunil Kumar // *HWP Team : Perv -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H index d02294fb..2b99ade3 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H @@ -31,7 +31,7 @@ // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : Sunil Kumar // *HWP Team : Perv -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H index 0ee04d69..abf1f54c 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H @@ -33,7 +33,7 @@ // *HWP HWP Owner : Abhishek Agarwal // *HWP FW Owner : Brian Silver // *HWP Team : Perv -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H index 7cb7497a..134fc853 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H @@ -31,7 +31,7 @@ // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : Sunil Kumar // *HWP Team : Perv -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ -- cgit v1.2.1