From ec9a99e9c39564fc9a69589d2bed3f339b0e86b1 Mon Sep 17 00:00:00 2001 From: Joachim Fenkes Date: Fri, 6 Oct 2017 14:38:51 +0200 Subject: p9_sbe_chiplet_reset: Set VITL_AL flag for MC chiplets There is a phase sync signal between the Nest and MC chiplets that is only needed for combined synchronous LBIST of the inter-chiplet interface, but can disrupt scanning in async MC operation. So it should be masked in normal operation by setting the VITL_AL flag in NET_CTRL0. Change-Id: Ic051943bbb915081b979078d248bf681c7ca5251 CQ: HW422475 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48055 Tested-by: FSP CI Jenkins Tested-by: PPE CI Dev-Ready: LENNARD G. STREAT Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48057 Reviewed-by: Hostboot Team Reviewed-by: Sachin Gupta --- src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 5 +++++ src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 1 + 2 files changed, 6 insertions(+) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index e04d078e..938be1bd 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -363,6 +363,11 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const { FAPI_DBG("Drop clk_div_bypass for Mc chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(targ)); + + //Setting VITL_AL config bit to disable listening to cross-chiplet DDR sync signal + FAPI_DBG("Set VITL_AL for MC chiplet"); + FAPI_TRY(fapi2::putScom(targ, PERV_NET_CTRL0_WOR, + p9SbeChipletReset::NET_CNTL0_SET_VITL_AL)); } } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index 1c4ffd0a..74b105f0 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -63,6 +63,7 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull, NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull, NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull, + NET_CNTL0_SET_VITL_AL = 0x0020000000000000ull, HANG_PULSE_0X10 = 0x10, HANG_PULSE_0X0F = 0x0F, HANG_PULSE_0X06 = 0x06, -- cgit v1.2.1