From e81b1f9a22e0fff681fd48904b30006e17350424 Mon Sep 17 00:00:00 2001 From: "CHRISTINA L. GRAVES" Date: Mon, 18 Jul 2016 14:50:36 -0500 Subject: Adding in writing to HRMOR for bootloader Change-Id: Ib929eff7d946025537cdf7437b4d288490a7fa9d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27230 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Thi N. Tran Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27232 Reviewed-by: Sachin Gupta --- .../procedures/hwp/nest/p9_sbe_load_bootloader.C | 62 ++++++++++++++++++++-- .../chips/p9/procedures/hwp/nest/p9_sbe_scominit.C | 6 +++ .../xml/attribute_info/nest_attributes.xml | 9 ++++ .../xml/attribute_info/p9_sbe_attributes.xml | 4 ++ .../error_info/p9_sbe_load_bootloader_errors.xml | 13 ++++- 5 files changed, 90 insertions(+), 4 deletions(-) diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index a368d5c3..a8c88844 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -38,6 +38,9 @@ #include #include #include +#include +#include +#include //----------------------------------------------------------------------------------- // Constant definitions @@ -47,6 +50,7 @@ const bool PBA_HWP_WRITE_OP = false; const int EXCEPTION_VECTOR_NUM_CACHELINES = 96; const uint32_t SBE_BOOTLOADER_VERSION = 0x901; +const uint8_t PERV_TO_CORE_POS_OFFSET = 0x20; //----------------------------------------------------------------------------------- // Function definitions //----------------------------------------------------------------------------------- @@ -63,6 +67,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader( // 0 6 29 30 31 //bit 30 is for absolute address (since it is not set this is relative) const uint32_t l_branch_to_12 = 0x48003000ull; + const uint32_t C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0 = 18; uint64_t l_bootloader_offset; uint64_t l_hostboot_hrmor_offset; uint64_t l_chip_base_address_nm; @@ -73,11 +78,39 @@ fapi2::ReturnCode p9_sbe_load_bootloader( uint32_t l_num_cachelines_to_roll; uint8_t l_data_to_pass_to_pba_array[FABRIC_CACHELINE_SIZE]; uint32_t l_exception_vector_size = 0; + uint8_t l_master_core = 0; int l_cacheline_num = 0; p9_PBA_oper_flag l_myPbaFlag; + fapi2::buffer l_dataBuf; + fapi2::Target l_coreTarget; + bool l_coreFoundMatch = false; FAPI_DBG("Start"); + //Find the master core for writing the HRMOR later + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MASTER_CORE, i_master_chip_target, l_master_core), "Error getting ATTR_MASTER_CORE"); + + for ( auto l_current_core : i_master_ex_target.getChildren()) + { + uint8_t l_attr_chip_unit_pos = 0; + fapi2::Target l_perv = l_current_core.getParent(); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos), + "Error getting ATTR_CHIP_UNIT_POS"); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - PERV_TO_CORE_POS_OFFSET; + FAPI_DBG("l_attr_chip_unit_pos = %d, l_attr_chip_unit_pos = %d, l_master_core = %d", l_attr_chip_unit_pos, + l_attr_chip_unit_pos, l_master_core); + + if (l_attr_chip_unit_pos == l_master_core) + { + l_coreTarget = l_current_core; + l_coreFoundMatch = true; + break; + } + } + + FAPI_ASSERT(l_coreFoundMatch, fapi2::P9_MASTER_CORE_NOT_FOUND().set_CHIP_TARGET(i_master_chip_target).set_EX_TARGET( + i_master_ex_target).set_MASTER_CORE(l_master_core) , "Error in finding the master core"); + // read platform initialized attributes needed to determine target base address FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOTLOADER_OFFSET, FAPI_SYSTEM, l_bootloader_offset), "Error from FAPI_ATTR_GET (ATTR_SBE_BOOTLOADER_OFFSET)"); @@ -147,9 +180,6 @@ fapi2::ReturnCode p9_sbe_load_bootloader( // Pass size of load including exception vectors and Bootloader l_bootloader_config_data.blLoadSize = l_exception_vector_size + i_payload_size; - - - // move data using PBA setup/access HWPs l_myPbaFlag.setFastMode(true); // FASTMODE l_myPbaFlag.setOperationType(p9_PBA_oper_flag::LCO); // LCO operation @@ -255,6 +285,32 @@ fapi2::ReturnCode p9_sbe_load_bootloader( } } + { + //instantiate the basic RamCore class + RamCore ram(l_coreTarget, 0); + + //Set the HRMOR + //Override PM_EXIT on master core bit 4 is for core 0 bit 5 is for core 1 + if (l_master_core % 2 == 0) + { + l_dataBuf.flush<0>().setBit(); + } + else + { + l_dataBuf.flush<0>().setBit(); + } + + FAPI_TRY(fapi2::putScom(i_master_ex_target, EX_0_CME_SCOM_SICR_SCOM2, l_dataBuf), + "Error overriding PM_EXIT"); + //Set ram_thread_active for t0 + l_dataBuf.flush<0>().setBit(); + FAPI_TRY(fapi2::putScom(l_coreTarget, C_0_THREAD_INFO, l_dataBuf), + "Error setting thread active for t0"); + l_dataBuf.flush<0>().insertFromRight<0, 64>(l_chip_base_address_nm); + //call RamCore put_reg method + FAPI_TRY(ram.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR"); + } + fapi_try_exit: FAPI_DBG("End"); return fapi2::current_err; diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index c7d5e3ec..cd837128 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -51,6 +51,7 @@ fapi2::ReturnCode p9_sbe_scominit(const { i_id_struct l_id_struct; uint64_t l_attr_xscom_bar_addr = 0; + uint64_t l_attr_lpc_base_addr = 0; fapi2::buffer l_data64; auto l_perv_functional_vector = i_target.getChildren (fapi2::TARGET_STATE_FUNCTIONAL); @@ -65,6 +66,7 @@ fapi2::ReturnCode p9_sbe_scominit(const l_id_struct.iv_system_id)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ADU_XSCOM_BAR_BASE_ADDR, i_target, l_attr_xscom_bar_addr)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_LPC_BASE_ADDR, i_target, l_attr_lpc_base_addr), "Error getting the LPC_BASE_ADDR"); for (auto l_target_chplt : l_perv_functional_vector) { @@ -117,6 +119,10 @@ fapi2::ReturnCode p9_sbe_scominit(const FAPI_TRY(fapi2::putScom(i_target, PU_XSCOM_BASE_REG, l_data64)); + // Setting LPC BASE ADDR register value + l_data64 = l_attr_lpc_base_addr; + FAPI_TRY(fapi2::putScom(i_target, PU_LPC_BASE_REG, l_data64)); + FAPI_DBG("Exiting ..."); fapi_try_exit: diff --git a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 479bcbf9..2662c9da 100644 --- a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -698,6 +698,15 @@ + + ATTR_LPC_BASE_ADDR + TARGET_TYPE_PROC_CHIP + Defines LPC base address on each processor level. + uint64 + + + + ATTR_MEM_MIRROR_PLACEMENT_POLICY TARGET_TYPE_SYSTEM diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index ce579484..6816ba25 100644 --- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -358,6 +358,10 @@ ATTR_ADU_XSCOM_BAR_BASE_ADDR 0x000603FC00000000 + + ATTR_LPC_BASE_ADDR + 0x0006030000000000 + ATTR_SUN_ID 0x01 diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml index 352659d6..b5c65d77 100755 --- a/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml @@ -7,7 +7,7 @@ - + @@ -44,4 +44,15 @@ PAYLOAD_SIZE + + RC_P9_MASTER_CORE_NOT_FOUND + + Procedure: p9_sbe_load_bootloader + The master core is not found from the ex master target + + CHIP_TARGET + EX_TARGET + MASTER_CORE + + -- cgit v1.2.1