From c5b050b3838dc314df4dca8f8406a48a09e52c4e Mon Sep 17 00:00:00 2001 From: Yue Du Date: Thu, 13 Apr 2017 19:24:22 -0500 Subject: IPL: Add global checkstop FIR check in Istep4 Change-Id: I01071130bcb020c020b7af6a72b0f736a3a07f69 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39241 Reviewed-by: Michael S. Floyd Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: AMIT KUMAR Reviewed-by: Gregory S. Still Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39242 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../hwp/cache/p9_hcd_cache_startclocks.C | 36 ++++++++++++---- .../procedures/hwp/core/p9_hcd_core_startclocks.C | 48 +++++++++++++++------- 2 files changed, 62 insertions(+), 22 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C index 4a8eaafe..5d50a6c3 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -111,6 +111,15 @@ p9_hcd_cache_startclocks( i_target.getChildren (fapi2::TARGET_STATE_FUNCTIONAL); +#ifndef __PPE__ + + uint8_t l_attr_is_simulation; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, l_sys, + l_attr_is_simulation)); + +#endif + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys, l_attr_system_ipl_phase)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, l_sys, @@ -332,14 +341,25 @@ p9_hcd_cache_startclocks( // Cleaning up // ------------------------------- - /// @todo RTC158181 ignore xstop checkstop in sim, review for lab - /* - FAPI_DBG("Check the Global Checkstop FIR"); - FAPI_TRY(getScom(i_target, EQ_XFIR, l_data64)); - FAPI_ASSERT(((l_data64 & BITS64(0, 27)) != 0), - fapi2::PMPROC_CACHE_XSTOP().set_EQXFIR(l_data64), - "Cache Chiplet Checkstop"); - */ +#ifndef __PPE__ + + // ignore xstop checkstop in sim + if (!l_attr_is_simulation) + { + +#endif + + FAPI_DBG("Check the Global Checkstop FIR of Cache Chiplet"); + FAPI_TRY(getScom(i_target, EQ_XFIR, l_data64)); + FAPI_ASSERT(((l_data64 & BITS64(0, 27)) == 0), + fapi2::PMPROC_CACHE_XSTOP().set_EQXFIR(l_data64), + "Cache Chiplet Checkstop"); + +#ifndef __PPE__ + + } + +#endif if (!l_attr_dd1_skip_flushmode_inhibit_drop) { diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C index c3a71b23..844e3064 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -102,6 +102,20 @@ p9_hcd_core_startclocks( i_target.getParent(); const fapi2::Target l_sys; +#ifndef __PPE__ + + uint8_t l_attr_is_simulation; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, l_sys, + l_attr_is_simulation)); + +#endif + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RUNN_MODE, l_sys, + l_attr_runn_mode)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys, + l_attr_system_ipl_phase)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip, l_attr_sdisn_setup)); @@ -112,12 +126,7 @@ p9_hcd_core_startclocks( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip, l_attr_system_id)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RUNN_MODE, l_sys, - l_attr_runn_mode)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys, - l_attr_system_ipl_phase)); - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos)); l_attr_chip_unit_pos = (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET) % 4; @@ -283,14 +292,25 @@ p9_hcd_core_startclocks( FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(18))); } - /// @todo RTC158181 ignore xstop checkstop in sim, review for lab - /* - FAPI_DBG("Check the Global Checkstop FIR"); - FAPI_TRY(getScom(i_target, C_XFIR, l_data64)); - FAPI_ASSERT(((l_data64 & BITS64(0, 27)) != 0), - fapi2::PMPROC_CORE_XSTOP().set_COREXFIR(l_data64), - "Core Chiplet Checkstop"); - */ +#ifndef __PPE__ + + // ignore xstop checkstop in sim + if (!l_attr_is_simulation && !l_attr_runn_mode) + { + +#endif + + FAPI_DBG("Check the Global Checkstop FIR of Core Chiplet"); + FAPI_TRY(getScom(i_target, C_XFIR, l_data64)); + FAPI_ASSERT(((l_data64 & BITS64(0, 27)) == 0), + fapi2::PMPROC_CORE_XSTOP().set_COREXFIR(l_data64), + "Core Chiplet Checkstop"); + +#ifndef __PPE__ + + } + +#endif FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_SET(2))); -- cgit v1.2.1