From b082595cb830528514b4f33b9b24fdcc675b8665 Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Mon, 23 Jan 2017 07:05:58 +0100 Subject: Control NDL training update Change-Id: I13d721d7fb1d71c58314dd1e09006a7b4df0dee2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35211 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35216 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../p9/procedures/hwp/perv/p9_sbe_attr_setup.C | 67 ++++++++++++++-------- .../p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 65 +++++++++++++++++++++ .../xml/attribute_info/p9_sbe_attributes.xml | 4 ++ .../xml/attribute_info/pervasive_attributes.xml | 11 +++- 4 files changed, 122 insertions(+), 25 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index 46436dae..beb24596 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -43,39 +43,49 @@ enum P9_SETUP_SBE_CONFIG_scratch4 { - // Scratch4 reg bit definitions - ATTR_OBUS_RATIO_VALUE_BIT = 21, - ATTR_EQ_GARD_STARTBIT = 0, - ATTR_EQ_GARD_LENGTH = 6, - ATTR_EC_GARD_STARTBIT = 8, - ATTR_EC_GARD_LENGTH = 24, - ATTR_I2C_BUS_DIV_REF_STARTBIT = 0, - ATTR_I2C_BUS_DIV_REF_LENGTH = 16, - ATTR_BOOT_FLAGS_STARTBIT = 0, - ATTR_BOOT_FLAGS_LENGTH = 32, - ATTR_PUMP_CHIP_IS_GROUP = 23, - ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26, - ATTR_PROC_FABRIC_GROUP_ID_LENGTH = 3, - ATTR_PROC_FABRIC_CHIP_ID_STARTBIT = 29, - ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3, - ATTR_CC_IPL_BIT = 0, - ATTR_INIT_ALL_CORES_BIT = 1, - ATTR_RISK_LEVEL_BIT = 2, - ATTR_DISABLE_HBBL_VECTORS_BIT = 3, - ATTR_MC_SYNC_MODE_BIT = 4, - ATTR_PLL_MUX_STARTBIT = 12, - ATTR_PLL_MUX_LENGTH = 20, - - // Scratch4 reg bit definitions + // Scratch_reg_1 + ATTR_EQ_GARD_STARTBIT = 0, + ATTR_EQ_GARD_LENGTH = 6, + ATTR_EC_GARD_STARTBIT = 8, + ATTR_EC_GARD_LENGTH = 24, + + // Scratch_reg_2 + ATTR_I2C_BUS_DIV_REF_STARTBIT = 0, + ATTR_I2C_BUS_DIV_REF_LENGTH = 16, + ATTR_NDL_MESHCTRL_SETUP_STARTBIT = 16, + ATTR_NDL_MESHCTRL_SETUP_LENGTH = 4, + + // Scratch_reg_3 + ATTR_BOOT_FLAGS_STARTBIT = 0, + ATTR_BOOT_FLAGS_LENGTH = 32, + + // Scratch_reg_4 ATTR_BOOT_FREQ_MULT_STARTBIT = 0, ATTR_BOOT_FREQ_MULT_LENGTH = 16, ATTR_NEST_PLL_BUCKET_STARTBIT = 24, ATTR_NEST_PLL_BUCKET_LENGTH = 8, + ATTR_OBUS_RATIO_VALUE_BIT = 21, ATTR_CP_FILTER_BYPASS_BIT = 16, ATTR_SS_FILTER_BYPASS_BIT = 17, ATTR_IO_FILTER_BYPASS_BIT = 18, ATTR_DPLL_BYPASS_BIT = 19, ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT = 20, + + // Scratch_reg_5 + ATTR_PLL_MUX_STARTBIT = 12, + ATTR_PLL_MUX_LENGTH = 20, + ATTR_CC_IPL_BIT = 0, + ATTR_INIT_ALL_CORES_BIT = 1, + ATTR_RISK_LEVEL_BIT = 2, + ATTR_DISABLE_HBBL_VECTORS_BIT = 3, + ATTR_MC_SYNC_MODE_BIT = 4, + + // Scratch_reg_6 + ATTR_PUMP_CHIP_IS_GROUP = 23, + ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26, + ATTR_PROC_FABRIC_GROUP_ID_LENGTH = 3, + ATTR_PROC_FABRIC_CHIP_ID_STARTBIT = 29, + ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3, }; fapi2::ReturnCode p9_sbe_attr_setup(const @@ -180,6 +190,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); + + l_read_scratch_reg.extractToRight<16, 4>(l_read_1); + + FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_read_1)); } else { @@ -188,7 +203,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const FAPI_DBG("Reading ATTR_I2C_BUS_DIV_REF"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); + FAPI_DBG("Reading ATTR_NDL_MESHCTRL_SETUP"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_read_1)); + l_read_scratch_reg.insertFromRight< ATTR_I2C_BUS_DIV_REF_STARTBIT, ATTR_I2C_BUS_DIV_REF_LENGTH >(l_read_4); + l_read_scratch_reg.insertFromRight< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >(l_read_1); FAPI_DBG("Setting up value of Scratch_reg2"); //Setting SCRATCH_REGISTER_2 register value diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 5e42a5dc..5965b556 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -120,12 +120,16 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0( static fapi2::ReturnCode p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup( const fapi2::Target& i_target_chip); +static fapi2::ReturnCode p9_sbe_chiplet_reset_meshctrl_setup( + const fapi2::Target& i_target_chiplet, bool value); + fapi2::ReturnCode p9_sbe_chiplet_reset(const fapi2::Target& i_target_chip) { // Local variable uint8_t l_mc_sync_mode = 0; uint8_t l_pll_bypass = 0; + fapi2::buffer l_read_attr; #ifndef __PPE__ fapi2::Target l_sys; uint8_t l_attr_system_ipl_phase; @@ -255,6 +259,32 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const } } + FAPI_DBG("Meshctrl setup"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, + l_read_attr)); + + for (auto& targ : l_perv_func_WO_Core_Cache) + { + uint32_t l_chipletID = targ.getChipletNumber(); + + if (l_chipletID == 9) + { + FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<4>())); + } + else if (l_chipletID == 10) + { + FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<5>())); + } + else if (l_chipletID == 11) + { + FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<6>())); + } + else if (l_chipletID == 12) + { + FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<7>())); + } + } + FAPI_DBG("Sector buffer strength and pulse mode setup"); // MC XBUS OBUS PCI @@ -455,6 +485,41 @@ fapi_try_exit: } +/// @brief meshctrl setup +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] value 0 or 1 to be written into perv_net_ctrl1 reg +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_meshctrl_setup( + const fapi2::Target& i_target_chiplet, bool value) +{ + fapi2::buffer l_data; + FAPI_INF("p9_sbe_chiplet_reset_meshctrl_setup: Entering ..."); + + if ( value ) + { + l_data.flush<0>(); + l_data.setBit<21>(); + + FAPI_DBG("Meshctrl setup"); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WOR, l_data)); + } + else + { + l_data.flush<1>(); + l_data.clearBit<21>(); + + FAPI_DBG("Meshctrl setup"); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data)); + + } + + FAPI_INF("p9_sbe_chiplet_reset_meshctrl_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; +} + /// @brief Setting up hang pulse counter for all parital good chiplet except for Tp /// /// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index f2c305b6..fcc56a95 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -455,5 +455,9 @@ attribute tank ATTR_IS_SP_MODE 0x0 + + ATTR_NDL_MESHCTRL_SETUP + 0x0 + diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index ebbc87b1..c59e0699 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -5,7 +5,7 @@ - + @@ -688,4 +688,13 @@ + + ATTR_NDL_MESHCTRL_SETUP + TARGET_TYPE_PROC_CHIP + Control NDL training:meshctrl setup + uint8 + + + + -- cgit v1.2.1