From 8e3010da46a16c4bdcc196e6a2ed89e3c599a6c8 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Fri, 27 May 2016 08:51:42 -0500 Subject: L2 HWP -- p9_setup_bars p9_setup_bars initial relase -- program FSP/PSI/NPU BARs & configure MCD nest_attributes proc_setup_bars_attributes adjust scope of BAR base address attributes from chip->system change to reflect offset from base of chip address range, rather than absolute address p9_fbc_utils modify p9_fbc_utils_get_chip_base_address() to output base of each on chip region, consider policy affecting placement of mirrrored memory p9_mss_eff_grouping p9_sbe_load_bootloader p9_sbe_mcs_setup adapt to p9_fbc_utils_get_chip_base_address() changes p9_sbe_scominit adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes add placeholder for FIR register initialization p9_pcie_config adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes skip programming of INT resources Change-Id: I62e1766fbe8366168cc3f1b9b43c64f48659aec0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27841 Tested-by: Jenkins Server Reviewed-by: Peng Fei Gou Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27849 Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C | 43 +- import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H | 16 +- .../procedures/hwp/nest/p9_sbe_load_bootloader.C | 29 +- .../p9/procedures/hwp/nest/p9_sbe_mcs_setup.C | 13 +- .../chips/p9/procedures/hwp/nest/p9_sbe_scominit.C | 468 +++++++++++++++------ .../chips/p9/procedures/hwp/nest/p9_sbe_scominit.H | 94 ++--- .../xml/attribute_info/nest_attributes.xml | 29 +- .../xml/attribute_info/p9_sbe_attributes.xml | 12 + .../xml/error_info/p9_sbe_scominit_errors.xml | 25 ++ 9 files changed, 507 insertions(+), 222 deletions(-) diff --git a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C index 265a7e13..4c9e3a12 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C +++ b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -88,8 +88,9 @@ const uint8_t FABRIC_ADDR_SS_GROUP_ID_END_BIT = 18; // chip ID (large system) const uint8_t FABRIC_ADDR_LS_CHIP_ID_START_BIT = 19; const uint8_t FABRIC_ADDR_LS_CHIP_ID_END_BIT = 21; -// msel bit (large & small system) -const uint8_t FABRIC_ADDR_MSEL_BIT = 13; +// msel bits (large & small system) +const uint8_t FABRIC_ADDR_MSEL_START_BIT = 13; +const uint8_t FABRIC_ADDR_MSEL_END_BIT = 14; //------------------------------------------------------------------------------ @@ -157,14 +158,16 @@ fapi_try_exit: fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( const fapi2::Target& i_target, - uint64_t& o_base_address_nm, - uint64_t& o_base_address_m) + uint64_t& o_base_address_nm0, + uint64_t& o_base_address_nm1, + uint64_t& o_base_address_m, + uint64_t& o_base_address_mmio) { uint32_t l_fabric_system_id; uint8_t l_fabric_group_id; uint8_t l_fabric_chip_id; uint8_t l_fabric_addr_bar_mode; - uint8_t l_msel; + uint8_t l_mirror_policy; fapi2::buffer l_base_address; const fapi2::Target FAPI_SYSTEM; @@ -182,7 +185,7 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, FAPI_SYSTEM, l_fabric_addr_bar_mode), "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_msel), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy), "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)"); // apply system ID @@ -230,19 +233,29 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( } // set output addresses based on application of msel - if (l_msel == fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) + if (l_mirror_policy == fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) { - // nm = 0b00, m = 0b10 - o_base_address_nm = l_base_address(); - l_base_address.setBit(FABRIC_ADDR_MSEL_BIT); - o_base_address_m = l_base_address(); + // nm = 0b00/01, m = 0b10, mmio = 0b11 + o_base_address_nm0 = l_base_address(); // 00 + l_base_address.setBit(); + o_base_address_nm1 = l_base_address(); // 01 + l_base_address.setBit(); + l_base_address.clearBit(); + o_base_address_m = l_base_address(); // 10 + l_base_address.setBit(FABRIC_ADDR_MSEL_END_BIT); + o_base_address_mmio = l_base_address(); // 11 } else { - // m = 0b10, m = 0b00 - o_base_address_m = l_base_address(); - l_base_address.setBit(FABRIC_ADDR_MSEL_BIT); - o_base_address_nm = l_base_address(); + // nm = 0b01/10, m = 0b00, mmio = 0b11 + o_base_address_m = l_base_address(); // 00 + l_base_address.setBit(); + o_base_address_nm0 = l_base_address(); // 01 + l_base_address.setBit(); + l_base_address.clearBit(); + o_base_address_nm1 = l_base_address(); // 10 + l_base_address.setBit(); + o_base_address_mmio = l_base_address(); // 11 } fapi_try_exit: diff --git a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index 55f3dbb8..af73102e 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -88,17 +88,21 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop( const fapi2::Target& i_target); /// -/// @brief Return base address origin (non-mirrored/mirrored) for this chip +/// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip /// -/// @param[in] i_target Reference to processor chip target -/// @param[out] o_base_address_nm Non-mirrored base address for this chip -/// @param[out] o_base_address_m Mirrored base address for this chip +/// @param[in] i_target Reference to processor chip target +/// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip +/// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip +/// @param[out] o_base_address_m Mirrored base address for this chip +/// @param[out] o_base_address_mmio MMIO base address for this chip /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. /// fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( const fapi2::Target& i_target, - uint64_t& o_base_address_nm, - uint64_t& o_base_address_m); + uint64_t& o_base_address_nm0, + uint64_t& o_base_address_nm1, + uint64_t& o_base_address_m, + uint64_t& o_base_address_mmio); #endif // _P9_FBC_UTILS_H_ diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index ba238852..6c6ae300 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -76,8 +76,9 @@ fapi2::ReturnCode p9_sbe_load_bootloader( const uint32_t C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0 = 18; uint64_t l_bootloader_offset; uint64_t l_hostboot_hrmor_offset; - uint64_t l_chip_base_address_nm; + uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1; uint64_t l_chip_base_address_m; + uint64_t l_chip_base_address_mmio; uint64_t l_target_address; uint32_t l_exception_instruction; bool l_firstAccess = true; @@ -128,20 +129,22 @@ fapi2::ReturnCode p9_sbe_load_bootloader( // (hostboot HRMOR offset) + // (bootloader offset) FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target, - l_chip_base_address_nm, - l_chip_base_address_m), + l_chip_base_address_nm0, + l_chip_base_address_nm1, + l_chip_base_address_m, + l_chip_base_address_mmio), "Error from p9_fbc_utils_get_chip_base_address"); // add hostboot HRMOR offset and bootloader offset contributions - l_chip_base_address_nm += l_hostboot_hrmor_offset; - l_chip_base_address_nm += l_bootloader_offset; + l_chip_base_address_nm0 += l_hostboot_hrmor_offset; + l_chip_base_address_nm0 += l_bootloader_offset; // check that base address is cacheline aligned - FAPI_ASSERT(!(l_chip_base_address_nm % FABRIC_CACHELINE_SIZE), + FAPI_ASSERT(!(l_chip_base_address_nm0 % FABRIC_CACHELINE_SIZE), fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS(). set_CHIP_TARGET(i_master_chip_target). set_EX_TARGET(i_master_ex_target). - set_TARGET_BASE_ADDRESS(l_chip_base_address_nm). + set_TARGET_BASE_ADDRESS(l_chip_base_address_nm0). set_HRMOR_OFFSET(l_hostboot_hrmor_offset). set_BOOTLOADER_OFFSET(l_bootloader_offset), "Target base address is not cacheline aligned!"); @@ -151,7 +154,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT, FAPI_SYSTEM, l_exception_instruction), "fapiGetAttribute of ATTR_SBE_HBBL_EXCEPTION_INSTRUCT failed!"); - l_target_address = l_chip_base_address_nm; + l_target_address = l_chip_base_address_nm0; BootloaderConfigData_t l_bootloader_config_data; @@ -190,7 +193,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader( l_myPbaFlag.setFastMode(true); // FASTMODE l_myPbaFlag.setOperationType(p9_PBA_oper_flag::LCO); // LCO operation - while (l_target_address < (l_chip_base_address_nm + i_payload_size + l_exception_vector_size)) + while (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)) { // invoke PBA setup HWP to prep stream FAPI_TRY(p9_pba_setup( i_master_chip_target, @@ -204,7 +207,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader( // call PBA access HWP per cacheline to move payload data while (l_num_cachelines_to_roll && - (l_target_address < (l_chip_base_address_nm + i_payload_size + l_exception_vector_size))) + (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size))) { if ((l_cacheline_num == 0) && (l_exception_instruction != 0)) { @@ -278,8 +281,8 @@ fapi2::ReturnCode p9_sbe_load_bootloader( l_myPbaFlag.setFlag(), l_firstAccess, (l_num_cachelines_to_roll == 1) || - ((l_target_address + FABRIC_CACHELINE_SIZE) >= - (l_chip_base_address_nm + i_payload_size + l_exception_vector_size)), + ((l_target_address + FABRIC_CACHELINE_SIZE) > + (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)), l_data_to_pass_to_pba_array), "Error from p9_pba_access"); l_firstAccess = false; // decrement count of cachelines remaining in current stream @@ -312,7 +315,7 @@ fapi2::ReturnCode p9_sbe_load_bootloader( l_dataBuf.flush<0>().setBit(); FAPI_TRY(fapi2::putScom(l_coreTarget, C_0_THREAD_INFO, l_dataBuf), "Error setting thread active for t0"); - l_dataBuf.flush<0>().insertFromRight<0, 64>(l_chip_base_address_nm); + l_dataBuf.flush<0>().insertFromRight<0, 64>(l_chip_base_address_nm0); //call RamCore put_reg method FAPI_TRY(ram.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR"); } diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C index cf160b39..1fe5dc4f 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C +++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C @@ -144,8 +144,7 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target(); auto l_mi_chiplets = i_target.getChildren(); @@ -170,20 +169,22 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target +/// @author Christy Graves +/// + +// +// *HWP HWP Owner: Joe McGill +// *HWP FW Owner: Thi Tran +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// + //------------------------------------------------------------------------------ -// *HWP HW Owner : Girisankar Paulraj -// *HWP HW Backup Owner : Joe McGill -// *HWP FW Owner : Thi N. Tran -// *HWP Team : Nest -// *HWP Level : 2 -// *HWP Consumed by : SBE +// Includes //------------------------------------------------------------------------------ +#include +#include + +#include +#include +#include -//## auto_generated -#include "p9_sbe_scominit.H" +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ -#include "p9_misc_scom_addresses.H" -#include "p9_perv_scom_addresses.H" +// XSCOM/LPC BAR constants +const uint64_t XSCOM_BAR_MASK = 0xFF000003FFFFFFFFULL; +const uint64_t LPC_BAR_MASK = 0xFF000000FFFFFFFFULL; +// FBC FIR constants +const uint64_t FBC_CENT_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t FBC_CENT_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_CENT_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_WEST_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t FBC_WEST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_WEST_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_EAST_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t FBC_EAST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_EAST_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; -static fapi2::ReturnCode p9_sbe_scominit_chiplet_cnfg(const - fapi2::Target& i_target_chip, - const i_id_struct& iv_id_struct); +// PBA FIR constants +const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t PBA_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t PBA_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; -fapi2::ReturnCode p9_sbe_scominit(const - fapi2::Target& i_target) +// chiplet pervasive FIR constants +const uint64_t PERV_LFIR_ACTION0[15] = { - i_id_struct l_id_struct; - uint64_t l_attr_xscom_bar_addr = 0; - uint64_t l_attr_lpc_base_addr = 0; - fapi2::buffer l_data64; - auto l_perv_functional_vector = i_target.getChildren - (fapi2::TARGET_STATE_FUNCTIONAL); + 0x0000000000000000ULL, // TP + 0x0000000000000000ULL, // N0 + 0x0000000000000000ULL, // N1 + 0x0000000000000000ULL, // N2 + 0x0000000000000000ULL, // N3 + 0x0000000000000000ULL, // X + 0x0000000000000000ULL, // - + 0x0000000000000000ULL, // - + 0x0000000000000000ULL, // OB0 + 0x0000000000000000ULL, // OB1 + 0x0000000000000000ULL, // OB2 + 0x0000000000000000ULL, // OB3 + 0x0000000000000000ULL, // PCI0 + 0x0000000000000000ULL, // PCI1 + 0x0000000000000000ULL // PCI2 +}; +const uint64_t PERV_LFIR_ACTION1[15] = +{ + 0x0000000000000000ULL, // TP + 0xFFFFFFFFFFFFFFFFULL, // N0 + 0xFFFFFFFFFFFFFFFFULL, // N1 + 0xFFFFFFFFFFFFFFFFULL, // N2 + 0xFFFFFFFFFFFFFFFFULL, // N3 + 0xFFFFFFFFFFFFFFFFULL, // X + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // OB0 + 0xFFFFFFFFFFFFFFFFULL, // OB1 + 0xFFFFFFFFFFFFFFFFULL, // OB2 + 0xFFFFFFFFFFFFFFFFULL, // OB3 + 0xFFFFFFFFFFFFFFFFULL, // PCI0 + 0xFFFFFFFFFFFFFFFFULL, // PCI1 + 0xFFFFFFFFFFFFFFFFULL // PCI2 +}; + +const uint64_t PERV_LFIR_MASK[15] = +{ + 0xFFFFFFFFFFFFFFFFULL, // TP + 0xFFFFFFFFFFFFFFFFULL, // N0 + 0xFFFFFFFFFFFFFFFFULL, // N1 + 0xFFFFFFFFFFFFFFFFULL, // N2 + 0xFFFFFFFFFFFFFFFFULL, // N3 + 0xFFFFFFFFFFFFFFFFULL, // X + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // OB0 + 0xFFFFFFFFFFFFFFFFULL, // OB1 + 0xFFFFFFFFFFFFFFFFULL, // OB2 + 0xFFFFFFFFFFFFFFFFULL, // OB3 + 0xFFFFFFFFFFFFFFFFULL, // PCI0 + 0xFFFFFFFFFFFFFFFFULL, // PCI1 + 0xFFFFFFFFFFFFFFFFULL // PCI2 +}; + +// chiplet XIR constants +const uint64_t PERV_XFIR_MASK[15] = +{ + 0xFFFFFFFFFFFFFFFFULL, // TP + 0xFFFFFFFFFFFFFFFFULL, // N0 + 0xFFFFFFFFFFFFFFFFULL, // N1 + 0xFFFFFFFFFFFFFFFFULL, // N2 + 0xFFFFFFFFFFFFFFFFULL, // N3 + 0xFFFFFFFFFFFFFFFFULL, // X + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // OB0 + 0xFFFFFFFFFFFFFFFFULL, // OB1 + 0xFFFFFFFFFFFFFFFFULL, // OB2 + 0xFFFFFFFFFFFFFFFFULL, // OB3 + 0xFFFFFFFFFFFFFFFFULL, // PCI0 + 0xFFFFFFFFFFFFFFFFULL, // PCI1 + 0xFFFFFFFFFFFFFFFFULL // PCI2 +}; + + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_sbe_scominit(const fapi2::Target& i_target) + +{ FAPI_DBG("Entering ..."); + fapi2::Target FAPI_SYSTEM; + uint64_t l_base_addr_nm0; + uint64_t l_base_addr_nm1; + uint64_t l_base_addr_m; + uint64_t l_base_addr_mmio; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, - l_id_struct.iv_chip_id)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, - l_id_struct.iv_group_id)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, - l_id_struct.iv_system_id)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ADU_XSCOM_BAR_BASE_ADDR, i_target, - l_attr_xscom_bar_addr)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_LPC_BASE_ADDR, i_target, l_attr_lpc_base_addr), "Error getting the LPC_BASE_ADDR"); - - for (auto l_target_chplt : l_perv_functional_vector) + // set fabric topology information in each pervasive chiplet (outside of EC/EP) { - uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_target_chplt, - l_attr_chip_unit_pos)); + // read fabric topology attributes + uint32_t l_fbc_system_id; + uint8_t l_fbc_group_id; + uint8_t l_fbc_chip_id; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fbc_system_id), + "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_SYSTEM_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fbc_group_id), + "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_GROUP_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fbc_chip_id), + "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_CHIP_ID)"); - if ((l_attr_chip_unit_pos & 0xF0) == 0) + for (auto l_chplt_target : i_target.getChildren + (static_cast(fapi2::TARGET_FILTER_TP | + fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI), + fapi2::TARGET_STATE_FUNCTIONAL)) { - FAPI_TRY(p9_sbe_scominit_chiplet_cnfg(l_target_chplt, l_id_struct)); + fapi2::buffer l_cplt_conf0; + FAPI_TRY(fapi2::getScom(l_chplt_target, PERV_CPLT_CONF0, l_cplt_conf0), + "Error from getScom (PERV_CPLT_CONF0)"); + l_cplt_conf0.insertFromRight + (l_fbc_system_id) + .insertFromRight(l_fbc_group_id) + .insertFromRight(l_fbc_chip_id); + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_CPLT_CONF0, l_cplt_conf0), + "Error from putScom (PERV_CPLT_CONF0)"); } } - // Clearing and masking the Local Power bus, Fabric bus and N3 chiplet FIRs/MASK/ACTION registers - //Setting FIR_MASK register value - //N3.FIR_MASK = p9SbeScominit::FIRMASK_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, 0x05040002, - p9SbeScominit::FIRMASK_RESET_VALUE)); - //Setting LOCAL_FIR_ACTION0 register value - //N3.LOCAL_FIR_ACTION0 = p9SbeScominit::FIRACT_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, PERV_N3_LOCAL_FIR_ACTION0, - p9SbeScominit::FIRACT_RESET_VALUE)); - //Setting LOCAL_FIR_ACTION1 register value - //N3.LOCAL_FIR_ACTION1 = p9SbeScominit::FIRACT_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, PERV_N3_LOCAL_FIR_ACTION1, - p9SbeScominit::FIRACT_RESET_VALUE)); - //Setting XFIR register value - //N3.XFIR = p9SbeScominit::FIR_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, 0x05040000, p9SbeScominit::FIR_RESET_VALUE)); - //Setting PBAFIRMASK register value - //N3.PBAFIRMASK = p9SbeScominit::FIRMASK_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRMASK, - p9SbeScominit::FIRMASK_RESET_VALUE)); - //Setting PBAFIRACT0 register value - //N3.PBAFIRACT0 = p9SbeScominit::FIRACT_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT0, - p9SbeScominit::FIRACT_RESET_VALUE)); - //Setting PBAFIRACT1 register value - //N3.PBAFIRACT1 = p9SbeScominit::FIRACT_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT1, - p9SbeScominit::FIRACT_RESET_VALUE)); - //Setting PBAFIR register value - //N3.PBAFIR = p9SbeScominit::FIR_RESET_VALUE - FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIR, p9SbeScominit::FIR_RESET_VALUE)); - - // Setting ADU XSCOM BASE ADDR register value - l_data64 = l_attr_xscom_bar_addr; - l_data64.clearBit<0, 8>(); - l_data64.clearBit<30, 34>(); - - FAPI_TRY(fapi2::putScom(i_target, PU_XSCOM_BASE_REG, l_data64)); - - // Setting LPC BASE ADDR register value - l_data64 = l_attr_lpc_base_addr; - FAPI_TRY(fapi2::putScom(i_target, PU_LPC_BASE_REG, l_data64)); + // determine base address of chip nm/m/mmmio regions in real address space + FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, + l_base_addr_nm0, + l_base_addr_nm1, + l_base_addr_m, + l_base_addr_mmio), + "Error from p9_fbc_utils_get_chip_base_address"); - FAPI_DBG("Exiting ..."); + // set XSCOM BAR + { + fapi2::buffer l_xscom_bar; + uint64_t l_xscom_bar_offset; -fapi_try_exit: - return fapi2::current_err; + FAPI_DBG("Configuring XSCOM BAR"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_xscom_bar_offset), + "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)"); -} + l_xscom_bar = l_base_addr_mmio; + l_xscom_bar += l_xscom_bar_offset; -/// @brief This function configures Fabric chip/system/group ID for functioning chiplet -/// -/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target -/// @param[in] i_id_struct This structure contains the following parameter -/// i_chip_id --> current chiplet Fabric chip id -/// i_group_id --> current chiplet Fabric group id -/// i_system_id --> current chiplet Fabric system id -/// @return FAPI2_RC_SUCCESS if success, else error code. -static fapi2::ReturnCode p9_sbe_scominit_chiplet_cnfg(const - fapi2::Target& i_target_chip, - const i_id_struct& i_id_struct) -{ - fapi2::buffer l_data64; - FAPI_DBG("Entering ..."); + FAPI_ASSERT((l_xscom_bar & XSCOM_BAR_MASK) == 0, + fapi2::P9_SBE_SCOMINIT_XSCOM_BAR_ATTR_ERR(). + set_TARGET(i_target). + set_XSCOM_BAR(l_xscom_bar). + set_XSCOM_BAR_OFFSET(l_xscom_bar_offset). + set_BASE_ADDR_MMIO(l_base_addr_mmio), + "Invalid XSCOM BAR configuration!"); + + FAPI_TRY(fapi2::putScom(i_target, PU_XSCOM_BASE_REG, l_xscom_bar), + "Error from putScom (PU_XSCOM_BASE_REG)"); + } - //Setting CPLT_CONF0 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CPLT_CONF0, l_data64)); - //CPLT_CONF0.TC_UNIT_GROUP_ID_DC = i_id_struct.iv_group_id - l_data64.insertFromRight<48, 4>(i_id_struct.iv_group_id); - //CPLT_CONF0.TC_UNIT_CHIP_ID_DC = i_id_struct.iv_chip_id - l_data64.insertFromRight<52, 3>(i_id_struct.iv_chip_id); - //CPLT_CONF0.TC_UNIT_SYS_ID_DC = i_id_struct.iv_system_id - l_data64.insertFromRight<56, 5>(i_id_struct.iv_system_id); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0, l_data64)); + // set LPC BAR + { + fapi2::buffer l_lpc_bar; + uint64_t l_lpc_bar_offset; - FAPI_DBG("Exiting ..."); + FAPI_DBG("Configuring LPC BAR"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_lpc_bar_offset), + "Error from FAPI_ATTR_GET (ATRR_PROC_LPC_BAR_BASE_ADDR_OFFSET"); + + l_lpc_bar = l_base_addr_mmio; + l_lpc_bar += l_lpc_bar_offset; + + FAPI_ASSERT((l_lpc_bar & LPC_BAR_MASK) == 0, + fapi2::P9_SBE_SCOMINIT_LPC_BAR_ATTR_ERR(). + set_TARGET(i_target). + set_LPC_BAR(l_lpc_bar). + set_LPC_BAR_OFFSET(l_lpc_bar_offset). + set_BASE_ADDR_MMIO(l_base_addr_mmio), + "Invalid LPC BAR configuration!"); + + FAPI_TRY(fapi2::putScom(i_target, PU_LPC_BASE_REG, l_lpc_bar), + "Error from putScom (PU_LPC_BASE_REG)"); + } + + // configure FBC FIRs + { + fapi2::buffer l_scom_data; + + // CENT + FAPI_DBG("Configuring FBC CENT FIR"); + // clear FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_REG)"); + + // configure action/mask + l_scom_data = FBC_CENT_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG)"); + + l_scom_data = FBC_CENT_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG)"); + + l_scom_data = FBC_CENT_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG)"); + + // WEST + FAPI_DBG("Configuring FBC WEST FIR"); + // clear FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_REG)"); + + // configure action/mask + l_scom_data = FBC_WEST_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG)"); + + l_scom_data = FBC_WEST_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG)"); + + l_scom_data = FBC_WEST_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG)"); + + // EAST + FAPI_DBG("Configuring FBC EAST FIR"); + // clear FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_REG)"); + + // configure action/mask + l_scom_data = FBC_EAST_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_ACTION0_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_ACTION0_REG)"); + + l_scom_data = FBC_EAST_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_ACTION1_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_ACTION1_REG)"); + + l_scom_data = FBC_EAST_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_MASK_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_MASK_REG)"); + } + + // configure PBA FIRs + { + fapi2::buffer l_scom_data; + + // clear FIR + FAPI_DBG("Configuring PBA FIR"); + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIR, l_scom_data), + "Error from putScom (PU_PBAFIR)"); + + // configure action/mask + l_scom_data = PBA_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT0, l_scom_data), + "Error from putScom (PU_PBAFIRACT0)"); + + l_scom_data = PBA_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT1, l_scom_data), + "Error from putScom (PU_PBAFIRACT1)"); + + l_scom_data = PBA_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRMASK, l_scom_data), + "Error from putScom (PU_PBAFIRMASK)"); + } + + // configure chiplet pervasive FIRs / XFIRs + { + for (auto l_chplt_target : i_target.getChildren + (static_cast(fapi2::TARGET_FILTER_TP | + fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + uint8_t l_unit_idx; + fapi2::buffer l_scom_data; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_target, l_unit_idx), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + l_unit_idx--; + + + // PERV LFIR + FAPI_DBG("Configuring PERV LFIR (chiplet ID: %02X)", l_unit_idx + 1); + // reset pervasive FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR)"); + + // configure pervasive FIR action/mask + l_scom_data = PERV_LFIR_ACTION0[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION0, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_ACTION0)"); + + l_scom_data = PERV_LFIR_ACTION1[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION1, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_ACTION1)"); + + l_scom_data = PERV_LFIR_MASK[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_MASK, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_MASK)"); + + // XFIR + FAPI_DBG("Configuring chiplet XFIR (chiplet ID: %02X)", l_unit_idx + 1); + // reset XFIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_XFIR, l_scom_data), + "Error from putScom (PERV_XFIR)"); + + // configure XFIR mask + l_scom_data = PERV_XFIR_MASK[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_FIR_MASK, l_scom_data), + "Error from putScom (PERV_FIR_MASK"); + } + } fapi_try_exit: + FAPI_DBG("Exiting ..."); return fapi2::current_err; } - -i_id_struct::i_id_struct() : iv_chip_id(0), iv_group_id(0), iv_system_id(0) -{ -} diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H b/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H index 99714ae2..4129098e 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H +++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H @@ -22,77 +22,57 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -//------------------------------------------------------------------------------ -/// @file p9_sbe_scominit.H /// -/// @brief This procedure contains SCOM based initialization required for -/// fabric configuration & HBI operation -/// *! -/// *! o Set fabric node/chip ID configuration for all configured -/// *! chiplets to chip specific values -/// *! o Establish ADU XSCOM BAR for HBI operation -//------------------------------------------------------------------------------ -// *HWP HW Owner : Girisankar Paulraj -// *HWP HW Backup Owner : Joe McGill -// *HWP FW Owner : Thi N. Tran -// *HWP Team : Nest -// *HWP Level : 2 -// *HWP Consumed by : SBE -//------------------------------------------------------------------------------ +/// @file p9_sbe_scominit.H +/// @brief Peform SCOM initialization required for fabric & HBI operation (FAPI2) +/// +/// @author Joe McGill +/// @author Christy Graves +/// +// +// *HWP HWP Owner : Joe McGill +// *HWP FW Owner : Thi N. Tran +// *HWP Team : Nest +// *HWP Level : 2 +// *HWP Consumed by : SBE +// #ifndef _P9_SBE_SCOMINIT_H_ #define _P9_SBE_SCOMINIT_H_ - +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ #include -namespace p9SbeScominit -{ -enum P9_SBE_SCOMINIT_Public_Constants -{ - FIR_RESET_VALUE = 0x0000000000000000ull, - FIRMASK_RESET_VALUE = 0xFFFFFFFFFFFFFFFFull, - FIRACT_RESET_VALUE = 0xFFFFFFFFFFFFFFFFull -}; -} - -typedef fapi2::ReturnCode (*p9_sbe_scominit_FP_t)(const - fapi2::Target&); - -/// @brief This function does ADU BAR and XSCOM BAR base setup, -/// Set Fabric node/chip ID for all configured chiplets in nest -/// area and Clearing/setting up FIR register -/// -/// @param[in] i_target Reference to TARGET_TYPE_PROC_CHIP target -/// @return FAPI2_RC_SUCCESS if success, else error code. -extern "C" -{ - fapi2::ReturnCode p9_sbe_scominit(const - fapi2::Target& i_target); -} - -// This structure contains the following parameter -// i_chip_id --> current chiplet Fabric chip id -// i_group_id --> current chiplet Fabric group id -// i_system_id --> current chiplet Fabric system id -struct i_id_struct -{ - //// Constructors and destructors //// +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ - public : +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_scominit_FP_t)(const fapi2::Target&); - //## auto_generated - i_id_struct(); - //// Attributes //// +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ - uint8_t iv_chip_id; +extern "C" +{ - uint8_t iv_group_id; +/// +/// @brief Set fabric topology IDs for all configured chipets (outside of EC/EP), +/// performs BAR setup needed for HBI (XSCOM/LPC), configures selected FIRs in +/// preparation for fabric init +/// an init command (ttype=pbop.init_all) from the Alter Display Unit (ADU) +/// +/// @param[in] i_target Reference to processor chip target +/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// + fapi2::ReturnCode p9_sbe_scominit(const fapi2::Target& i_target); - uint32_t iv_system_id; -}; +} // extern "C" #endif diff --git a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 0c12fe00..56afc909 100644 --- a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -695,19 +695,34 @@ - ATTR_ADU_XSCOM_BAR_BASE_ADDR - TARGET_TYPE_PROC_CHIP - Defines XSCOM base address on each processor level. - address provided by the MRW + ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET + TARGET_TYPE_SYSTEM + XSCOM BAR base address offset + creator: platform + consumer: p9_sbe_scominit + firmware notes: + Defines 16GB range (size implied) mapped for XSCOM usage + Attribute holds offset (relative to chip MMIO origin) to program into + chip address range field of BAR -- RA bits 22:29 + (excludes system/memory select/group/chip fields) + uint64 - ATTR_LPC_BASE_ADDR - TARGET_TYPE_PROC_CHIP - Defines LPC base address on each processor level. + ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET + TARGET_TYPE_SYSTEM + LPC BAR base address offset + creator: platform + consumer: p9_sbe_scominit + firmware notes: + Defines 4GB range (size implied) mapped for LPC usage + Attribute holds offset (relative to chip MMIO origin) to program into + chip address range field of BAR -- RA bits 22:31 + (excludes system/memory select/group/chip fields) + uint64 diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 96d72a93..4972e342 100644 --- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -510,4 +510,16 @@ attribute tank ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING + + + ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET + 0x000003FC00000000 + + + + ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET + 0x000003FB00000000 + + + diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml index 0cac2485..97226c2d 100644 --- a/import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml @@ -24,4 +24,29 @@ + + + RC_P9_SBE_SCOMINIT_XSCOM_BAR_ATTR_ERR + + Procedure: p9_sbe_scominit + Invalid XSCOM BAR attribute configuration + + TARGET + XSCOM_BAR + XSCOM_BAR_OFFSET + BASE_ADDR_MMIO + + + + RC_P9_SBE_SCOMINIT_LPC_BAR_ATTR_ERR + + Procedure: p9_sbe_scominit + Invalid LPC BAR attribute configuration + + TARGET + LPC_BAR + LPC_BAR_OFFSET + BASE_ADDR_MMIO + + -- cgit v1.2.1