From 7d4a70e5f5dcebe147370396025d6fe774f0dbf4 Mon Sep 17 00:00:00 2001 From: Sachin Gupta Date: Mon, 1 Aug 2016 01:34:16 -0500 Subject: Reset fapi2::current_err Change-Id: I16d926b7213089494393014e8fd611e0750d7c9e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27677 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS Reviewed-by: Shakeeb A. Pasha B K Reviewed-by: AMIT J. TENDOLKAR --- sbe/sbefw/sbecmdprocessor.C | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sbe/sbefw/sbecmdprocessor.C b/sbe/sbefw/sbecmdprocessor.C index 0f3f90b4..969367c0 100644 --- a/sbe/sbefw/sbecmdprocessor.C +++ b/sbe/sbefw/sbecmdprocessor.C @@ -44,6 +44,7 @@ #include "sbecmdiplcontrol.H" #include "sberegaccess.H" #include "sbestates.H" +#include "fapi2.H" ///////////////////////////////////////////////////////////////////// @@ -272,6 +273,12 @@ void sbeSyncCommandProcessor_routine(void *i_pArg) uint8_t l_cmdClass = 0; uint8_t l_cmdOpCode = 0; + // Reset the value of fapi2::current_err from previous value. + // This is required as none of procedure set this value in success + // case. So if we do not reset previous value, previous failure + // will impact new chipops also. + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + // Check on the Rx Thread Interrupt Bits for Interrupt Status if ( g_sbeIntrSource.isSet(SBE_RX_ROUTINE, SBE_INTERFACE_PSU) ) -- cgit v1.2.1