From 701c3b882d41c4193e20dc620a4c8cd4fa66b463 Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Thu, 21 Jan 2016 13:57:15 +0100 Subject: Level 2 HWP for p9_setup_clock_term Also included wrap files and makefiles Change-Id: I228028a5af319ebda4343e5cf39b3f2618162470 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23474 Tested-by: Jenkins Server Dev-Ready: Brent Wieman Reviewed-by: Manish K. Chowdhary Reviewed-by: Sunil Kumar Reviewed-by: Parvathi Rachakonda Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48500 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta --- .../p9/procedures/hwp/perv/p9_setup_clock_term.H | 49 ++++++++++++++++------ 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H b/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H index 5b6b1baa..77913892 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H @@ -25,16 +25,14 @@ //------------------------------------------------------------------------------ /// @file p9_setup_clock_term.H /// -/// @brief proc setup clock term -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : Email: +/// @brief Setup the clock termination correctly for system/chip type //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal -// *HWP FW Owner : Brian Silver -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HW Owner : Anusha Reddy Rangareddygari +// *HWP HW Backup Owner : Srinivas V Naga +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : FSP:HB //------------------------------------------------------------------------------ @@ -45,18 +43,43 @@ #include +namespace p9SetupClockTerm +{ +enum P9_SETUP_CLOCK_TERM_Public_Constants +{ + OSCSWITCH_RC3 = 0x0080C000, + OSCSWITCH_RC4 = 0x0 +}; +} + +typedef enum { BOTH_SRC0, BOTH_SRC1, SRC0, SRC1, SRC_NONE } pci_clk_req_enum; + +// pci_clk_req_enum enumarated data type with allowed PCI refclock configurations +// BOTH_SRC0: redundant PCI clock available, SRC0 configured as primary source +// BOTH_SRC1: redundant PCI clock available, SRC1 configured as primary source +// SRC0: redundant PCI clock but forced to use SRC0 only as other clock may be garded/deconfigured +// SRC1: redundant PCI clock but forced to use SRC1 only as other clock may be garded/deconfigured +// SRC_NONE: non-redundant PCI clock setup + + + typedef fapi2::ReturnCode (*p9_setup_clock_term_FP_t)(const - fapi2::Target&); + fapi2::Target&, const pci_clk_req_enum); -/// @brief Setup the clock termination correctly for system/chip type -/// Since this is the first procedure run against the chips it also clears the GP write protect +/// @brief Setup the clock termination correctly, since this is the first procedure run against the chips it also clears the GP write protect /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +// pci_clk_req_enum enumarated data type with allowed PCI refclock configurations +// BOTH_SRC0: redundant PCI clock available, SRC0 configured as primary source +// BOTH_SRC1: redundant PCI clock available, SRC1 configured as primary source +// SRC0: redundant PCI clock but forced to use SRC0 only as other clock may be garded/deconfigured +// SRC1: redundant PCI clock but forced to use SRC1 only as other clock may be garded/deconfigured +// SRC_NONE: non-redundant PCI clock setup /// @return FAPI2_RC_SUCCESS if success, else error code. extern "C" { fapi2::ReturnCode p9_setup_clock_term(const - fapi2::Target& i_target_chip); + fapi2::Target& i_target_chip, const pci_clk_req_enum i_pci_clk_req); } #endif -- cgit v1.2.1