From 6124b03a2ec4471dfae9f07129ff64cdb1b6cc44 Mon Sep 17 00:00:00 2001 From: Thi Tran Date: Fri, 23 Sep 2016 14:56:59 -0500 Subject: Fix MCFGP table look up when MCA is garded out Also fix incorrect description of ATTR_MSS_MEM_MC_IN_GROUP Change-Id: I7c793373b5c124c56ab9caa30dcc7e5cfe7253ca CQ:SW366015 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30193 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30194 Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../chips/p9/procedures/xml/attribute_info/nest_attributes.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 70df0df4..a9fb0b6f 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -878,14 +878,14 @@ ATTR_MSS_MEM_MC_IN_GROUP TARGET_TYPE_PROC_CHIP - An 8 bit vector that would be a designation of which MC (Nimbus MCS or + An 8 bit vector that would be a designation of which MC (Nimbus MCA or Cumulus MI) are involved in the group. So the bits would represent Nimbus Cumulus - Bit 0 MCS0 MI0 - Bit 1 MCS1 MI1 + Bit 0 MCA0 MI0 + Bit 1 MCA1 MI1 ..... - Bit 7 MCS7 MI7 + Bit 7 MCA7 MI7 Set by p9_mss_eff_grouping uint8 -- cgit v1.2.1