From 5ed7e3200c5fe9a317d0b2df000bf65f23a16fef Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Thu, 27 Oct 2016 15:06:46 +0200 Subject: sector buffer,pulse mode attributes * p9_sbe_chiplet_reset * p9_sbe_npll_setup Change-Id: I488e9cda493e34f36dc60edccd7bec02582878b1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32106 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej Reviewed-by: Sunil Kumar Reviewed-by: PARVATHI RACHAKONDA Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32164 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 63 ++++++++++++++++++++++ .../p9/procedures/hwp/perv/p9_sbe_npll_setup.C | 53 ++++++++++++++++++ .../xml/attribute_info/p9_sbe_attributes.xml | 12 +++++ .../xml/attribute_info/pervasive_attributes.xml | 22 ++++++++ 4 files changed, 150 insertions(+) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index c4dc56b4..389e5557 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -139,6 +139,9 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic( static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0( const fapi2::Target& i_target_chip); +static fapi2::ReturnCode p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup( + const fapi2::Target& i_target_chip); + fapi2::ReturnCode p9_sbe_chiplet_reset(const fapi2::Target& i_target_chip) { @@ -294,6 +297,9 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const FAPI_DBG("Clock mux settings"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_call(i_target_chip)); + FAPI_DBG("Sector buffer strength and pulse mode setup"); + FAPI_TRY(p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup(i_target_chip)); + if ( l_attr_vitl_setup ) { l_target_state = fapi2::TARGET_STATE_PRESENT; @@ -1450,3 +1456,60 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0( fapi_try_exit: return fapi2::current_err; } + +/// @brief Setup sector buffer strength and pulse mode for MC,OB,XB,PCIE +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup( + const fapi2::Target& i_target_chip) +{ + + fapi2::buffer l_data64_net_ctrl1; + fapi2::buffer l_attr_buffer_strength = 0; + fapi2::buffer l_attr_pulse_mode_enable = 0; + fapi2::buffer l_attr_pulse_mode_value = 0; + fapi2::Target l_sys; + + FAPI_INF("p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup:Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECTOR_BUFFER_STRENGTH, l_sys, + l_attr_buffer_strength)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PULSE_MODE_ENABLE, l_sys, + l_attr_pulse_mode_enable)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PULSE_MODE_VALUE, l_sys, + l_attr_pulse_mode_value)); + + for (auto l_target_cplt : i_target_chip.getChildren + (static_cast(fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(fapi2::getScom(l_target_cplt, PERV_NET_CTRL1, l_data64_net_ctrl1)); + + FAPI_DBG("Sector buffer strength"); + l_data64_net_ctrl1.insertFromRight< PERV_1_NET_CTRL1_SB_STRENGTH, + PERV_1_NET_CTRL1_SB_STRENGTH_LEN >(l_attr_buffer_strength); + FAPI_TRY(fapi2::putScom(l_target_cplt, PERV_NET_CTRL1, l_data64_net_ctrl1)); + + FAPI_DBG("Pulse mode enable & pulse mode"); + + if (l_attr_pulse_mode_enable.getBit<7>()) + { + FAPI_DBG("setting pulse mode enable"); + l_data64_net_ctrl1.setBit(); + FAPI_TRY(fapi2::putScom(l_target_cplt, PERV_NET_CTRL1, l_data64_net_ctrl1)); + + l_data64_net_ctrl1.insertFromRight< PERV_1_NET_CTRL1_CLK_PULSE_MODE, + PERV_1_NET_CTRL1_CLK_PULSE_MODE_LEN >(l_attr_pulse_mode_value); + FAPI_TRY(fapi2::putScom(l_target_cplt, PERV_NET_CTRL1, l_data64_net_ctrl1)); + } + + } + + FAPI_INF("p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup:Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C index be89e97d..abeb8550 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C @@ -51,6 +51,9 @@ enum P9_SBE_NPLL_SETUP_Private_Constants SIM_CYCLE_DELAY = 1000 // unit is sim cycles }; +static fapi2::ReturnCode p9_sbe_npll_setup_sectorbuffer_pulsemode_settings( + const fapi2::Target& i_target_chip); + fapi2::ReturnCode p9_sbe_npll_setup(const fapi2::Target& i_target_chip) { @@ -64,6 +67,9 @@ fapi2::ReturnCode p9_sbe_npll_setup(const fapi2::buffer l_data64_perv_ctrl0; FAPI_INF("p9_sbe_npll_setup: Entering ..."); + FAPI_DBG("Sector buffer strength and pulse mode setup"); + FAPI_TRY(p9_sbe_npll_setup_sectorbuffer_pulsemode_settings(i_target_chip)); + FAPI_DBG("Reading ROOT_CTRL8 register value"); //Getting ROOT_CTRL8 register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, @@ -278,3 +284,50 @@ fapi_try_exit: return fapi2::current_err; } + +/// @brief Setup sector buffer strength and pulse mode +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_npll_setup_sectorbuffer_pulsemode_settings( + const fapi2::Target& i_target_chip) +{ + fapi2::Target l_sys; + fapi2::buffer l_data64_perv_ctrl1; + fapi2::buffer l_attr_buffer_strength = 0; + fapi2::buffer l_attr_pulse_mode_enable = 0; + fapi2::buffer l_attr_pulse_mode_value = 0; + + FAPI_INF("p9_sbe_npll_setup_sectorbuffer_pulsemode_settings:Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECTOR_BUFFER_STRENGTH, l_sys, + l_attr_buffer_strength)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PULSE_MODE_ENABLE, l_sys, + l_attr_pulse_mode_enable)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PULSE_MODE_VALUE, l_sys, + l_attr_pulse_mode_value)); + + FAPI_TRY(fapi2::getScom(i_target_chip , PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1)); + + FAPI_DBG("Sector buffer strength"); + l_data64_perv_ctrl1.insertFromRight< PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC, + PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC_LEN >(l_attr_buffer_strength); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1)); + + FAPI_DBG("Pulse mode enable & pulse mode"); + + if (l_attr_pulse_mode_enable.getBit<7>()) + { + l_data64_perv_ctrl1.setBit(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1)); + + l_data64_perv_ctrl1.insertFromRight< PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC, + PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC_LEN >(l_attr_pulse_mode_value); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1)); + } + + FAPI_INF("p9_sbe_npll_setup_sectorbuffer_pulsemode_settings:Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index ea7118d0..5b6fdf55 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -549,5 +549,17 @@ attribute tank ATTR_PROC_FABRIC_PUMP_MODE 0x2 + + ATTR_SECTOR_BUFFER_STRENGTH + 0x0 + + + ATTR_PULSE_MODE_ENABLE + 0x0 + + + ATTR_PULSE_MODE_VALUE + 0x0 + diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 582e55a1..f58006a3 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -663,6 +663,28 @@ + + ATTR_SECTOR_BUFFER_STRENGTH + TARGET_TYPE_SYSTEM + Sector buffer strength + uint8 + + + + + ATTR_PULSE_MODE_ENABLE + TARGET_TYPE_SYSTEM + enable the pulse mode + uint8 + + + + ATTR_PULSE_MODE_VALUE + TARGET_TYPE_SYSTEM + value for pulse mode + uint8 + + -- cgit v1.2.1