From 48cb971825de06b01906fcebf1eb5490f8969127 Mon Sep 17 00:00:00 2001
From: Adam Hale <adam.samuel.hale@ibm.com>
Date: Thu, 10 Aug 2017 15:45:35 -0500
Subject: Halt on zero instruction/load/store address

Change-Id: Ia865a3b89a22ff81c2099ce4688bae076e54b279
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44497
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44503
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
---
 src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h      | 7 ++++++-
 src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S | 4 +++-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
index 18ee3fdf..d1be9935 100644
--- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
@@ -428,7 +428,12 @@ uint32_t __pk_panic_dbcr = DBCR_RST_HALT;
 /// the 'panic' macros and the default DBCR0 setup.
 
 #ifndef PPE42_DBCR_INITIAL
-#define PPE42_DBCR_INITIAL DBCR_TRAP
+#define PPE42_DBCR_INITIAL (DBCR_TRAP | DBCR_IACE)
+#endif
+
+
+#ifndef PPE42_DACR_INITIAL
+#define PPE42_DACR_INITIAL 0
 #endif
 
 /// This is the value of the MSR used during initialization.  Once PK threads
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
index 189c2968..c83c02a5 100644
--- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -120,6 +120,8 @@ __reset_trap:
 #ifndef NO_INIT_DBCR0
         _liwa   %r3, PPE42_DBCR_INITIAL
         mtdbcr  %r3
+        _liwa   %r3, PPE42_DACR_INITIAL
+        mtdacr  %r3
 #endif
 
         ## The exception vector prefix is set - it must be 512 byte aligned.
-- 
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