From 2fdf5d8448f8b52816d629a2ee9c32cac2a89efe Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Fri, 4 Aug 2017 16:10:14 +0200 Subject: p9_setup_clock_term updates Using pci_clk_req enum to set osc0 and osc1 configurations Change-Id: Ie4a45f121e9c5ecb2e4883332ac948d80ab6a6cf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44218 Reviewed-by: Manish K. Chowdhary Tested-by: Jenkins Server Reviewed-by: Soma Bhanutej Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48502 Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H b/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H index a2430740..2404e6a0 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_clock_term.H @@ -50,8 +50,10 @@ enum P9_SETUP_CLOCK_TERM_Public_Constants OSCSWITCH_RC3 = 0x0080C000, OSCSWITCH_RC4 = 0x0, DISABLE_WRITE_PROTECTION = 0x4453FFFF, - P9C_OSCSWITCH_RC3_CP0_CP2 = 0x00009000, - P9C_OSCSWITCH_RC3_CP1_CP3 = 0x00006000 + P9C_OSCSWITCH_RC3_BOTHSRC0 = 0x00009000, + P9C_OSCSWITCH_RC3_BOTHSRC1 = 0x00006000, + P9C_OSCSWITCH_RC3_SRC0 = 0x0000C000, + P9C_OSCSWITCH_RC3_SRC1 = 0x00003000 }; } @@ -82,7 +84,7 @@ typedef fapi2::ReturnCode (*p9_setup_clock_term_FP_t)(const extern "C" { fapi2::ReturnCode p9_setup_clock_term(const - fapi2::Target& i_target_chip, const pci_clk_req_enum i_pci_clk_req); + fapi2::Target& i_target_chip, const pci_clk_req_enum i_pci_clk_req = BOTH_SRC0 ); } #endif -- cgit v1.2.1