From 0a62b30ce373bdb8096fc886ce535078696c2cf4 Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Fri, 16 Sep 2016 15:04:09 +0200 Subject: Changing ATTR_PG from 32 to 16 bit Change-Id: I346f10136e9621ea06e381cfad2a2b903cb2bd64 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29834 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Daniel M. Crowell Reviewed-by: Thi N. Tran Reviewed-by: Matt K. Light Dev-Ready: Joseph J. McGill Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29836 Reviewed-by: Hostboot Team Reviewed-by: Shakeeb A. Pasha B K Tested-by: FSP CI Jenkins Reviewed-by: RAJA DAS Reviewed-by: Santosh S. Puranik --- src/hwpf/src/plat/target.C | 6 +++--- .../chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C | 5 +---- .../chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C | 10 ++-------- src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C | 12 ++++++------ src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C | 1 - .../chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 2 +- src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | 8 ++++---- src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H | 2 +- .../chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C | 6 +++--- .../p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C | 6 +++--- .../chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C | 6 +++--- .../procedures/xml/attribute_info/pervasive_attributes.xml | 5 ++--- 12 files changed, 29 insertions(+), 40 deletions(-) diff --git a/src/hwpf/src/plat/target.C b/src/hwpf/src/plat/target.C index 4249c6ec..9ff1a75b 100644 --- a/src/hwpf/src/plat/target.C +++ b/src/hwpf/src/plat/target.C @@ -293,7 +293,7 @@ namespace fapi2 bool & o_present) { o_present = false; - uint32_t attr_value = 0; + uint16_t attr_value = 0; FAPI_ATTR_GET(fapi2::ATTR_PG, i_target, attr_value); @@ -472,7 +472,7 @@ fapi_try_exit: fapi2::Target l_parent = target_name.getParent(); // Get the parent EQ's ATTR_PG - uint32_t l_eqAttrPg = 0; + uint16_t l_eqAttrPg = 0; FAPI_ATTR_GET(fapi2::ATTR_PG, l_parent.getParent(), l_eqAttrPg); // Check if this EX's L2 and L3 regions are marked "good" @@ -507,7 +507,7 @@ fapi_try_exit: fapi2::Target l_nestTarget((plat_getTargetHandleByChipletNumber(N3_CHIPLET - (MCS_PER_MCBIST * (i / MCS_PER_MCBIST))))); - uint32_t l_attrPg = 0; + uint16_t l_attrPg = 0; FAPI_ATTR_GET(fapi2::ATTR_PG, l_nestTarget, l_attrPg); diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C index fa20765a..a508e448 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -98,7 +98,6 @@ p9_hcd_cache_startclocks( uint8_t l_attr_chip_id = 0; uint8_t l_attr_chip_unit_pos = 0; uint8_t l_attr_system_ipl_phase; - uint32_t l_attr_pg; fapi2::Target l_chip = i_target.getParent(); fapi2::Target l_perv = @@ -113,8 +112,6 @@ p9_hcd_cache_startclocks( l_attr_chip_id)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip, l_attr_system_id)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, l_perv, - l_attr_pg)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos)); l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET; @@ -304,7 +301,7 @@ p9_hcd_cache_startclocks( // Cleaning up // ------------------------------- - if (((~l_attr_pg) & BITS32(4, 11)) && l_attr_system_ipl_phase != 4) + if (l_attr_system_ipl_phase != 4) { FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]"); FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(18))); diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C index d7bf6491..1ae58a8a 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -87,7 +87,6 @@ p9_hcd_core_startclocks( FAPI_INF(">>p9_hcd_core_startclocks"); fapi2::buffer l_data64; uint32_t l_timeout; - uint32_t l_attr_pg; uint8_t l_attr_chip_unit_pos; uint8_t l_attr_system_ipl_phase; uint8_t l_attr_runn_mode; @@ -101,8 +100,6 @@ p9_hcd_core_startclocks( l_attr_runn_mode)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys, l_attr_system_ipl_phase)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, l_perv, - l_attr_pg)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos)); l_attr_chip_unit_pos = (l_attr_chip_unit_pos - @@ -245,11 +242,8 @@ p9_hcd_core_startclocks( // Cleaning up // ------------------------------- - if ((~l_attr_pg) & BITS32(4, 11)) - { - FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]"); - FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(18))); - } + FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(18))); /// @todo ignore xstop checkstop in sim, review for lab /* diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C index 3c90b0b8..a15db407 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C @@ -279,9 +279,9 @@ fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_16(const const fapi2::buffer i_regions_value, fapi2::buffer& o_regions_value) { - fapi2::buffer l_read_attr = 0; - fapi2::buffer l_read_attr_invert = 0; - fapi2::buffer l_read_attr_shift1_right = 0; + fapi2::buffer l_read_attr = 0; + fapi2::buffer l_read_attr_invert = 0; + fapi2::buffer l_read_attr_shift1_right = 0; FAPI_INF("p9_perv_sbe_cmn_regions_setup_16: Entering ..."); FAPI_DBG("Reading ATTR_PG"); @@ -324,9 +324,9 @@ fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_64(const const fapi2::buffer i_regions_value, fapi2::buffer& o_regions_value) { - fapi2::buffer l_read_attr = 0; - fapi2::buffer l_read_attr_invert = 0; - fapi2::buffer l_read_attr_shift1_right = 0; + fapi2::buffer l_read_attr = 0; + fapi2::buffer l_read_attr_invert = 0; + fapi2::buffer l_read_attr_shift1_right = 0; fapi2::buffer l_temp = 0; FAPI_INF("p9_perv_sbe_cmn_regions_setup_64: Entering ..."); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C index 04f9c0da..55651514 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C @@ -69,7 +69,6 @@ fapi2::ReturnCode p9_sbe_arrayinit(const fapi2::Target& i_target_chip) { fapi2::buffer l_regions; - fapi2::buffer l_attr_pg; fapi2::buffer l_attr_read; FAPI_INF("p9_sbe_arrayinit: Entering ..."); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 11beaf87..240287f4 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -961,7 +961,7 @@ fapi_try_exit: static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache( const fapi2::Target& i_target_chiplet) { - uint32_t l_attr_pg = 0; + uint16_t l_attr_pg = 0; FAPI_INF("p9_sbe_chiplet_reset_mc_setup_cache: Entering ..."); FAPI_DBG("Reading ATTR_PG"); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index bbdc3c67..7523181a 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -499,17 +499,17 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( const fapi2::Target& i_target_chiplet, - const fapi2::buffer i_attr_pg) + const fapi2::buffer i_attr_pg) { // Local variable and constant definition fapi2::buffer l_cplt_ctrl_init; - fapi2::buffer l_attr_pg; + fapi2::buffer l_attr_pg; fapi2::buffer l_data64; FAPI_INF("p9_sbe_common_cplt_ctrl_action_function: Entering ..."); l_attr_pg = i_attr_pg; l_attr_pg.invert(); - l_attr_pg.extractToRight<20, 11>(l_cplt_ctrl_init); + l_attr_pg.extractToRight<4, 11>(l_cplt_ctrl_init); // Not needed as have only nest chiplet (no dual clock controller) Bit 62 ->0 // @@ -517,7 +517,7 @@ fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( //Setting CPLT_CTRL1 register value l_data64.flush<0>(); l_data64.writeBit - (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + (l_attr_pg.getBit<3>()); //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_cplt_ctrl_init l_data64.insertFromRight<4, 11>(l_cplt_ctrl_init); FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H index 00838856..4f6abdde 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H @@ -72,7 +72,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( const fapi2::Target& i_target_chiplet, - const fapi2::buffer i_attr_pg); + const fapi2::buffer i_attr_pg); fapi2::ReturnCode p9_sbe_common_flushmode(const fapi2::Target& i_target_chiplet); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C index a31883b1..9face087 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C @@ -64,7 +64,7 @@ static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop( static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( const fapi2::Target& i_target_chiplet, - fapi2::buffer& o_attr_pg); + fapi2::buffer& o_attr_pg); static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( const fapi2::Target& i_target_chiplet, @@ -79,7 +79,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const { uint8_t l_read_attr = 0; fapi2::buffer l_read_flush_attr; - fapi2::buffer l_attr_pg; + fapi2::buffer l_attr_pg; fapi2::buffer l_pg_vector; fapi2::buffer l_clock_regions; fapi2::buffer l_n3_clock_regions; @@ -299,7 +299,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if success, else error code. static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( const fapi2::Target& i_target_chiplet, - fapi2::buffer& o_attr_pg) + fapi2::buffer& o_attr_pg) { FAPI_INF("p9_sbe_nest_startclocks_get_attr_pg: Entering ..."); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C index b1d932ac..36978a77 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C @@ -58,7 +58,7 @@ enum P9_SBE_STARTCLOCK_CHIPLETS_Private_Constants static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( const fapi2::Target& i_target_chiplet, - fapi2::buffer& o_attr_pg); + fapi2::buffer& o_attr_pg); static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop( const fapi2::Target& i_target_chiplet, @@ -85,7 +85,7 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const fapi2::buffer l_pg_vector; fapi2::buffer l_regions; fapi2::buffer l_attr_obus_ratio; - fapi2::buffer l_attr_pg; + fapi2::buffer l_attr_pg; FAPI_INF("p9_sbe_startclock_chiplets: Entering ..."); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, @@ -177,7 +177,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if success, else error code. static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( const fapi2::Target& i_target_chiplet, - fapi2::buffer& o_attr_pg) + fapi2::buffer& o_attr_pg) { FAPI_INF("p9_sbe_startclock_chiplets_get_attr_pg: Entering ..."); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C index fe877144..ae843d3b 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C @@ -332,7 +332,7 @@ static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup( const fapi2::Target& i_target_chiplet) { // Local variable and constant definition - fapi2::buffer l_attr_pg; + fapi2::buffer l_attr_pg; fapi2::buffer l_attr_pg_data; fapi2::buffer l_data64; FAPI_INF("p9_sbe_tp_chiplet_init3_region_fence_setup: Entering ..."); @@ -340,13 +340,13 @@ static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); l_attr_pg.invert(); - l_attr_pg.extractToRight<20, 11>(l_attr_pg_data); + l_attr_pg.extractToRight<4, 11>(l_attr_pg_data); FAPI_DBG("Drop partial good fences"); //Setting CPLT_CTRL1 register value l_data64.flush<0>(); l_data64.writeBit - (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + (l_attr_pg.getBit<3>()); //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_attr_pg_data l_data64.insertFromRight<4, 11>(l_attr_pg_data); FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index d632baa3..f682aa39 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -417,11 +417,10 @@ ATTR_PG TARGET_TYPE_PERV - Chiplet Partial good info attribute. Provided by Ring scans. + Chiplet Partial good info attribute This should be a direct copy of the data from the PG keyword of VPD. - (Note : the 16-bit vpd data is right-justified into attribute) - uint32 + uint16 -- cgit v1.2.1