| Commit message (Collapse) | Author | Age | Files | Lines |
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Send response on PSU chipops everytime
Increase resolution of timer to us
Implement support for update timer
Change-Id: I497265010d346fc65d14680e356473c019864194
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51933
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Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I273c1e1f6720db08eb66366a3c1e88f8b10b5411
RTC: 184523
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51931
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Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I73d38d6029a5b84590d1081855e12c145a535869
CQ: SW413192
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51338
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
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Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51345
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ief523bd33a34a6a96f61664f6ab3545d9dc15d98
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52050
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Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52121
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ibc514c12567ab472d0eb55106356c84deff1897b
CQ:SW411365
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52091
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Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52097
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I5255e89c75243486acdd74ca9e07c9a680db6677
CQ: SW410020
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51952
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ieccb58c724769e5ae58f2117bb1ddd52fffdfe06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52083
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Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Makefile re-org for project specific build
Change-Id: I51893710979f19cf00e41725c83d1c0c653c4b60
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50744
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Support for the new ADU flags required to
use ADU chipops to switch fabric configuration
Change-Id: Ia2ace86c0ceb63e6f0c58882d660cf176967c3b4
RTC:177901
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51439
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Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Within the PK interrupt vector, if you have a function call from
one function to another, it needs branch link instruction, but
since the BL is already being used to jump from software context
to the PK Vectored Interrupt context, the function call from within
will corrupt the Link register.
For interrupts like data_storage, instruction_storage,
alignment_exception and program_exception, the save-off will
capture the LR registers to indicate which interrupt was getting
executed when halt happened. For Machine check handler, LR won't be
valid.
Change-Id: Iee17b37acd438c7bee2c956cac2de3ce64d04441
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51587
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Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51588
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Change-Id: I90b9b21957bb58ab7e1ed1802d8723dcf4b05b6f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48094
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Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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Change-Id: I0d0aebc925c963a32e2cf2266e833df84a799235
CQ: HW409194
CQ: HW407065
CQ: HW419541
CQ: HW430944
CQ: HW417829
CQ: HW422533
CQ: HW414249
CQ: HW432749
CQ: HW414146
CQ: HW433125
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51677
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51685
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I0213b7b59d482dd5182f0c4e7593a246a0f82e86
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52059
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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With increased run cycles, jenkins failure is resolved
Change-Id: I316004d6846800c6b520f881628aa2678c7b9569
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52066
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Change-Id: I5435bef91381ade76a1439a842fa90b86e17aab3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51599
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51604
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Bit mask of group IDs which will be present in the fully configured
CEC configuration.
Change-Id: I43b06e856d2b285bb919025926b914d3ec4de451
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51701
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: If2916c99b37c4ce56ad1cf6f6957d67497fac5ab
CQ: SW412668
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Reviewed-by: YUE DU <daviddu@us.ibm.com>
Dev-Ready: Brian T. Vanderpool <vanderp@us.ibm.com>
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Iee18d460dc99de59eb0b1f8891dad1e8698e3208
CQ:HW430944
CQ:HW432070
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This update propagates the extracted EC level in xip_customize
through to the TOR API via the call to tor_get_single_ring(). The
TOR API has been updated to verify that the requested DD level
matches matches the DD level in the TOR header of the supplied
ring section which, in the case of xip_customize, is an .overlays
ring section.
Key_Cronus_Test=XIP_REGRESS
Change-Id: Ic087c269306acc0afcb8c759fe68eac63ae93d29
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Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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Change-Id: I6c64841173f036c4898c199ef1615046a3974dcc
CQ: HW422471
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48525
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- IMC6 changed to implement special nop
- IMC7 serializes bcctr for NDD2.2/CDD1.1
- mttrig2 moved to mttrig0
- mttrig2 now causes an L1 flush on NDD2.2/CDD1.1
- Force private L1D
- branch hint bits always honored
- enable new TM mode for NDD2.2
Change-Id: I3b724f6d742b9ba321ea1abbfa6bbc7d5482b8ed
CQ: HW430733
CQ: SW410726
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50872
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51025
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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centaur.mbs.scan.initfile
Remove static application of read data delay disables
Centaur will now flush to read data delay enabled
cen_initf
Add block to re-rotate tcn_mbs_func and:
- fix existing spy parity errors
- apply read data delay disables,
executed only when attached chip is Cumulus DD1.0
Change-Id: I10279decbbf27df911a94ce27d11b4d2e30b6e5f
RTC: 138785
CQ: HW419021
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50720
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50735
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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That delay was always compiled into the procedure and we tested with
it, so let's make it permanent.
Change-Id: If8a5c6fbf4bd8b42e37656f66ced96604813485b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48748
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48754
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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cen_ringId.CH
cen_ring_id.h
add entries to hold multiple PLL rings, 8 in total
cen_initf.C
cen_pll_initf.C
cen_pll_initf_errors.xml
replace invocation of generated initfile HWP with putRing API calls
(rings to be scanned gleamed from p8 cen assembly source)
select correct PLL ring image based on NEST,MEM frequency
cen_bucketX.txt
define frequency points for each PLL bucket
1 = 2000 MHz NEST, 1066 MHz MEM
2 = 2000 MHz NEST, 1333 MHz MEM
3 = 2000 MHz NEST, 1600 MHz MEM
4 = 2000 MHz NEST, 1866 MHz MEM
5 = 2400 MHz NEST, 1066 MHz MEM
6 = 2400 MHz NEST, 1333 MHz MEM
7 = 2400 MHz NEST, 1600 MHz MEM
8 = 2400 MHz NEST, 1866 MHz MEM
ipl_base.txt
ipl_risk.txt
remove frequency attributes from base attribute files
scan_procedures.mk
add rules to generate PLL buckets
Change-Id: I8aee5e82337800ea9afe9a9af12d8d34f6e1e01e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50475
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50478
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I1c93a9b505e6656ea9bda20a7fac363e037a3d73
CQ: HW430546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50832
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50979
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I0068d797ad4a82216e440f701c5182ad95584a15
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51503
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51504
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This commit is the first part of 49692, which is splitted in
order to have SBE platform proceed with code supports.
Change-Id: I1f491cac6cfef8476487217067d69d4551de1228
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51048
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51049
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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to support WIN32 for manu team.
Also,
- various updates to dd_container error handling,
- improved DD support query checking.
Change-Id: I2eab02732b3852698d8ffba5eed16a5e0bb37faa
Original-Change-Id: I706e56258894c3453cf01aa1a637fe888af1db00
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46596
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51558
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The PCI oscillator checking code in proc_clock_test2 always checked both
osc error bits, which fails on a Cumulus system with only a single PCI
refclock active. Modify it to check osc error bits depending on which
oscillators have been configured in the osclite config.
Change-Id: I8c5ee38f8bc718dbb8eab59139a19800bb3a9f6f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51723
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Martin Padeffke <padeffke@de.ibm.com>
Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51796
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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chip_ec_attributes.xml
add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need
MCD disable for HW423589 (applied to Nimbus EC20 and 22+)
p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scan.initfile
p9.l3.scan.initfile
p9.mmu.scom.initfile
p9.ncu.scan.initfile
p9.npu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_pcie_config.C
set unit scope disable dials
p9_sbe_scominit.C
p9_pm_pba_init.C
set PBA unit scope disable dial
p9_pm_set_homer_bar.C
change PBA0 default command scope from GROUP to NODAL
p9.fbc.ab_hp.scom.initfile
disable group master setup
p9_setup_bars.C
p9_setup_bars_defs.H
skip MCD setup for HW423589_OPTION1
cmvc-prereq: 1043014
Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I05b7b14e8ce7fdb61be1a5e6ccefc2e49beeeb4f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51236
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51239
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
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Disabling generic and instruction control chip ops on DD1
to reclaim pibmem
Change-Id: Id5ee5c7669ffbba8ffca6e580c7516d2339ed74a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51759
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: If9ce191a8d09ccf4cd46fd9daabb26bfe8012fef
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45780
Reviewed-by: ARAVIND T. NAIR <aravindnair@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Srikantha S. Meesala <srikantha@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51522
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Introduce project specific IPL table
Change-Id: Ibc22805e6145a241c2e205e69ef10272da67d351
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50743
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I4245ba11c525e8406cf24554b2c0194c8023c13d
Original-Change-Id: I4c9d8cb28d4ae6a8b21c87ebaad07c1fd7163b85
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39588
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com>
Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51557
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Addition of app/common directory and associated makefiles
Change-Id: I9cd107965b5712ee03b32d3939828281a6cadf83
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50569
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Remove separate seeprom makefile from core folder
Change-Id: I5693d948d931cb4770dea1cb9ec6e45e3fb9b592
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50553
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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I inserted P9A before CT_CEN for purely estaetic reasons. Since
the current Centaur image in EKB isn't being used yet, this
should be safe (as otherwise there would be a co-req
situation).
Change-Id: Ia5ef9950644eacea3fdc28a0195502bdcae44327
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50812
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50962
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Separate chip-op handler and chip-op table to make
it project specific
Change-Id: I3ff0e83b199172ce0c0fcb49a980a0076ad778a7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50504
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Create a core and app folder inside sbefw
Change-Id: I4ee04eb5d6623a2272a20f5dd8b02ef795757b2e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50185
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I72b12175743f1b1e420b6e9d191f3255daf27700
CQ: SW412231
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51309
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
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i2c reset sequence as a C function
Change-Id: Ia14523765c5b4d4a7073f40e7dbf614197f5b825
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50796
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sandeep Korrapati <sakorrap@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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As dump is using get reg in secure systems, unblocking it
Change-Id: I623eafde360c7cecf70e027831ddd57af42efd07
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51228
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Entity which is calling mpipl, supposed to set MBX registers to
right value. The value can differ from previous IPL. SBE was
overwriting the new value with previous value.
Change-Id: Ia458d46a0e81ac164e6a4dfb8fd8114e03ca3d4e
CQ: SW411113
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51176
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I8cf51a4e044c70871c5f74a5d3a6ecfe64dafd47
CQ: SW411044
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50779
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50992
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I1f39c95d11b9a2a0b03a7303d2024f63e295f43a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51174
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Reset MPIPL flags if enter or continue mpipl fails
Also reset the flag if contoniue mpipl pass
Change-Id: I71d6ab7035431dfe3061d67108e43ca262601917
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50815
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Nimbus DD2.0 disable will go into op910 only (for Boston Coral)
but not into master
Change-Id: I28376316be3e6700af97df83a02c48e46d715dec
CQ: HW415945
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50445
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50453
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The PCIe timeout have increased to 66-100ms, so we need to double
the NCU master timeouts to be above these timeouts. This has a
chain effect causing the L2/L3 master timeouts to increase which
causes the tlbie snooper to increase which causes the tlbie master
to increase.
This would also ususally cause the core timeout to increas, but
the core is already at around 13 seconds, so there is headroom
there.
Change-Id: I5930076151267a9bfa66e24edef0985c165db0b7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50582
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50602
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Upon PGPE Halt
1) SGPE performs STOP Recovery Trigger to set
a malfunction alert and removes PGPE IPCs
from wake-up decisions.
2) CME is interrupted by QPPM OCC Heartbeat
Lost that PGPE stopped updating
Upon SGPE Halt
1) PGPE moves to Psafe
2) PGPE performs STOP Recovery Trigger to set
a malfunction alert.
This commit also includes SGPE Panic Code
Cleanup such as debug halt support.
However PGPE Panic Code Cleanup is dealt in
a different commit
Key_Cronus_Test=PM_REGRESS
Change-Id: I893aa1ef21d2f684722b8c10dbbeb92b9505c1c4
CQ: SW410252
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49275
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49429
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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