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* INT scan initfile change to add workaround for HW408972Jenny Huynh2017-04-281-0/+18
* Updating HW363605 workaround to be applied to all chipsLuke Murray2017-04-281-17/+0
* Add NCU/L3 dials for HW396230 to p9.ncu.scom.initfileCHRISTINA L. GRAVES2017-04-284-5/+54
* IPL: Add global checkstop FIR check in Istep4Yue Du2017-04-282-22/+62
* p9_setup_bars -- support DD2 NPU SCOM address changesCHRISTINA L. GRAVES2017-04-201-0/+18
* Fixing SGPE TOR allocation bug in ring_applyClaus Michael Olsen2017-04-191-0/+1
* p9_pstate_param_blk: Define VFRT table and initialize the dataPrasad Bg Ranganath2017-04-191-0/+37
* PM: Resonant Clocking Enablement - InfrastructureChristopher M. Riedl2017-04-191-6/+6
* using literal definitionsSoma BhanuTej2017-04-192-61/+57
* PK move global data to .sdata/.sbss sections to reduce code sizeDoug Gilbert2017-04-196-13/+17
* p9_sbe_startclock_chiplets updatesAnusha Reddy Rangareddygari2017-04-191-0/+21
* Add unique FAPI RC per PIB RCSantosh Puranik2017-04-181-1/+43
* STOP: Enable CHTMYue Du2017-04-181-0/+38
* PK DEC timer interrupts too close togetherDoug Gilbert2017-04-182-10/+19
* Added read ctr bad delay workaroundStephen Glancy2017-04-181-0/+17
* Updating optimal larx/stcx dials for performanceLuke Murray2017-04-181-0/+24
* HW407123: Slow down xlink command rate for Nimbus DD1/2Jenny Huynh2017-04-181-0/+19
* p9_htm_setup -- cleanup start behavior for multi-chip systemsJoe McGill2017-04-131-8/+10
* Need to disable fast path and cmd bypass for HB loadDean Sanner2017-04-111-1/+12
* Add another writeBit API, modify getBit. Add unit tests.Andre Marin2017-04-111-4/+30
* FFDC updates - p9_start_cbsAnusha Reddy Rangareddygari2017-04-061-1/+13
* Update filter pll settings as per HW407180Ben Gass2017-04-061-0/+18
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2017-04-063-0/+28
* Updating L3 LCO watermarks for HW406803Luke Murray2017-04-061-0/+17
* Adding epsilon divider variable to cache initfilesLuke Murray2017-04-062-12/+24
* Updating cache epsilon initfile equationLuke Murray2017-04-062-94/+14
* Added suspend_io in p9_sbe_check_quiesce procedureRaja Das2017-04-061-0/+3
* Enabled p9_suspend_io hwp in SBE MakefileRaja Das2017-04-061-0/+1
* Change RingID to RingId_t in putRingKahn Evans2017-04-062-5/+4
* Build p9n 10 and 20 by default.Ben Gass2017-04-061-10/+50
* Do the real LPC reset for DD2CHRISTINA L. GRAVES2017-04-062-1/+33
* add TARGET_TYPE_MCMatt K. Light2017-04-061-2/+4
* literal definitionsAnusha Reddy Rangareddygari2017-04-064-62/+65
* STOP: UIH updates on trace and phantom interrupt handlingYue Du2017-04-061-4/+18
* Adding good LCO settings to initfileLuke Murray2017-04-031-0/+41
* Add workaround so p9_suspend_io can be called systems with no PHB5crgeddes2017-03-311-0/+22
* HW404292: Assert analog fence in cache_chiplet_resetYue Du2017-03-313-2/+10
* HW405243/IPL: Assert/drop pcb_mux_disable around quad power offYue Du2017-03-313-6/+61
* update DPLL and IVRM initsJoe McGill2017-03-313-4/+61
* IPL: Change select_ex to use core/eq targets instead of pervYue Du2017-03-311-25/+23
* disable noise window for DD1 HW406577Shelton Leung2017-03-311-0/+17
* support customization of Nimbus DD1 PCI reference clock speedJoe McGill2017-03-312-0/+38
* Defining generic RingId_t type for transitional eCMD releaseKahn Evans2017-03-301-1/+2
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-03-295-5/+120
* Enablement of additional eq_ana_bndy rings for Nimbus DD2Sumit Kumar2017-03-245-27/+104
* Increased the size of buildTag in xip header by another 4BytesRaja Das2017-03-242-6/+1
* adding opencapi to ATTR_OPTICS_CONFIG_MODEJoshua Hannan2017-03-231-1/+3
* Include p9_ring_id.h or p9_ringId.HKahn Evans2017-03-232-0/+2
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2017-03-234-6/+30
* p9_suspend_io procedure with updates from review feedbackRicardo Mata2017-03-233-0/+463
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