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* Attribute cleanupDan Crowell2018-09-212-98/+30
| | | | | | | | | | | | | | | | | | | | | Added mrwHide to a lot of platInit attributes, this will prevent them from showing up in the ServerWiz tool where the value will be hard to change. Instead these will always rely on the default in the xml or explicit platform code to set. Also removed a bunch of unused tags to clean things up. Change-Id: Id237924d737392368c418cc31d6506f1f5598b98 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64233 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66013 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support 1byte data access on LPCspashabk-in2018-09-212-6/+40
| | | | | | | | | | | | | | | | | | | | Currently LPC driver supports only 4bytes data access, with this commit introducing support for 1byte and also a way to extend this to 2bytes. RTC: 194000 Change-Id: I7cb258425100c2d2a3e78f35f0aaf7da1c0e8508 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64174 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64176 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* FBC ABUS TDM inject and recovery HWPsJoe McGill2018-09-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_fbc_ioo_tdm_inject New HWP to permit concurrent maintenance of an SMP OBUS link (full-width to half-width operation) Specified half-link of provided endpoint target will have: - FIRs masked - DL layer quiesced - PHY powered down FW should set i_opts members as follows: - i_opts.run_all=true -- HWP executes all steps - i_opts.step=P9_FBC_IOO_TDM_INJECT_END -- don't care p9_fbc_ioo_tdm_recovery New HWP to permit concurrent maintenance of an SMP OBUS link (half-width to full-width operation) HWP detects half-link to recover from provided enpoint target. Specified half-link will have: - FIRs masked and reset - DL layer reset - PHY layer reset, dccal run, and re-initialized - DL FIRs cleared - DL started and retrained - FIRs unmasked FW should set i_opts members as follows: - i_opts.run_all=true -- HWP executes all steps - i_opts.even_not_odd=true -- don't care - i_opts.step=P9_FBC_IOO_TDM_RECOVERY_END -- don't care p9_security_white_black_list Add greylist entries for OBUS PHY, DL layer FIR and FIR mask registers p9_io_regs Add register constants needed for link recovery p9_io_obus_reset Clear RX and TX ioreset Add inits specified in SCOM initfile used at initial IPL p9_obus_fir_utils Add constants to reflect grey list entries for OBUS FIRs p9_io_obus_scominit p9_chiplet_scominit Reference p9_obus_fir_utils for OBUS FIR programming values Change-Id: Iad3884f6057c2ca21f436bc6efc0423fb5f70226 CQ: SW446137 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59370 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63633 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Move lpc_rw to a source filespashabk-in2018-09-193-66/+83
| | | | | | | | | | | | | | | | | | | Moving lpc_rw to its source file to avoid code duplication if more than one file includes lpc_utils.H. This is mainly required by SBE to use lpc_rw for virtual PNOR access. Change-Id: I7de30bcbae932307e0b63d8d42ae6ce050753339 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64296 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64309 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Register 1020019 was white listedmanichow2018-09-191-0/+1
| | | | | | | | | | | | Change-Id: I67234205f15a221927c102cb123e1f6fbbe18814 CQ: SW445497 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66078 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66236 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* RAS_XML: updates to sync the XML with actual values from hardwareZane Shelley2018-09-172-1/+19
| | | | | | | | | | | | | | | | Change-Id: I590d6790cd391ff4be984001acd41c6a1ba48a06 CQ: SW445620 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63398 Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63841 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* IPL/STOP: Disable LCO when only two EXes are configuredYue Du2018-09-171-13/+1
| | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I168f03dbd45da9da1c7f80e37ea508d7b56deec4 CQ: HW463903 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66065 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66066 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SW427193 / HW461448: Enable memory controller watJenny Huynh2018-09-121-0/+21
| | | | | | | | | | | | | | | | | | Change-Id: I2fc4cf0dda43d4eba543024605c8f358e22e1bae CQ:SW427193 CQ:HW461448 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65476 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S. Hale <adam.samuel.hale@ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65508 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "UV Support : Augmented STOP API and self restore for enabling UV"Prem Shanker Jha2018-09-121-24/+0
| | | | | | | | | | | | | | | Change-Id: Iaabd787166422b68179901b7785ab3e8a54d35b8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65875 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65883 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone only-IPL Procedures update to support SBE changesAbhishek Agarwal2018-09-104-35/+219
| | | | | | | | | | | | | | | Using SBE_AXONE_CONFIG compile flag for Axone specific changes Change-Id: I3d67c8f9ebba9fc18925ae02d1fff3cca8a9440b Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53714 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53735
* Axone only-Mux settings for TOD refclk inputAnusha Reddy Rangareddygari2018-09-101-0/+13
| | | | | | | | | | | | | Change-Id: Ie7347a3de7c760dcdb875516c07f470e94f7f027 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61851 Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61855 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* get FAPI_POS for all valid target types passed in SBE FIFO ffdcRichard J. Knight2018-09-071-1/+3
| | | | | | | | | | | | | | | | | | | | | | -In some cases the the SBE will return a proc target type as part of the SBE FFDC buffer, the current code only considers non-proc types when converting the FFDC buffer contents to a target. This commit will correctly convert all valid target types passed back in the FFDC buffer. Change-Id: If9f3542f18b72652d3353b6f167a264fcba21352 CQ:SW444855 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65832 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65852 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Initf procedure updates for Axone OMI ringsAnusha Reddy Rangareddygari2018-09-073-2/+83
| | | | | | | | | | | | | | | using SBE_AXONE_CONFIG compile flag for axone specific changes Change-Id: Ibbbb69d6f8d87b4cbbd011fa5af4f496e5106335 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64915 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64917 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_sbe_lpc_init: Skip final error check for Fleetwood GA1Joachim Fenkes2018-09-071-0/+2
| | | | | | | | | | | | | | | | | | | As a temporary workaround for SW440738, ignore errors after LPC init so we don't halt the IPL for a benign LPC error on the alt master LPC. If the master LPC happens to have a problem we'll find out soon enough. Change-Id: I2d97efe6b49bfab83b834dde31ed878588339bd0 CQ: SW440738 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65767 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65776 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "Initf procedure updates for OMI rings for Axone"Jennifer A. Stofer2018-09-073-65/+2
| | | | | | | | | | | | | This reverts commit 19228973bc00b3b9433470177c1878c46ab65450. Change-Id: I131098b902f3ce99c9aab35bab5ff20b3e2a4548 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64801 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64812 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Initf procedure updates for OMI rings for AxoneAnusha Reddy Rangareddygari2018-09-073-2/+65
| | | | | | | | | | | | | Change-Id: I90c6ecd6e553d36b2f34ba0949cdfce3938ce1c1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64297 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64299 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Infrastructure support for new MC OMI rings for AxoneClaus Michael Olsen2018-09-063-19/+80
| | | | | | | | | | | | | | | | | Key_Cronus_Test=XIP_REGRESS Change-Id: I931305965d8f463233c5c30a3f561c93a4e2e08a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64115 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64127 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* UV Support : Augmented STOP API and self restore for enabling ultravisor.Prem Shanker Jha2018-09-061-0/+24
| | | | | | | | | | | | | | | | | HW-Image-Coreq: yes HW-Image-Prereq: Ia9ae0d284398af375f1562efff152a6a12a6eb9a Change-Id: I1f7ca865640dfc0a08aef783fd3595d2f249a672 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/58843 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62700 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Secure Boot: Whitelist PPE External Interface XCR and SMP lane related registerNick Bofferding2018-09-051-0/+2
| | | | | | | | | | | | | | | | | | Whitelists the PPE External Interface XCR register to allow FSP to start/stop the IO PPE at different phases of system SMP link training to enable better handling of an A-bus cable pull Also whitelist registers used in rx_lane_ana_pdwn, rx_lan_dig_pdwn, rx_tx_lane_pdwn, & rx_lane_disabled HWP Change-Id: I3f0494064919e5182ef3aba0149a9eb49dd05868 CQ: SW441542 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65603 Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65604 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM:Some more cleanups in update_ec_eq procedure for core unit xstop casePrasad Bg Ranganath2018-08-314-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | - Enabled EX check. even if it's EQ is functional - one more check of clock power off which is required for mpipl case. - had one bug during l2/l3 stop clock which fixes status bit update. Actually clock was stopped but the status bit was not set in EQ_CLOCK_STAT register. Key_Cronus_Test=PM_REGRESS Change-Id: I7e8dbea00235ade5a692198dde7c2e6758809b9f CQ:SW443537 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65360 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65364 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add TLBIE WATNick Klazynski2018-08-291-0/+17
| | | | | | | | | | | | | | | | Change-Id: I862f3b5f6deaebc52f3dd4a6cf601b9ea2a214f4 CQ: HW440920 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65191 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65298 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* prevent NVDL recal_abort to OBUS PHY during SMP usageJoe McGill2018-08-291-12/+28
| | | | | | | | | | | | | | | | | | | | | | | p9.fbc.scan.intifile scan init NVDL pipe to drive recal_abort low, on Cumulus only chip_ec_attributes redefine feature attribute for 404391, to skip SCOM based glsmux X-state workaround sequence on Cumulus and use SCAN inits for all functional OBUSes Change-Id: I272392618b3e60e4c05b54f1cdf652871de717cb CQ: SW442771 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64749 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64795 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "lpc_init: Correct LPC host controller timeout value"Jennifer A. Stofer2018-08-291-1/+1
| | | | | | | | | | | | | This reverts commit 77b6c7e6b123b32e37d07db91b0478a938a4d4a7. Change-Id: I95ffbf3404932c027093ea614ff979178292edeb Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65113 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65129 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* lpc_init: Correct LPC host controller timeout valueJoachim Fenkes2018-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The LPC host controller has an interesting way to decode the timeout value. The left 4 bits are used for the "short wait" timeout, while the entire 8 bits are used for the "long wait" timeout. If the "short wait" timeout is 0xF, it is taken to be infinite, causing the host controller to hang if the slave doesn't respond. Change the timeout value from 0xFE to 0xEF, the correct maximum value that is not decoded to be infinity. Change-Id: Iaf1a5119a87338c24b1e324d814ade0b30353360 CQ: SW442999 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64850 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64856 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable Core compatability Mode; Add HW443669Nick Klazynski2018-08-291-0/+41
| | | | | | | | | | | | | | | | | Change-Id: I7298d0ac0d7b9eb37213b9ad0b5571c480deaee2 CQ: HW443669 CQ: SW442796 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64432 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64440 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Use core target for HRMOR/URMOR scoms in p9_sbe_load_bootloaderDean Sanner2018-08-291-2/+2
| | | | | | | | | | | | | | | -Code was using EX target, which only results in core 0 working Change-Id: I2106a836f9ab73b32a37665758fbc6f8ab3a888c Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64403 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64404 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* nest updates for p9c DD1.3 native and p9c DD1.2 compatibility modesJoe McGill2018-08-293-14/+36
| | | | | | | | | | | | | | | | | | | | | | | HW 446279 - disable update for compat and native modes HW 439321 - disable update for compat, enable for native mode HW 443004 - disable update for compat and native modes HW 446453 - disable update for compat, enable for native mode Change-Id: I3dd1ed6075ff473adbaf342671dd977c53fb2f06 CQ: HW446279 CQ: HW439321 CQ: HW443004 CQ: HW446453 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64067 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updates to permit synchronized SS PLL spreading via TODJoe McGill2018-08-294-14/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create EC feature attribute and user override attribute to control application of synchronized spreading. Default to enable synchronized spreading on Axone only. p9_sbe_npll_setup Conditionally skip existing unsynchronized spread enablement p9_tod_init Conditionally invoke spread sync routine after TOD network is running p9_ss_pll_sync Remove from repository, shift code into p9_tod_init to prevent need for mirroring into downstream repositories for FW consumption Change-Id: Ic32c800d58c260136b45fe9561989987d0a97ceb Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63494 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63503 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SMF: SBE updates for SMF (URMOR set and CPMMR[Runtime Wakeup Mode] clear)Greg Still2018-08-294-28/+93
| | | | | | | | | | | | | | | | | | - set URMOR if MSR[S] bit is set in p9_sbe_load_bootloader - clear CPMMR[Runtime Wakeup Mode] in all cores in p9_sbe_select_ex to ensure Hostboot starts from known state Change-Id: I572a1d9e0ebf8e194c811e2b8c176d145b7361e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61812 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61817 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Introducing lpc utils source filespashabk-in2018-08-281-0/+24
| | | | | | | | | | | | | | | | | Including the dummy file so that the platforms could mirror this file without breaking existing implementation. Will follow up with separation of lpc_rw into source file on top of mirrored commits Change-Id: I4596af3a8740cb9593f135a0138e84299a5946ac Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64298 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65269 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* HCODE Make divide using DERP/DORP atomicDouglas Gilbert2018-08-231-1/+7
| | | | | | | | | | | | | | Change-Id: Ib7e1c88f7ac934ba551082f27231fff1bb3961dc CQ: SW443103 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64570 Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64578 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Avoid enabling smf bits in nmmu logic for P9Jenny Huynh2018-08-111-17/+0
| | | | | | | | | | | | | | | | | | No secure accelerators in P9, so avoid enabling nmmu smf bits that will otherwise cause sm table walk hangs. Nmmu will gate off addr15 when mm_cfg_xlat_ctl_urmor(0:2)=0b000. Change-Id: Ib008d6be5d32f45ebb2b66600e45828decf6fbf4 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64064 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Emmanuel Sacristan <esacris@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64070 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* apply INT ARX clock gate disable to p9n DD2.0 hardwareJoe McGill2018-08-061-1/+1
| | | | | | | | | | | | | | | Change-Id: Id0d49c9146b990a8048a00abb7a2e4a6b2e9784a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63715 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63730 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Prevent Core-L2 Quiesce from removing PM_EXIT upon SPWUYue Du2018-08-011-1/+11
| | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I34f08519d2c86fec2f0ee0feb96a62bd826e31fa CQ: SW440301 cmvc-prereq: 1063483 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61438 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62502 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Validate OBUS DL lane failed indications during initial link trainingJoe McGill2018-07-311-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Under certain circumstances, the DL logic can consume a spare lane during training, reporting that the link trained successfully but without reporting a lane sparing event in the FIR This commit adds a change to check for failed lanes in this case, and: - raise the lane spared indication in the FIR if a single lane is spared (no HWP error returned, but attention can trigger MFG IPL failure) - mark the link as failed to train if more than a single lane is marked spared, to trigger reconfig loop Change-Id: Iecc69bb1cad172d9c0b16c9b987cc6896e46216b CQ: SW439577 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63383 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63394 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disable HW439321 workaround in dd1.3Adam Hale2018-07-311-0/+17
| | | | | | | | | | | | | | Change-Id: Iefeff37efedc89567c229c1780ce0054b8279b36 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63221 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63371 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable CDD1.3's 4 risklevels (step 1)Nick Klazynski2018-07-271-6/+64
| | | | | | | | | | | | | | | | | | | | | | | | Risklevel 0 - DD1.2 compat, non-HANA (variant1/2 secure) Risklevel 1 - DD1.2 compat, HANA (no security) Risklevel 2 - Unused Risklevel 3 - Unused Risklevel 4 - DD1.3 native, non-HANA (variant1/2 secure) Risklevel 5 - DD1.3 native, HANA (no security) Step 2 will involve disabling all fixes to make CDD1.3 RL0/RL1 identical to CDD1.2 RL0/RL1. Change-Id: Ic7f031c97f2616a0eec0a965c52dcaed3ec698e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62935 Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62984 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_lpc_init: Improve resetJoachim Fenkes2018-07-272-13/+17
| | | | | | | | | | | | | | | | | | | | | | | The sequence to switch the LPC HC clock onto the nest clock temporarily was incorrect as it used the TP CPLT_CTRL0 register inasted of N3, so it never really switched the clocks during reset. Also, for good measure, keep the clock switched to the nest clock while we're resetting the LPC bus. (Bonus change: Decrease the sim delay cycles waiting for a command to complete.) Change-Id: I5e77fa056204639a96aad9c1eec4b7bc76d8e54b CQ: SW439536 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63279 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63286 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove ATTR_PROC_CHIP_MEM_TO_USEDan Crowell2018-07-271-12/+0
| | | | | | | | | | | | | | Cleaning up deprecated code Change-Id: I83d38acc12588ec2c1954920cfb083b0d0190aee Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63043 Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63159
* Initf procedure updates for CumulusAnusha Reddy Rangareddygari2018-07-272-4/+121
| | | | | | | | | | | | | Change-Id: Ieba2a677f48c9632e41020b9a48be7375c6eb31a CQ: SW437518 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62384 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62400 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Handling special wakeup assert/deassert mis-match in PM Reset/Init on MALFAmit Tendolkar2018-07-222-4/+16
| | | | | | | | | | | | | | | | | | | | - Skip deassert special wakeup in PM Init when in PM Malf path - Attribute changes to default HB to disable MALF and PM FFDC enablement on IPL - Attribute to track Malf Flow across PM Reset and Init - Do not fail PM reset in Malf Flow, if auto special wakeup could not be set Change-Id: I5c730c818bbf886b8db7fc497cfb62c7a6c9c7f0 CQ: SW437841 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62528 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62541 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.pci.scan.initfile -- replace 62028 implementation with initfile entryJoe McGill2018-07-192-111/+0
| | | | | | | | | | | | | | | | | | | | | | 62028 added a workaround for SW 430383, using a manual re-scan of the ring hardcoded to flip the desired bits because engineering data was not yet available for the necessary spies This commit removes the SBE manual scan sequence and sets the necessary chicken switches by the newly added spy entries Change-Id: I912f190ab44c320f9bd142ce626570d34ec0b00f CQ: SW438480 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62675 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62710 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: remove chiplet enable drop in core_poweron for multicast scomYue Du2018-07-181-4/+1
| | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I388c81cc1af356231daa4a11702a3a84dcc222c9 CQ: SW437797 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62302 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62326 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- set XSCOM BAR in secure memory with SMF enabledJoe McGill2018-07-183-0/+30
| | | | | | | | | | | | | | | Change-Id: I7e3b39bb75ad8ee3983f4b4352d08369fe6bfc5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62065 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62074 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Avoid spurious Malf Alert (HMI) to PHYP in PM Complex Reset/SuspendAmit Tendolkar2018-07-131-0/+7
| | | | | | | | | | | | | | | | | | | Reseting the engines potentially causes another to send the PM Malf Alert to PHYP. Disable in PM Reset and let SGPE re-enable in PM Init. Added a similar safe check and disable in MPIPL path for pm_suspend Change-Id: If9fd572d156a8f280b0fd204175e5ccf0969b249 CQ: SW436905 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62135 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62298 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Clockgate disable workaround for HW452921Nick Klazynski2018-07-131-3/+3
| | | | | | | | | | | | | | | Change-Id: I09ec35894a488f0c9e2b03d8726b3a5a3ce08fcf CQ: HW452921 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62048 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62067 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cleanup: Updated Mvpd access function and removal of unused ringsClaus Michael Olsen2018-07-133-18/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Removed the function that converts the outdated RS4v2 header format to the current RS4v3 header format in the Mvpd accessor functions, mvpdRingFundFind(). This can be done since all Mvpd in existance on any of our supported P9 systems (i.e., >=P9N DD20) use RS4v3. - Removed two #R rings which are no longer supported since P9n DD10. Because these rings happen to be located at the end of the TOR instance ring sections, it will alter the image, but will not interfere with the traversing of the ringSection image due to the way chiplet and common/instance sub-sections are partitioned. Key_Cronus_Test=XIP_REGRESS Change-Id: I39740a099b224bfade8a97a057453b85498e5880 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61100 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Michael C. Sgro <mcs793@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61288 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Marking CME sram addr and cntrl register for whitelistPrasad Bg Ranganath2018-07-131-0/+4
| | | | | | | | | | | | Change-Id: I480a7bb511718cbd2e04a2ca5b41585ce9ce1606 CQ:SW437569 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61879 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61881
* Secure memory allocation and setupJenny Huynh2018-07-129-16/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_mss_eff_grouping.C: - determines whether secure mem is requested, reserves smf space - always reserve smf at end of range because of end-of-range bit - set addr15 when reporting smf base address - mask off group_id(0) via chip address extension if smf is enabled - updated to set value of attr_smf_enabled - enhanced error reporting with smf config/supported values - made values reported to attr_mss_mcs_group_32 more clear p9_mss_setup_bars.C: - set MCFGPA/MCFGPMA registers with SMF data - fixed scom registers for MCFGPA/MCFGPMA hole setup - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711 - added assert to check for HOLE1 and SMF enable overlaps p9_query_mssinfo.C: - updated to print out SMF reservations - print out HTM/OCC/SMF reservations regardless of mirroring enable p9_fbc_utils.C: - prevent group_id(0)=1 from affecting mappable memory ranges p9_sbe_fabricinit.C: - mask off group_id(0) via chip address extension if smf is enabled p9_setup_sbe_config.C, p9_sbe_attr_setup.C: - use scratch_reg6 bit(16) to pass smf_config value initfiles: - removed setup to use other addr bits as secure bit; core only uses addr15 - added setup for ncu addr15 value in hcode - always set addr15 config bit in bridge unit if smf is supported - set addr15 bit across all mcs if smf is enabled - added in settings to enable smf in nmmu unit - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported attributes: - ATTR_SMF_ENABLE is a system level attribute - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported) CQ:HW451708 CQ:HW451711 Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Inverted logic of hasClock bit in Clock Status registerRaja Das2018-07-121-0/+4
| | | | | | | | | | | | | CQ: SW437571 Change-Id: I9101adc63225a97aeddf445519fa660d961c3d9c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61463 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61471 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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