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* TOR space reductionsMartin Peschke2017-01-258-906/+933
* dd1 workaround for hw400075 coherency errorShelton Leung2017-01-251-0/+17
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2017-01-241-0/+17
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-01-243-92/+29
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-01-243-3/+34
* p9_sbe_attr_setup optimizedAnusha Reddy Rangareddygari2017-01-241-35/+13
* p9_sbe_tp_chiplet_init1 optimizedAnusha Reddy Rangareddygari2017-01-241-26/+22
* p9_pm_pstate_gpe_init Level 2Greg Still2017-01-241-0/+32
* FBC updates for HW383616, HW384245Joe McGill2017-01-242-2/+36
* Updating P9 L2 scan initfile to use attributesLuke Murray2017-01-241-0/+34
* Added Quad Power Management Mode Register Clear for Quad Power HwpRaja Das2017-01-231-1/+10
* Adding chip_ec_feature attributes for dd2 buildBen Gass2017-01-221-0/+1312
* Adding skip group dials for cache when chip=groupLuke Murray2017-01-222-0/+54
* Changing ttype to dma for MPIPL runsCHRISTINA L. GRAVES2017-01-221-2/+13
* Set plck as default mode in ATTR_BOOT_FLAGSSantosh Puranik2017-01-221-1/+1
* istep 4: only use one EX even if both are goodGreg Still2017-01-192-20/+47
* PK: make GPE using 8B in64/out64 opYue Du2017-01-181-31/+0
* MCS FIR updatesJoe McGill2017-01-182-5/+1
* p9_sbe_startclock_chiplets optimizedAnusha Reddy Rangareddygari2017-01-181-146/+45
* p9_sbe_chiplet_pll_setup optimizedAnusha Reddy Rangareddygari2017-01-181-162/+111
* SGPE HWP : tune PFET controller pollingAmit Kumar2017-01-171-2/+7
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-172-6/+32
* PK stack checkingDoug Gilbert2017-01-175-9/+50
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-01-161-0/+18
* Modify signature of p9_stopclocksspashabk-in2017-01-162-70/+99
* p9_stopclocks SBE/PPE related changesspashabk-in2017-01-164-31/+205
* Implementation of PIB stopclock with CBSSoma BhanuTej2017-01-164-51/+231
* Adding bool for cache/cores in the p9_stopclocks HWPSoma BhanuTej2017-01-162-9/+25
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2017-01-161-3/+3
* Stopclock procedure updatesSoma BhanuTej2017-01-164-56/+110
* Fixing a bug in stopclk cmn module - p9_common_stopclocksSoma BhanuTej2017-01-162-3/+3
* Fapi Implementation of Level2 HWP p9_stopclocksSoma BhanuTej2017-01-1610-19/+1060
* Level 1 HWP for p9_stopclocksSoma BhanuTej2017-01-162-0/+150
* configure FBC pump mode in SBEJoe McGill2017-01-158-118/+95
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-01-151-0/+34
* Add new core workarounds, defect inline in the initfileNick Klazynski2017-01-131-3/+3
* SW375288: Reads to C_RAS_MODEREG causes SPR corruptionNick Klazynski2017-01-111-13/+19
* Enable imprecise mode only for CMEPrasad Bg Ranganath2017-01-101-2/+0
* Enable QUEUED SCAN in CME putring codePrasad Bg Ranganath2017-01-101-1/+3
* HW398189: mask SIBRC = 6 in CME MSR under NDD1Yue Du2017-01-082-2/+28
* Increasing delay for l3_flush based on HW requirementsCHRISTINA L. GRAVES2017-01-061-2/+2
* ISTEP4: using FAPI_ASSERT instead of manual fapi_rc_falseYue Du2017-01-041-38/+33
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-041-35/+1
* Change MCFIR_CHANNEL_0_TIMEOUT_ERROR to be maskedBrian Silver2017-01-041-2/+1
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-01-041-19/+1
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-01-042-18/+27
* Hcode: add a new xml error fileYue Du2017-01-042-1/+39
* PK Support for 1.125 timebase scaleDoug Gilbert2017-01-031-6/+12
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2017-01-011-0/+18
* HCODE: Drop TLBIE Quiesce after initfile scan it to 1Yue Du2016-12-201-2/+2
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