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path: root/src/import/chips/p9/procedures
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* Leave scratch valid bits alone to allow HB to queryDean Sanner2018-11-291-15/+4
* Adding omi_init procedures.Ben Gass2018-11-251-0/+34
* Adding p9a_ocmb_enableBen Gass2018-11-201-0/+12
* HW471413 Aggressive Uncle: disable ERAT thread sharingJenny Huynh2018-11-111-5/+12
* p9_sbe_tp_chiplet_init: Fix missing semicolonsJoel Stanley2018-11-011-2/+2
* Revert "Clear INT_CQ related firs after completing sync_reset in MPIPL"Christian R. Geddes2018-11-012-51/+0
* Clear INT_CQ related firs after completing sync_reset in MPIPLChristian Geddes2018-11-012-0/+51
* Img Build: HOMER changes for SMF and SPR self save.Prem Shanker Jha2018-10-291-0/+24
* PM: Fixed handling of CME LFIR mask during PM complex reset.Prem Shanker Jha2018-10-241-1/+1
* Only save the CME FIR Masks after they have been setup onceDan Crowell2018-10-241-0/+1
* Enforce SMF size requirements and correct valid bitJenny Huynh2018-10-171-5/+1
* HW467590 - WAT Solution to prevent ARMWF starvation early hangAdam Hale2018-10-151-0/+19
* Update Axone engd.Ben Gass2018-10-111-18/+7
* Mask NMMUFIR(7), NMMUFIR(36:39)Jenny Huynh2018-10-091-2/+2
* SMF: clear HRMOR[15] in all modes so that secure mode won't hang coreGreg Still2018-10-051-5/+7
* Removes unused attribute accessorsStephen Glancy2018-10-041-1/+0
* STOP:Dont clear pmc_pcb_intr_type0_pending in OISR1/OIMR1 registerPrasad Bg Ranganath2018-09-271-15/+26
* Back out p9a_10 engd that breaks the initcompiler.Ben Gass2018-09-271-0/+18
* Mask early hang indicators from nmmu/vas unitJenny Huynh2018-09-261-4/+4
* Support ATTR_LPC_CONSOLE_CNFG attributeSachin Gupta2018-09-262-0/+15
* Update p9a_10 engd from o10_e9018_1_tp018_ec409_soa_sc_u261_01Ben Gass2018-09-241-18/+0
* Attribute cleanupDan Crowell2018-09-212-98/+30
* Support 1byte data access on LPCspashabk-in2018-09-212-6/+40
* Move lpc_rw to a source filespashabk-in2018-09-193-66/+83
* RAS_XML: updates to sync the XML with actual values from hardwareZane Shelley2018-09-172-1/+19
* IPL/STOP: Disable LCO when only two EXes are configuredYue Du2018-09-171-13/+1
* SW427193 / HW461448: Enable memory controller watJenny Huynh2018-09-121-0/+21
* Revert "UV Support : Augmented STOP API and self restore for enabling UV"Prem Shanker Jha2018-09-121-24/+0
* Axone only-IPL Procedures update to support SBE changesAbhishek Agarwal2018-09-104-35/+219
* Axone only-Mux settings for TOD refclk inputAnusha Reddy Rangareddygari2018-09-101-0/+13
* get FAPI_POS for all valid target types passed in SBE FIFO ffdcRichard J. Knight2018-09-071-1/+3
* Initf procedure updates for Axone OMI ringsAnusha Reddy Rangareddygari2018-09-073-2/+83
* p9_sbe_lpc_init: Skip final error check for Fleetwood GA1Joachim Fenkes2018-09-071-0/+2
* Revert "Initf procedure updates for OMI rings for Axone"Jennifer A. Stofer2018-09-073-65/+2
* Initf procedure updates for OMI rings for AxoneAnusha Reddy Rangareddygari2018-09-073-2/+65
* UV Support : Augmented STOP API and self restore for enabling ultravisor.Prem Shanker Jha2018-09-061-0/+24
* PM:Some more cleanups in update_ec_eq procedure for core unit xstop casePrasad Bg Ranganath2018-08-314-0/+79
* Add TLBIE WATNick Klazynski2018-08-291-0/+17
* prevent NVDL recal_abort to OBUS PHY during SMP usageJoe McGill2018-08-291-12/+28
* Revert "lpc_init: Correct LPC host controller timeout value"Jennifer A. Stofer2018-08-291-1/+1
* lpc_init: Correct LPC host controller timeout valueJoachim Fenkes2018-08-291-1/+1
* Enable Core compatability Mode; Add HW443669Nick Klazynski2018-08-291-0/+41
* Use core target for HRMOR/URMOR scoms in p9_sbe_load_bootloaderDean Sanner2018-08-291-2/+2
* nest updates for p9c DD1.3 native and p9c DD1.2 compatibility modesJoe McGill2018-08-293-14/+36
* Updates to permit synchronized SS PLL spreading via TODJoe McGill2018-08-294-14/+76
* SMF: SBE updates for SMF (URMOR set and CPMMR[Runtime Wakeup Mode] clear)Greg Still2018-08-294-28/+93
* Introducing lpc utils source filespashabk-in2018-08-281-0/+24
* HCODE Make divide using DERP/DORP atomicDouglas Gilbert2018-08-231-1/+7
* Avoid enabling smf bits in nmmu logic for P9Jenny Huynh2018-08-111-17/+0
* apply INT ARX clock gate disable to p9n DD2.0 hardwareJoe McGill2018-08-061-1/+1
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