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* HW405413 : NCU sends data out of orderAlex Taft2017-09-121-0/+17
| | | | | | | | | | | | | | Serializes the data. Apply to DD1 only and risk_level 0 Change-Id: Id798a18dfef6022724ff49a33a7a9458e8aa3a87 Original-Change-Id: I4aa5d35b04afec2c20c7f6ea5d732210d1fe2f97 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37643 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Scrubbing needs to stay off for DD2, bug HW405443Juan Medina2017-09-121-1/+2
| | | | | | | | | | | | Change-Id: I777e6b8642b0a5f31345e9545ef59c0812d62178 Original-Change-Id: I1421f90e1e6fe4b1e8cd73a9124daddade4026c8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37666 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* PM: GPE timer fix (HW389045 - Update Shadow copy of TSEL)Greg Still2017-09-121-0/+17
| | | | | | | | | | | | | | | | - Tested in Cronus with U.H to pick up init from hw_image. - For Firmware, this change is needed in the SBE image!!!! Change-Id: I9f52968efe5e546011c23c91a609a7abaca5a555 Original-Change-Id: Ia8b087db972f6974d1ef6fbbda5dc4fb92e41693 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37508 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Set NDL IOValids based on configured NV links.Ben Gass2017-09-121-0/+36
| | | | | | | | | | | | Change-Id: I31fcb6ec160986116510d852b63385b4556096c8 Original-Change-Id: I8dfc5410f4f4e6ec4b6fc6dc16b54b99da8f1641 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37375 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DARREN J. DUFFY <darren@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* p9_start_cbs updatesAnusha Reddy Rangareddygari2017-09-121-0/+18
| | | | | | | | | | | | | | | | | | | Adding delay to wait for PibReset to complete Change-Id: I2dc75f00a68cb063c8f47fe44b910038b2834584 Original-Change-Id: I79c9f591102c0114810348647c38d4b7fb762076 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37161 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Dev-Ready: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* enable prefetch drop for better MC fairnessShelton Leung2017-09-121-1/+18
| | | | | | | | | | | | Change-Id: Ib1a66f5bda49f1e72bc3d2cf52dff2f659d86ae2 Original-Change-Id: I0fee2fe19b703e090ad2364a2a38dac31079b38f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37010 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Reducing rng pace rate from 2000 -> 300 for HW403701Jenny Huynh2017-09-121-0/+17
| | | | | | | | | | | | | Change-Id: Ie664f9d9d6ba111cc0bfbde3f00b2726c89e4bc1 Original-Change-Id: I263cf15a6fa3a375590c813536f4b52ce915c4bd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36919 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Dev-Ready: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Updates to run HW VREF cal by defaultStephen Glancy2017-09-121-0/+34
| | | | | | | | | | | | | | | | | | | | | | This code runs the HW VREF calibrations (both WR and RD VREF) by default if it is supported by the HW. Four new attributes are added to handle whether HW VREF cal should be run and with what overrides it needs to be run. Change-Id: I89f3d2abea9a16ceecd2e7e9552f5ed27135b2f3 Original-Change-Id: I3ed63794e955ee8c94cffce0b98dba58886e4a9d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36803 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: RYAN P. KING <rpking@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* adjust SRAM timingsJoe McGill2017-09-121-19/+2
| | | | | | | | | | | | | Change-Id: Ic3e5e66c9076c021d023f1bc5d745e761a413ec6 Original-Change-Id: Iae2a281eeebe46f316dc4c7d23e869f103b88abb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36892 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* New dummy pulse pok bits (for L2/L3)Alex Taft2017-09-121-0/+34
| | | | | | | | | | | | | | | | CAY_L2C_A102_MAC & CAY_L3DIR_MAC L2 cache and L3 Dir/Lru arrays. Change-Id: Ie9ea5fb41e35a64e365cd7710a83c2767ff0cfc1 Original-Change-Id: Ib1912c9382a4cd5ce14488683b9b145a0f472d7b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36819 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* NPU scan/scom init updatesRyan Black2017-09-121-0/+17
| | | | | | | | | | | | | | | | | | | p9.npu.scan.initfile initial release, mask updates for HW403585 p9_npu_scominit configure XTS ATRMISS register Change-Id: Ib911d6d083738996fd39dd4b17da36f8dd55f259 Original-Change-Id: Id77aad7833a7fe0c3ab2cf0710a63b215a966a80 CQ: HW403585 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36393 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: RYAN BLACK <rblack@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com>
* Add three WATs, remove IMC2, replace stop2 workaroundNick Klazynski2017-09-121-1/+52
| | | | | | | | | | | Change-Id: I223e430176d5def0a36dc3f25d93e47c4e08363a Original-Change-Id: Idb63b61235cfbb7ac3345f6f1e3c0b5dd4738a50 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36735 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2017-09-121-0/+20
| | | | | | | | | | | | | | Change-Id: Ie974183447ac1a72206277ec1ce6dbf7239cdf9e Original-Change-Id: If02e5e31c768c62bbdf37c15b5146bacaaf38d80 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36173 Dev-Ready: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-09-121-0/+16
| | | | | | | | | | | | Change-Id: I514bf9635b8b534b577b97e922dc68cc7d3e5371 Original-Change-Id: Ia7ffcfdead79e859f21b95be183af05949e68579 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36276 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Thi N. Tran <thi@us.ibm.com>
* reverting FIRs to master values, setting only bit 8Juan Medina2017-09-121-0/+19
| | | | | | | | | | | | Change-Id: Ib3c25e8ac1c98e7709d08e897f071e4e9c791e06 Original-Change-Id: I9ff37faffad1c6c2323c501a5c55992a81fc9fd8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35575 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* adding insert for soft fail threshold for dd1 and dd2Joshua Hannan2017-09-121-0/+17
| | | | | | | | | | | | | | Change-Id: I98938e23945522e688794df3b6347d8451321d43 Original-Change-Id: I4d3be984693aa758874ee22761c55f7508cd0ff9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36301 Dev-Ready: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modesNick Klazynski2017-09-121-2/+53
| | | | | | | | | | | | Change-Id: I3e6391c2d1d1c778ea598d3d8cabf5674528e192 Original-Change-Id: I6a6803cc0f3571d41ae3e5fa501b89609b88d525 CQ: HW401811 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36063 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* amo cache disabled for dd1 for HW401780Shelton Leung2017-09-121-0/+17
| | | | | | | | | | | | | Change-Id: Ic4838a9978f1502565401df350bd8245cc5f871f Original-Change-Id: Iad3918c1d7e54b55ecc61f6d66181f0c05b1064a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35839 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Adding HW363780 to NPU scom initfilesJenny Huynh2017-09-121-0/+18
| | | | | | | | | | | | | | | NPU fir bit can fire for any rcmd snoop that misses in the table lookup. Masking for nimbus dd1 only. Change-Id: I91c52ff7fbcbbf0575afcb6ddec9026bf691465e Original-Change-Id: I0651b37279b0cee4ca5d383d83f0eb1079b75bd1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35676 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* workarounds for HW399919 HW400898 HW398269 HW398269 HW399765Nick Klazynski2017-09-121-0/+137
| | | | | | | | | | | | | Change-Id: Ieb6222aedbdc6d7f2c1022a29f81313c1b3d8fe9 Original-Change-Id: Id84495c3b83d75e8fddd4833f04ec23614d223e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35406 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-09-121-0/+18
| | | | | | | | | | | | | | | Change-Id: Ie727889bb62d1b200e2d690a9942bb62dcddbf79 Original-Change-Id: I8c55c2947dd85cc9ada45aaa9225ce641633f259 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35239 Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* workaround for hw400932 atag corruptin in prespShelton Leung2017-09-121-0/+17
| | | | | | | | | | | | | | Change-Id: Ibd8feaad0f8602b0698c2fab2917ea987eab8098 Original-Change-Id: I4a90407ed6fbf4bb9dbf64ee7e9c26b1e179784b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35287 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* dd1 workaround for hw400075 coherency errorShelton Leung2017-09-121-0/+17
| | | | | | | | | | | | Change-Id: Ifbe2747adbbea13758d2ab735d9bc892cac7f5a2 Original-Change-Id: I09ba40e8b92f7800a4843ff562cea3fbb75383c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35235 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-09-121-19/+1
| | | | | | | | | | | | | | cq : HW399324 Change-Id: Ibd036f5a736d1db26c1090cf27818d6979edee1d Original-Change-Id: I4236b25b2587cb9705632dd55077c79e3d5cf246 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34827 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2017-09-121-0/+17
| | | | | | | | | | | Change-Id: Iff4af6547ce5119ca03fad6094d2fc5dae98df6b Original-Change-Id: I1176cf9eba88a9f4f0b0309d15a44c45caf73ef9 CQ: HW401249 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35231 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-09-121-0/+17
| | | | | | | | | | | Change-Id: I11c9c68ed140ab8593a1a6eee54c9dd3ee2464d3 Original-Change-Id: I838703170232b7ad39ae752f0fcde996f5bd577e CQ: HW401184 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Updating P9 L2 scan initfile to use attributesLuke Murray2017-09-121-0/+34
| | | | | | | | | | | | | | Change-Id: I3d196497212bf955a2241e1999d43992fcdce217 Original-Change-Id: I8aa808d2f0f3af8325af6900a0ec9fd5521183e5 RTC: 167767 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35194 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* FBC updates for HW383616, HW384245Joe McGill2017-09-121-0/+36
| | | | | | | | | | | | | | Change-Id: I06b770004a69f6328c98183c2e5817fce2167ec1 Original-Change-Id: I3b65925b1cadb6f4db5d64868f997ebf4ff7e625 CQ: HW383616 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34810 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Adding skip group dials for cache when chip=groupLuke Murray2017-09-121-0/+41
| | | | | | | | | | | | | | | | | | The L2 dial is a scomable dial for DD1, but the NCU and L3 dials are not scan only for DD1. So the NCU and L3 have two dials one used in DD1 and one for after DD1. Change-Id: Ic5f0f33fc38ef1b2771ae7228d099e7c4b1e03d1 Original-Change-Id: Ica63b417ae79b3b5a230c8034fd6f76b982df23b RTC: 167679 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34857 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Adding chip_ec_feature attributes for dd2 buildBen Gass2017-09-121-0/+1312
| | | | | | | | | | | | | | | | Resulting dd10 hw_image file matches the one generated from initfiles in master. Grub boots with resulting image and procedures. Change-Id: I80ca15537dd36f1067427c28444dbdc7cd6f977e Original-Change-Id: I2257448a7dcdb6be44da6196da847cca8ad4077d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34736 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-09-121-0/+18
| | | | | | | | | | | | | support PCIE on DD1.x by lowering input refclock Change-Id: If50bd3441437f6f534e95c981e337dd9f3ef1168 Original-Change-Id: Ic69f0b4cdcba9d667d08aa37aced6dbc4c156c98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34389 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-09-121-0/+34
| | | | | | | | | | | Change-Id: I550eda2ba9c5568c074f15796cb1498895f0027d Original-Change-Id: Ibef138e8d727c55ee564ffe2ee422fc79550162e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34676 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-09-121-35/+1
| | | | | | | | | | | | | | | | | Keyword V0 offsets are the same as V1 Move bad-bits error processing to 1.03 Change-Id: I8d48ae6ca0b6483b0e2612753717db202d574706 Original-Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-09-121-18/+0
| | | | | | | | | | | | Change-Id: I870a801241e038441b3d35ede7014f5fcabb0c12 Original-Change-Id: Ia36d3ed31614976c25bef144c45396f577f037b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33401 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2017-09-121-0/+18
| | | | | | | | | | Change-Id: I61596dae0b45fd857e096176b8b529f666137a89 Original-Change-Id: I7004f226a353e9075e8fe32e3bc157a58c36b4b5 CQ: HW397255 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33952 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2017-09-121-0/+17
| | | | | | | | | | | | | Change-Id: I0183834889cdd3bdf87803adff0ccad670c03168 Original-Change-Id: I6575ec51a94024708611678bee7af0cf7819b206 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33362 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: ADAM S. HALE <ashale@us.ibm.com> Dev-Ready: ADAM S. HALE <ashale@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Add Memory Subsystem FIR supportBrian Silver2017-09-121-0/+17
| | | | | | | | | | | | | | | | | | | Add FIR.md to memory/docs Change some PHY workarounds, lab says hold off Add MC FIR to SBE code Change-Id: I81b4594e405c5ef8c283856c761c95f6e0e9d9ca Original-Change-Id: I904079ab84d978637dd2b3e638c90d59395019fd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33060 Dev-Ready: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Adding in defect HW395947,HW930007 to INT initfilesJenny Huynh2017-09-121-1/+72
| | | | | | | | | | | Change-Id: I6c468c6cccca9cccf5ec86a983f05a6b6cfc2e3f Original-Change-Id: Iff8bed55ac363c8bd881fcc06f9cd3cd40261e15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33369 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Add EC workaround for PHY training bad bit processingBrian Silver2017-09-121-1/+20
| | | | | | | | | | | | | | | | Change-Id: I1506878ec0951335f62dacb24011806413d74f08 Original-Change-Id: Ia23b7bb80ae0875c869104b0557e7758d4df80a5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33465 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Dev-Ready: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
* scan inits for lab workaround for DI bug HW392781Shelton Leung2017-09-121-0/+17
| | | | | | | | | | | Change-Id: Id963b7e3d836a7be9758201465759b2cd53ec94c Original-Change-Id: Ia71c4d0933112c6804774b76a08ec5fbbe254833 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32780 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2017-09-121-0/+16
| | | | | | | | | | Change-Id: Iae39f526583ebd113712fa646348186df3a89b29 Original-Change-Id: I019d7ba16b4e39b5cf140fe1461218736ce329f5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Adding workaround for HW930007 and HW386013Jenny Huynh2017-09-121-0/+18
| | | | | | | | | | | | | Change-Id: I08a2c5123ce90dcb5f96b32e364734a11dd3160f Original-Change-Id: I934d63af496da2789ab69d857afe36cb1657175c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31500 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2017-09-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | changes in this commit: 1) enable dpll lock checking in non-sim envrionment 2) change FAPI_DBG lines on set/reset sdis_n ops as removing prints saying they are DD1 only workaround due to they are permenant steps now 3) add missing content of p9_hcd_core_dcc_skewadjust 4) add DD2 sram_enable support (NOOP for DD1) Change-Id: I9a87c9fb68bd3b8df156ca07ba384e38cac85e94 Original-Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719 Reviewed-by: Joseph E. Dery <dery@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* Add EC feature levels to MSS workaroundsBrian Silver2017-09-121-12/+140
| | | | | | | | | | | | | Change-Id: Ie86b6483e0aaf131b37279dc3bb4ce50a0876a35 Original-Change-Id: Iec6db88808f26353ce88f9038222db12f2d9b6c0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32421 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* p9_psi_init -- parametrize link speed (half/full)Joe McGill2017-09-121-0/+18
| | | | | | | | | | | | | | | | Wrapper tested on zzfp033 Appears to correctly trigger half speed mode from FSP tool feedback $ cat /sys/devices/psi_link0/clock FSP-2, PSI(0) CLK overwrite: 1 Speed: 166 MHz Change-Id: I9002d3e6cfc018108cfe342964267372cb461827 Original-Change-Id: I45997c30e71457ceedfcba70550f0e6d98584a1e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31497 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* PPM reg collision (HW389511) work-around: Special Wake-upChristopher Riedl2017-09-121-0/+17
| | | | | | | | | | | | | | | | - fixed screwed-up/duplicate commits - addressed code review comments and implemented FAPI_ASSERT conditions for the error case(s) Change-Id: I71cbb7cb61e9452c95dba9c24d322603f10baba8 Original-Change-Id: I706b3247f0f9c3ea241ae2841fbce456577c78b6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31379 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
* p9.fbc.scan.initfile -- create initfile, add workaround for HW376651Joe McGill2017-09-121-0/+18
| | | | | | | | | | | | | Change-Id: Ie43c77a695ba7aa8f32278dd879c5c257cf439e5 Original-Change-Id: Iaccfdf902d179819549f46ddee65631873fa023e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31309 Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* HW388878 VCS workaroundJoe McGill2017-09-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | In pre-poweron HWP, Reset ROOT CTRL and PERV CTRL regs to cold IPL state Tested with poweron flow which: drops all rails (preserving Vstandby) executes pre-poweron HWP to reset cfam region regs enables rails (excluding VCS) executes cfam pop start sequence enables VCS rail Add defect number to feature attribute, used in all consumer HWPs Change-Id: I649ad1ae9ee62f27ad445a1663414e70ab07fd36 Original-Change-Id: I5bf5d61033bdca97527c8b499995eb6920ac1122 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31101 Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Cache HWP: DD1 VCS WorkaroundYue Du2017-09-121-0/+18
| | | | | | | | | | | | Change-Id: Ie1539ac675d2c66568feff5ad181005a4caec561 Original-Change-Id: I9634a767878904f810cb1e6a0767ba4bbad241cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30827 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
* Change chip to unsecure always for DD1 chipsSoma BhanuTej2017-09-121-0/+18
| | | | | | | | | | | | | Change-Id: I2d9b5d7136ff95b410e3acd0bf1b0ae76193d0ff Original-Change-Id: I73e2aace7ad9a56bfd528b4b2d82741148df971f RTC:158131 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30952 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
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