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path: root/src/import/chips/p9/procedures/xml
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* workarounds for HW399919 HW400898 HW398269 HW398269 HW399765Nick Klazynski2017-01-311-0/+137
| | | | | | | | | | | | | | | | Change-Id: Id84495c3b83d75e8fddd4833f04ec23614d223e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35406 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35534 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Control NDL training updateAnusha Reddy Rangareddygari2017-01-312-1/+14
| | | | | | | | | | | | | | Change-Id: I13d721d7fb1d71c58314dd1e09006a7b4df0dee2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35211 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35216 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-01-311-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I8c55c2947dd85cc9ada45aaa9225ce641633f259 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35239 Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35334 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* workaround for hw400932 atag corruptin in prespShelton Leung2017-01-311-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I4a90407ed6fbf4bb9dbf64ee7e9c26b1e179784b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35287 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35291 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* dd1 workaround for hw400075 coherency errorShelton Leung2017-01-251-0/+17
| | | | | | | | | | | | | | Change-Id: I09ba40e8b92f7800a4843ff562cea3fbb75383c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35235 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35258 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2017-01-241-0/+17
| | | | | | | | | | | | Change-Id: I1176cf9eba88a9f4f0b0309d15a44c45caf73ef9 CQ: HW401249 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35231 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35242 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-01-242-24/+2
| | | | | | | | | | | | | | | | cq : HW399324 Change-Id: I4236b25b2587cb9705632dd55077c79e3d5cf246 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34827 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34828 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-01-242-0/+21
| | | | | | | | | | | | Change-Id: I838703170232b7ad39ae752f0fcde996f5bd577e CQ: HW401184 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35202 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* FBC updates for HW383616, HW384245Joe McGill2017-01-242-2/+36
| | | | | | | | | | | | | | | Change-Id: I3b65925b1cadb6f4db5d64868f997ebf4ff7e625 CQ: HW383616 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34810 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34815 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updating P9 L2 scan initfile to use attributesLuke Murray2017-01-241-0/+34
| | | | | | | | | | | | | | | Change-Id: I8aa808d2f0f3af8325af6900a0ec9fd5521183e5 RTC: 167767 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35194 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35195 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding chip_ec_feature attributes for dd2 buildBen Gass2017-01-221-0/+1312
| | | | | | | | | | | | | | | | | | Resulting dd10 hw_image file matches the one generated from initfiles in master. Grub boots with resulting image and procedures. Change-Id: I2257448a7dcdb6be44da6196da847cca8ad4077d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34736 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34864 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding skip group dials for cache when chip=groupLuke Murray2017-01-221-0/+41
| | | | | | | | | | | | | | | | | | | | The L2 dial is a scomable dial for DD1, but the NCU and L3 dials are not scan only for DD1. So the NCU and L3 have two dials one used in DD1 and one for after DD1. Change-Id: Ica63b417ae79b3b5a230c8034fd6f76b982df23b RTC: 167679 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34857 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35108 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Set plck as default mode in ATTR_BOOT_FLAGSSantosh Puranik2017-01-221-1/+1
| | | | | | | | | | | | Change-Id: I1f9f8a5db4a152efa719fac3c53a0150dfb43ccc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35101 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35107 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | | For DD1.0[123], to obtain Gen3 or Gen4 operation, we need to run the PCIE clocks at a slower speed. For simplicity we will just do this across the board for all DD1.0 parts. 34389 updates the SS filter PLL to output a reduced frequency output (94 MHz instead of 100 MHz nominal) for DD1 only. This commit will trigger the SBE to use the SS filter PLL to feed the downstream PCIE PLLs, for DD1 only. Change-Id: I344455de1fc54e9180090740b5725d580cb35b6f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34985 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34996 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-01-161-0/+18
| | | | | | | | | | | | | | | | support PCIE on DD1.x by lowering input refclock Change-Id: Ic69f0b4cdcba9d667d08aa37aced6dbc4c156c98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34389 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34469 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* configure FBC pump mode in SBEJoe McGill2017-01-151-5/+4
| | | | | | | | | | | | | | Change-Id: Ia4e69cf50548e355cfb7cbf5e67be48e61427ffa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34318 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34348 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-01-151-0/+34
| | | | | | | | | | | | | | Change-Id: Ibef138e8d727c55ee564ffe2ee422fc79550162e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34676 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34681 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-041-35/+1
| | | | | | | | | | | | | | | | | | | | Keyword V0 offsets are the same as V1 Move bad-bits error processing to 1.03 Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34134 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-01-041-19/+1
| | | | | | | | | | | | | | Change-Id: Ia36d3ed31614976c25bef144c45396f577f037b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33401 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33402 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Hcode: add a new xml error fileYue Du2017-01-042-1/+39
| | | | | | | | | | Change-Id: If5c986034c3e7d0b9011cdfbbde99c62b38fba06 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34301 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34351
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2017-01-011-0/+18
| | | | | | | | | | | | | Change-Id: I7004f226a353e9075e8fe32e3bc157a58c36b4b5 CQ: HW397255 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33952 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33954 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-202-0/+21
| | | | | | | | | | | | | | | Change-Id: I6575ec51a94024708611678bee7af0cf7819b206 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33362 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: ADAM S. HALE <ashale@us.ibm.com> Dev-Ready: ADAM S. HALE <ashale@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33366 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Added support for CME/SGPE flags in respective image header.Prem Shanker Jha2016-12-201-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I0c49a550eb3afb85e88afa930b36e59ba338cfd2 RTC:160829 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29927 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: ADAM S. HALE <ashale@us.ibm.com> Dev-Ready: ADAM S. HALE <ashale@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29928 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add Memory Subsystem FIR supportBrian Silver2016-12-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | Add FIR.md to memory/docs Change some PHY workarounds, lab says hold off Add MC FIR to SBE code Change-Id: I904079ab84d978637dd2b3e638c90d59395019fd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33060 Dev-Ready: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33259 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding in defect HW395947,HW930007 to INT initfilesJenny Huynh2016-12-201-1/+72
| | | | | | | | | | | | | | Change-Id: Iff8bed55ac363c8bd881fcc06f9cd3cd40261e15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33369 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33424 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add EC workaround for PHY training bad bit processingBrian Silver2016-12-201-1/+20
| | | | | | | | | | | | | | | | | | | Change-Id: Ia23b7bb80ae0875c869104b0557e7758d4df80a5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33465 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Dev-Ready: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33468 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* scan inits for lab workaround for DI bug HW392781Shelton Leung2016-11-301-0/+17
| | | | | | | | | | | | | | Change-Id: Ia71c4d0933112c6804774b76a08ec5fbbe254833 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32780 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32822 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove unused SBE attributesSantosh Puranik2016-11-281-126/+1
| | | | | | | | | | | | | | | Change-Id: I9e7347b1508752bddf90d534edba27e0277b981d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32857 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32858 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Adding workaround for HW930007 and HW386013Jenny Huynh2016-11-211-0/+18
| | | | | | | | | | | | | | | Change-Id: I934d63af496da2789ab69d857afe36cb1657175c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31500 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31505 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2016-11-212-0/+20
| | | | | | | | | | | | Change-Id: I019d7ba16b4e39b5cf140fe1461218736ce329f5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32285 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_attr_setup updatesAnusha Reddy Rangareddygari2016-11-212-0/+5
| | | | | | | | | | | | | | | | | | | | | | set the ATTR_IS_SP_MODE attribute from MBX scratch reg 3 CQ : HW393961 Change-Id: Id1eb51173451680367de614c114bd0732a678e5b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32468 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32469 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-212-1/+22
| | | | | | | | | | | | | | | | | | | | | | | changes in this commit: 1) enable dpll lock checking in non-sim envrionment 2) change FAPI_DBG lines on set/reset sdis_n ops as removing prints saying they are DD1 only workaround due to they are permenant steps now 3) add missing content of p9_hcd_core_dcc_skewadjust 4) add DD2 sram_enable support (NOOP for DD1) Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719 Reviewed-by: Joseph E. Dery <dery@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31810 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add new attribute file that contains pervasive SBE only attrscrgeddes2016-11-151-0/+26
| | | | | | | | | | Change-Id: I9d8ff081b7b0b7068e45318c64d6d6c44e68ea43 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31274 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* MPIPL Start Chipops and Mpipl istep implementationRaja Das2016-11-111-0/+4
| | | | | | | | | | Change-Id: If0579dfdfb10eb42bc837107e38361512a416b03 RTC: 123696 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30367 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add EC feature levels to MSS workaroundsBrian Silver2016-11-101-12/+140
| | | | | | | | | | | | | | | | Change-Id: Iec6db88808f26353ce88f9038222db12f2d9b6c0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32421 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32426 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Customization of CME and SGPE rings in HOMER.Prem Shanker Jha2016-11-101-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Extracts rings from hardware image and VPD and stashes in to a temp buffer using HWP p9_xip_customize. Subsequently, using TOR API creates a fresh and leaner layout of scan rings in HOMER. - Implements a debug infrastructure to verify the scan ring layout in HOMER. - Implemented scan ring overrides for core common and cache common rings. - Introduces size check for various sections of HOMER. Change-Id: I8d7785f632823c31077bd4f320c453129be4ef0c RTC:157954 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27697 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30395 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* nest_attributes -- add initToZero tags for chip contained executionJoe McGill2016-11-101-0/+10
| | | | | | | | | | | | | | | | | | | init memory bases/sizes attributes to permit execution of proc_setup_bars without mss_eff_grouping Change-Id: I798f29be3d49751a23e04bb63e6453f2ab7fb2ae Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32460 Reviewed-by: Camille R. Mann <camille@us.ibm.com> Dev-Ready: Camille R. Mann <camille@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32462 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* sector buffer,pulse mode attributesAnusha Reddy Rangareddygari2016-11-082-0/+34
| | | | | | | | | | | | | | | | | | * p9_sbe_chiplet_reset * p9_sbe_npll_setup Change-Id: I488e9cda493e34f36dc60edccd7bec02582878b1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32106 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32164 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_psi_init -- parametrize link speed (half/full)Joe McGill2016-10-311-0/+18
| | | | | | | | | | | | | | | | | | | Wrapper tested on zzfp033 Appears to correctly trigger half speed mode from FSP tool feedback $ cat /sys/devices/psi_link0/clock FSP-2, PSI(0) CLK overwrite: 1 Speed: 166 MHz Change-Id: I45997c30e71457ceedfcba70550f0e6d98584a1e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31497 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31569 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PPM reg collision (HW389511) work-around: Special Wake-upChristopher Riedl2016-10-261-0/+17
| | | | | | | | | | | | | | | | | | - fixed screwed-up/duplicate commits - addressed code review comments and implemented FAPI_ASSERT conditions for the error case(s) Change-Id: I706b3247f0f9c3ea241ae2841fbce456577c78b6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31379 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31381 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* cache/core/l2_stopclocks updatesYue Du2016-10-263-138/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | patchset 1: skip l2_stopclocks if ex_select is 0 patchset 2: check power state before execute hwp patchset 3: fix syntax typos from patch 2 update patchset 4: add chiplet accessibility check patchset 5: add possible counter to CME PCBMUX patchset 6: add skipping message on check patchset 7: change polling timout method patchset 8: add a missing comma patchset 9: fix ffdc patchset 10:roll back cme pcbmux counter until check to ensure cme accessibility patchset 11:rebased patchset 12:initial checkin of ppe state handling patchset 13:checkin new clk_ctrl_state procedure patchset 14:add attribute xml for new procedure patchset 15:fix calling the p9_common_clk_ctrl_state patchset 16:Matt rebase patchset 17:Warning instead of fail with error on check delete common C file, include only header Change-Id: I14c9480ac0931ac7f8b456f193148ceb3b939947 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28808 Dev-Ready: YUE DU <daviddu@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30365 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.fbc.scan.initfile -- create initfile, add workaround for HW376651Joe McGill2016-10-181-0/+18
| | | | | | | | | | | | | | | | Change-Id: Iaccfdf902d179819549f46ddee65631873fa023e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31309 Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31310 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Adding in system checkstop if anything fails and removing PHB targetsCHRISTINA L. GRAVES2016-10-181-0/+12
| | | | | | | | | | | | | | Change-Id: Iafec57d821b7ef012e9094cc911e4e5aa41d315a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30171 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31277 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* ATTR_SBE_SYS_CONFIG is writeable now, to update it via Psu ChipopRaja Das2016-10-181-0/+1
| | | | | | | | | | | | | | | Change-Id: I91d9c32e10582e0e8773b0dafa0f282f59ac1e9f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31393 Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31396 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_pstate_paramter_block L2 commitSudheendra K Srivathsa2016-10-172-1/+87
| | | | | | | | | | | | | | | Change-Id: I8d3d557ade04c88a77145feeb15d46f45f472e84 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28837 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29013 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add support for ATTR_PROC_FABRIC_PUMP_MODE in sbe attribute xmlSachin Gupta2016-10-151-2/+8
| | | | | | | | | | Change-Id: I097520e4f05091753ce79d6960e6f94ab27162ba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31294 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31296 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Lab: DD1 VCS workaround fixYue Du2016-10-141-0/+5
| | | | | | | | | | | | | | | Change-Id: I4830fb203d34d46cfc2f84b24b38a0645fbf30d5 cmvc-coreq:1008525 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31025 Dev-Ready: YUE DU <daviddu@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31029 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L2 for p9_sbe_check_quiesceCHRISTINA L. GRAVES2016-10-131-0/+199
| | | | | | | | | | | | Change-Id: I23a267f50d6bff3c4099fe3bc90deaff87099250 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28563 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31152 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L2 HWP p9_pm_pfet_controlSumit Kumar2016-10-131-0/+66
| | | | | | | | | | | | Change-Id: I7587f3436d9ef9918f31926cf2788378044fa375 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25610 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31151 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L1 and L2 for p9_l3_flush procedureCHRISTINA L. GRAVES2016-10-131-0/+62
| | | | | | | | | | | | | | Change-Id: I5a16a2e2b564ad86f29e54872235731cec780cdd Original-Change-Id: I6debd1747dffd21a171b5e2e4cbeae90a0ebc9ca Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22703 Tested-by: Jenkins Server Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31150 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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