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path: root/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
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* PM: refine enablement attributes for advanced functions (VDM,RESCLK,WOF,IVRM)Greg Still2017-09-121-2/+18
* Undo some p9 Cumulus spy workarounds in initfilesThi Tran2017-09-121-18/+0
* Cumulus initfile update for OBUS & XBUS PLLsSoma BhanuTej2017-09-121-0/+18
* adjusted mem 2400 nest 1600 workaround and make dd1 onlyShelton Leung2017-09-121-0/+17
* P9 Cumulus InitCompiler supportis - Part 3Thi Tran2017-09-121-4/+5
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2017-09-121-153/+130
* jgr17050500 Added Centaur and DMI IO SCOM initfilesJohn Rell2017-09-121-0/+18
* Update core inits for DD2Nick Klazynski2017-09-121-5/+314
* Updated memory DD1 vs DD2 attributeStephen Glancy2017-09-121-2/+2
* L3 updates -- p9_build_smp, p9_fbc_utilsJoe McGill2017-09-121-0/+18
* Adds DCD calibration control attributesStephen Glancy2017-09-121-0/+17
* Initfile updates for FBC DD2dchowe2017-09-121-0/+18
* p9.int.scan.initfile -- init PSIHB to LSI modeJoe McGill2017-09-121-0/+17
* Update INT DD2 initfilesDavid Kauer2017-09-121-0/+17
* Updates for P9 NX DD2 initfilesChris Hanudel2017-09-121-54/+72
* Add DLL workaround and unit testsAndre Marin2017-09-121-54/+73
* NMMU Nimbus dd2 scom/scan updates, updated commentsEmmanuel Sacristan2017-09-121-0/+82
* Implementing Michael Floyds improvements.Michael Koch2017-09-121-5/+37
* Added DQS alignment workaroundStephen Glancy2017-09-121-0/+19
* p9.xbus.pll.scan.initfile -- restore full frequency settings for Nimbus DD2+Joe McGill2017-09-121-0/+18
* dd2 initsShelton Leung2017-09-121-34/+103
* derate NVLINK frequency for Nimbus DD1Joe McGill2017-09-121-0/+17
* Performance updates for HW409069Luke Murray2017-09-121-0/+25
* Change RD_CTR workaround val and update attr nameJacob Harvey2017-09-121-8/+8
* L3 initfile updatesAlex Taft2017-09-121-17/+18
* Adding HW401552 to cxa initfile to workaround clockgating bugJenny Huynh2017-09-121-0/+17
* Updating HW363605 workaround to be applied to all chipsLuke Murray2017-09-121-17/+0
* Disable cp_me from the L3 for Nimbus DD1 and DD2.0.Luke Murray2017-09-121-0/+17
* INT scan initfile change to add workaround for HW408972Jenny Huynh2017-09-121-0/+18
* p9_setup_bars -- support DD2 NPU SCOM address changesCHRISTINA L. GRAVES2017-09-121-0/+18
* Updating optimal larx/stcx dials for performanceLuke Murray2017-09-121-0/+24
* Added read ctr bad delay workaroundStephen Glancy2017-09-121-0/+17
* HW407123: Slow down xlink command rate for Nimbus DD1/2Jenny Huynh2017-09-121-0/+19
* Update filter pll settings as per HW407180Ben Gass2017-09-121-0/+18
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2017-09-121-0/+18
* Updating L3 LCO watermarks for HW406803Luke Murray2017-09-121-0/+17
* Adding good LCO settings to initfileLuke Murray2017-09-121-0/+41
* update DPLL and IVRM initsJoe McGill2017-09-121-0/+56
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-09-121-0/+33
* disable noise window for DD1 HW406577Shelton Leung2017-09-121-0/+17
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2017-09-121-2/+2
* HW406130: Reduce dma read requests from 16->8 in NX initsJenny Huynh2017-09-121-0/+18
* Add risklevel for HW399624 due to perf penalty; Add HW405851Nick Klazynski2017-09-121-0/+17
* p9_abist: Support for p9ndd2Markus Dobler2017-09-121-0/+17
* Add ec_abst ring to p9n.hw_imageThi Tran2017-09-121-0/+17
* HW405413 : NCU sends data out of orderAlex Taft2017-09-121-0/+17
* Scrubbing needs to stay off for DD2, bug HW405443Juan Medina2017-09-121-1/+2
* PM: GPE timer fix (HW389045 - Update Shadow copy of TSEL)Greg Still2017-09-121-0/+17
* Set NDL IOValids based on configured NV links.Ben Gass2017-09-121-0/+36
* p9_start_cbs updatesAnusha Reddy Rangareddygari2017-09-121-0/+18
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