| Commit message (Collapse) | Author | Age | Files | Lines |
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There is a phase sync signal between the Nest and MC chiplets that is
only needed for combined synchronous LBIST of the inter-chiplet interface,
but can disrupt scanning in async MC operation. So it should be masked in
normal operation by setting the VITL_AL flag in NET_CTRL0.
Change-Id: Ic051943bbb915081b979078d248bf681c7ca5251
CQ: HW422475
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48055
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: LENNARD G. STREAT <lstreat@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48057
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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update the metadata to reflect that HWPs
are product ready (HWP Level: 3)
Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46791
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_sbe_chiplet_reset
p9c_mc_scom
resolve HW CQ 418671
set MC CPLT_CONF1 FASTX2 ratio controls in p9_sbe_chiplet_reset
need to set prior to MC chiplet clock start for proper functional operation
remove from initfile
p9_cen_framelock
resolve HW CQ 418901
analyze captured FRTL value along with FRTL counter overflow error FIR
centaur.mcs.scan.initfile
cen_scominits
enable MBI trace array prior to framelock, to make usable for future debug
Update p9c.mc.initfile to include fix for ZCAL to help with conflicts - bgass
Change-Id: I7897d41250b9c113adf22fe40a8ca5971bca2a6f
CQ: HW418671
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44708
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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The hang pulse setting of 68s is not supported by the PCB slave,
and NX can deal with a 34s hang pulse too, so revert back to 34s.
We could change the chiplet's base divider and adapt all other hang
pulse settings, but that would be a huge code ripup as it breaks
uniformity among chiplets.
Change-Id: I17ae92e58d713d54256083f43eabd9ce4be7167f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39795
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39797
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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reduce X states to improve LBIST stability
Change-Id: I5f62f19e88a3701f2677ec43e0994aed7854a3ec
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37121
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: Joseph E. Dery <dery@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37131
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I42a8ed1c11ca995a3368c60af63afc8c9e46ed41
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36913
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36916
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Icdd7460d8e3213f9bbd3d52e7825242bc59fc9e9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29825
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I726951318cdb19fd445af2f7910e0d6872eff18c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29086
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
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