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* Account for OMI technology in initial mcs setup for AxoneChristian Geddes2019-08-061-17/+65
| | | | | | | | | | | | | | | | | | | The scom registers that setup the memory channel's intial state get written during the SBE steps. The hwp that does this needs to be updated to account for the changes to the MCFGP0 register that happened between P9N/P9C and P9A. Change-Id: Icfa50177f9fefca3acabbbc41b60f65d280348e7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81458 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81482 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Move to long term CLSCOM workaroundAdam Hale2019-08-061-2/+1
| | | | | | | | | | | | | | | | Change-Id: I33ff7d349b63c54794bf6acf806c89d22e5d9ac0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81474 Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: Devon A Baughen <devon.baughen1@ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81486 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* temporary mc inits to enable wider teamAdam Hale2019-07-171-2/+3
| | | | | | | | | | | | | | | Change-Id: Ic9adb821799b3383b90b8e9feb86815c9b28f7f2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79669 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Devon A. Baughen <devon.baughen1@ibm.com> Reviewed-by: BRIANA E. FOXWORTH <befoxwor@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79874 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Update p9_l2_flush to check if purge is busy on anything prior to flush.Ben Gass2019-03-222-5/+89
| | | | | | | | | | | | | | | | | | | | | | | | | The previous check was only checking once if CMD_REG_BUSY is off. This will now check if CMD_PRGSM_BUSY is off, indicating the Purge engine is not busy with any requests at all. It will also poll on busy prior to issuing the flush. If PURGE_CMD_ERR is on prior to starting flush a warning will be printed via FAPI_DBG. PURGE_CMD_ERR will be cleared prior to issuing the purge. Change-Id: I120cc9a00d26da8cf2ca4ec6dd7d8f3006633b61 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72562 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: MURULIDHAR NATARAJU <murulidhar@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72582 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Implement PBA Cache-Inhibited 8B Rd/Wr AccessChristopher M Riedl2019-02-124-31/+68
| | | | | | | | | | | | | | | | | | | | | The PBA supports 8B cache-inhibited rd/wr operations via the OCB indirect-OCI access path. Also implemented necessary changes in the wrapper to support the PBA cache-inhibited operations. Turns out that the ADU cache-inhibited ops are broken in the wrapper so I undocumented them in the wrapper's usage/help string. Change-Id: Ic6f3d358a548a1750a779a7f17b223a275983419 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71166 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71180 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "Clear INT_CQ related firs after completing sync_reset in MPIPL"Christian R. Geddes2018-11-012-51/+0
| | | | | | | | | | | | | This reverts commit 9b1a1383bb554e9810f45717c3f44782c79411f3. Change-Id: I31b958d11dc1bbe058712e48831baa5945823af9 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68201 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68203 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Clear INT_CQ related firs after completing sync_reset in MPIPLChristian Geddes2018-11-012-0/+51
| | | | | | | | | | | | | | | | | | | | | | In the SBE steps of the MPIPL, the SBE calls a HWP called p9_sbe_check_quiesce. This function ensures that traffic on the powerbus is stopped prior to cycling the master core on and off. During this HWP a sync_reset is performed on the INT component. After this reset we have been told to clear out all of the related' INT_CQ firs. This commit adds in a new function which is called immediatly after sync reset and will clear all relevent scoms. Change-Id: Ia99a2f2d3f855823472f81b32baf44d25d7c4cad CQ:SW448121 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68020 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68023 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SMF: clear HRMOR[15] in all modes so that secure mode won't hang coreGreg Still2018-10-051-5/+7
| | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I26a98dfce1eb8123c79b35f2f4dc1783e16e411e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66687 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66693 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* RAS_XML: updates to sync the XML with actual values from hardwareZane Shelley2018-09-171-1/+1
| | | | | | | | | | | | | | | | Change-Id: I590d6790cd391ff4be984001acd41c6a1ba48a06 CQ: SW445620 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63398 Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63841 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Use core target for HRMOR/URMOR scoms in p9_sbe_load_bootloaderDean Sanner2018-08-291-2/+2
| | | | | | | | | | | | | | | -Code was using EX target, which only results in core 0 working Change-Id: I2106a836f9ab73b32a37665758fbc6f8ab3a888c Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64403 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64404 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SMF: SBE updates for SMF (URMOR set and CPMMR[Runtime Wakeup Mode] clear)Greg Still2018-08-291-7/+27
| | | | | | | | | | | | | | | | | | - set URMOR if MSR[S] bit is set in p9_sbe_load_bootloader - clear CPMMR[Runtime Wakeup Mode] in all cores in p9_sbe_select_ex to ensure Hostboot starts from known state Change-Id: I572a1d9e0ebf8e194c811e2b8c176d145b7361e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61812 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61817 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- set XSCOM BAR in secure memory with SMF enabledJoe McGill2018-07-183-0/+30
| | | | | | | | | | | | | | | Change-Id: I7e3b39bb75ad8ee3983f4b4352d08369fe6bfc5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62065 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62074 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Secure memory allocation and setupJenny Huynh2018-07-123-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_mss_eff_grouping.C: - determines whether secure mem is requested, reserves smf space - always reserve smf at end of range because of end-of-range bit - set addr15 when reporting smf base address - mask off group_id(0) via chip address extension if smf is enabled - updated to set value of attr_smf_enabled - enhanced error reporting with smf config/supported values - made values reported to attr_mss_mcs_group_32 more clear p9_mss_setup_bars.C: - set MCFGPA/MCFGPMA registers with SMF data - fixed scom registers for MCFGPA/MCFGPMA hole setup - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711 - added assert to check for HOLE1 and SMF enable overlaps p9_query_mssinfo.C: - updated to print out SMF reservations - print out HTM/OCC/SMF reservations regardless of mirroring enable p9_fbc_utils.C: - prevent group_id(0)=1 from affecting mappable memory ranges p9_sbe_fabricinit.C: - mask off group_id(0) via chip address extension if smf is enabled p9_setup_sbe_config.C, p9_sbe_attr_setup.C: - use scratch_reg6 bit(16) to pass smf_config value initfiles: - removed setup to use other addr bits as secure bit; core only uses addr15 - added setup for ncu addr15 value in hcode - always set addr15 config bit in bridge unit if smf is supported - set addr15 bit across all mcs if smf is enabled - added in settings to enable smf in nmmu unit - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported attributes: - ATTR_SMF_ENABLE is a system level attribute - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported) CQ:HW451708 CQ:HW451711 Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_check_quiesce -- restore call to p9_int_scrub_cachesJoe McGill2018-07-122-0/+50
| | | | | | | | | | | | | | | | | | | | | | 52512 removed code related to the DD1 SW based INT reset sequence, to leave only the HW based reset in production code for DD2 and beyond. It also erroneously removed the call to/code for p9_int_scrub_caches. This commit restores the subroutine, and invokes it prior to the HW quiesce/sync reset into order to scrub/flush the EQC, VPC, IVC, and SBC caches. Change-Id: I051117e3a18c55aea7267e53eea1652f0cff9790 CQ: SW431898 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62227 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62243 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3: Set up oscillator error mask based on MF osc settingJoachim Fenkes2018-07-041-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | On Cumulus, set up the oscerr mask (0102001A) such that errors on unused MF/PCI oscillators are masked (based on the setup in RC3), making sure the corresponding FIR bit (TP LFIR bit 37) will not report false positives. Keep the mask constant for Nimbus as only MF oscillator 0 is in use there. This reverts most of commit ce194c5cd773bdabd093b3aa44c2b3d3bcfb58e5 because a correct mask setting here obviates the need for selective FIR masking. Change-Id: Ib49704fb50fc1e62168cc4cd06841d068c488914 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61365 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61370 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* correctly propogate bad return code from p9_adu_coherent_status_checkJoe McGill2018-06-182-9/+17
| | | | | | | | | | | | | | | | | | | p9_adu_access.C p9_adu_setup.C save current_err to local return code object at start of exit path, and return the saved value at exit (prior code was clobbering current_err by call to cleanup routines) Change-Id: I2f247ba2e93c673b3581e3ebe1504d4f05cb3a24 CQ: SW434090 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60607 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60618 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- unmask TP LFIR 37 only when MF oscswitch redundancy enabledJoe McGill2018-06-181-3/+12
| | | | | | | | | | | | | | Change-Id: Ib2614f887a3da7801db9d8680520e21daef90fba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60435 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60443 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* shift OBUS FIR programming inits for secure bootJoe McGill2018-06-172-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_scominit: unmask all OBUS EXTFIR bits, use PB CENT FIR 14 to mark update for downstream code (qualify XBUS/OBUS EXTFIR updates to apply to PPE platform only) p9_fab_iovalid: conditionally unmask OBUS EXTFIR based on state of PB CENT FIR 14 (will handle unmasking here when insecure -- Cronus or old SBE images) p9_obus_extfir_setup: new HWP for HB to call, mask OBUS EXTFIR bits for unused busses Change-Id: I07e7da4a7c61c041451ff4ddfeec3c266385d404 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60358 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60361
* p9_sbe_scominit -- unmask TP LFIR bit 37 for CumulusJoe McGill2018-06-081-0/+16
| | | | | | | | | | | | | | | Change-Id: Id216f65d5c240d88c4db62e374c9f3278d623fbb CQ: SW432374 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60118 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60125 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert changes to EFF_FBC_GRP_CHIP_IDS modespashabk-in2018-04-202-7/+5
| | | | | | | | | | | | | | | | Change-Id: I4907eea62c2fa85bdf9ed193d1820fba84afc82f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57530 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57534 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Consume PROC_MEM_TO_USE for alt memory configspashabk-in2018-04-164-26/+25
| | | | | | | | | | | | | | | Change-Id: Ideb3c3d2bbdbce8b773d51b86d9f97f2e654ca56 RTC:189091 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56197 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56203
* move xlink psave configuration to SBEJoe McGill2018-04-031-1/+29
| | | | | | | | | | | | | | | | | | | | | | | 55058 added inits to prime the PPE for xlink psave the register touched is in the blacklist, so it can't be touched on slave chips via FSI in the ioe tl SCOM initifle -- this was triggering HW CI failures this commit simply shifts the register setup into the SBE, where it can be performed securely Change-Id: I57504ccfe4c5f7e71397d11c7468da42ec09f059 CQ: SW421691 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56252 Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56256 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Pass SBE Security Backdoor Bit to HB BootloaderIlya Smirnov2018-04-022-4/+6
| | | | | | | | | | | | | | | | | | | | Add a "SBE security backdoor" bit to reflect the state of the SBE security backdoor; the bit is passed to the hostboot bootloader from SBE. The new bit is the inverse of the ATTR_SECURITY_MODE attribute. Also bump the version of SBE/bootloader to reflect the change. Change-Id: Idf3009447c51c66306c043daf7f8189b8cbf2f36 RTC:188961 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56309 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56318
* FIR + RAS XML updatesJoe McGill2018-02-151-2/+2
| | | | | | | | | | | | | | | | | | | p9_sbe_scominit.C mask PBCENT FIR bit 5, rely on action of unit master specific FIR bits to drive attention generation on any cresp address error condition Change-Id: I3c23aeecd426687fe91d37aadfd5ca6243c4a4b3 CQ: SW417475 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54067 Reviewed-by: Daniel J. Henderson <hende@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* enforce strict 512 GB per socket limit on Witherspoon memory map (part2)Joe McGill2018-02-122-3/+6
| | | | | | | | | | | | | | | | | | | | | | | first commit merged before HW testing was complete, and caused issue with skiboot's detection of the MCD workaround mechanism this update restores the chip address extension HW programming to 0x7, (to avoid a coreq skiboot change) but should still restrict the allocation to lie within the first 512 GB of address space on each socket Change-Id: Ie844a609c16ffa1aa38091bae42145da9c7912a4 CQ: SW415901 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53594 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53642 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* enforce strict 512 GB per socket limit on Witherspoon memory mapJoe McGill2018-02-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SW415901 exposed a problem with the current implementation of extended addressing for Witherspoon Coral systems. With fully configured memory present in the system (8x64GB=512GB per socket), GARDing a DIMM will currently result in: - group of 6 fullying occupying 0-512GB address space - group of 1 mapped at 8TB region (2nd extended addressing region) The single group mapping has RA bit 20 active, which is problematic for the NVIDIA device driver. p9_fbc_utils.H p9.trace.scan.initfile for HW423589 option 2, enable chip address extension for chip ID LSB RA bit 21 only. This creates only one 4TB extended addressing region per socket. indirectly, this limits DIMMs to map into the 512 GB region with RA bit 21=0 and should cause an IPL failure if more than 512 GB is plugged or the memory grouping algorithm attempts to spill beyond 512 GB on a given chip p9_mss_eff_grouping.C prohibit formation of group sizes 6 and 3 when HW423589 option2 WA is active Change-Id: I997c080a2821cf3c556a4f8b35d5e0fdb34da500 CQ: SW415901 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53406 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53411 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* cresp address error handling updatesJoe McGill2018-02-011-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit sets up the FBC trace arrays to stop on a combined response address error, for MPIPL FFDC collection. It also adjusts the FIR configuration for several units, to trigger a system checkstop (based on their own LFIR) if they master a command which recieves a combined response address error cresp, and we do not support MPIPL from that condition. Unlike in past projects, the FBC level cresp address error FIR bit cannot be set to checkstop (in order to support MPIPL scenarios where the unacknowledged access eminates from the core) FIR action bits modified: PSIHB bits 15:20 PBA bit 1 Change-Id: Ie569600c2c937644740636e8a33097f7979d8d6f CQ: SW411054 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52604 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52634 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_build_smp -- use ADU chipops to switch fabric configuration part #2Joe McGill2018-01-301-1/+4
| | | | | | | | | | | | | | | | | | | | p9_build_smp HWP code is modified to invoke new p9_putmemproc FAPI HWP via FAPI_CALL_SUBROUTINE HB platform must invoke SBE chipop under the covers for security Cronus may directly invoke p9_putmemproc body in an insecure system Change-Id: I34b90ce906e8caaf3ce86e728228f634ce136d33 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49692 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49694 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* shift XBUS FIR programming inits for secure bootJoe McGill2018-01-261-1/+127
| | | | | | | | | | | | | | | | | | | | | | general approach: - enable runtime FIR settings in SBE code, for all present XBUS regions - remove FIR initialization from HB code which runs prior to SMP build - update HB HWPs to re-mask XBUSes which are present but not functionally used CQ: SW409902 CQ: SW409903 CQ: SW409905 Change-Id: I378ed2ca39c0d5be894420bfc3257e41e3e95de5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50519 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50528 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Remove workaround for DD1 SW reset for XIVESachin Gupta2018-01-262-270/+22
| | | | | | | | | | | | | | | | Change-Id: Ic2cf3510350aa00c0641cc910824000bf58d8276 RTC: 177741 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52512 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52515 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_xbus_fir_utils.H -- create header for definition of XBUS related FIR settingsJoe McGill2018-01-251-0/+97
| | | | | | | | | | | | independent commit to create pre-req for 50519 Change-Id: I69a4c497c2def46f396d1c37594b26c9bea263d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52390 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52580 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* fix ADU setup for MCD disabled operationJoe McGill2018-01-131-2/+2
| | | | | | | | | | | | | | Change-Id: I0068d797ad4a82216e440f701c5182ad95584a15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51503 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51504 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_build_smp -- use ADU chipops to switch fabric configuration part #1Thi Tran2018-01-134-21/+124
| | | | | | | | | | | | | | | | | | This commit is the first part of 49692, which is splitted in order to have SBE platform proceed with code supports. Change-Id: I1f491cac6cfef8476487217067d69d4551de1228 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51048 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51049 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* MCD disable workaround for HW423589 (option1)Joe McGill2018-01-121-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need MCD disable for HW423589 (applied to Nimbus EC20 and 22+) p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scan.initfile p9.l3.scan.initfile p9.mmu.scom.initfile p9.ncu.scan.initfile p9.npu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_pcie_config.C set unit scope disable dials p9_sbe_scominit.C p9_pm_pba_init.C set PBA unit scope disable dial p9_pm_set_homer_bar.C change PBA0 default command scope from GROUP to NODAL p9.fbc.ab_hp.scom.initfile disable group master setup p9_setup_bars.C p9_setup_bars_defs.H skip MCD setup for HW423589_OPTION1 cmvc-prereq: 1043014 Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_mss_eff_grouping -- fix mirrored memory mapping bug introduced by 49290Joe McGill2017-12-041-2/+7
| | | | | | | | | | | | | | | | | | | | | | | p9_fbc_utils.C return each mirorred region as two chunks, to make m.size = nm0.size + nm1.size for Cumulus p9_mss_eff_grouping.C fix off by one error in max region index calculation Change-Id: I79ac3651de048ed83a0eff704b49b25bff9a84cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50393 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: JEREMY R. NEATON <jrneaton@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50397 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Chip address extension workaround for HW423589 (option2), part1Joe McGill2017-12-016-23/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml nest_attributes.xml p9_sbe_attributes.xml add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines set of chips which physically support the feature add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips which need extended address workaround for MCD issue (applied only to Nimbus EC 21) add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of memory groups formed. Written by p9_mss_eff_grouping. For HW423589_OPTION2, this will default to 512GB add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold extended address configuration. Written by p9_sbe_fabricinit (SBE) and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will default to 0b0000_111, consuming all chip ID bits for extended addressing. p9_fbc_utils.C p9_fbc_utils.H extend p9_fbc_utils_get_chip_base_address to support address extension, now outputs set of ranges in each msel based on ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID maintain original function for PPE platform which requires knowledge of non-aliased base addresses only, for code size p9_mss_eff_grouping.C p9_mss_eff_grouping_errors.xml set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform restrict size of groups formed for HW423589_OPTION2 p9_sbe_fabricinit.C set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform configure FBC/NMMU extended addressing registers p9_setup_bars.C p9_setup_bars_defs.H p9_setup_bars_errors.xml add general purpose support for extended address mode for HW423589_OPTION2, configure static MCD setup p9_hcode_image_defines.H p9_hcode_image_build.C customize SGPE image with address extension configuration to apply p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scom.initfile p9.l3.scom.initfile p9.ncu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_hcd_cache_scominit.C p9_hcd_cache_scominit.c p9_pcie_config.C set unit address extension configuration on supported chips p9_rng_init_phase2.C p9_sbe_scominit.C p9c_set_inband_addr.C p9_sbe_load_bootloader.C p9_sbe_mcs_setup.C adapt to alterations in p9_fbc_utils_get_chip_base_address Change-Id: I614d566c073f1169f04f647057e6e85889f1c237 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48892 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_check_quiesce -- dont attempt PHB DMA quiesce if ETU is already in resetJoe McGill2017-10-271-16/+20
| | | | | | | | | | | | | | | Change-Id: I32c2e2f1d2f4793a8ae42561a74d9ff3abdfa897 CQ: SW403955 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48805 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Ricardo Mata <ricmata@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48811 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Need to clear OCB3 errors before a PBA operationThi Tran2017-10-261-2/+5
| | | | | | | | | | | | | | | Change-Id: Iaa7246b82bc490222162ef74011db78bc8631e23 CQ:SW405593 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48647 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48649 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Share common code between p9_l2_flush and p9_l2err_linedeleteThi Tran2017-10-112-122/+154
| | | | | | | | | | | | | | | | | Change-Id: I547078b1e0fc7adec767402faf5e64e4b4390bc9 RTC: 178071 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46359 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46385 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* update HWP level metadata for nest, common filesJoe McGill2017-10-022-59/+64
| | | | | | | | | | | | | | | | Change-Id: I451695b8ae1d8f7d5ed6d512631992dea98b5ee8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46967 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46969 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Prime PSSCR reg on thread 1 so istep 16 works in SMT1Dean Sanner2017-09-191-0/+5
| | | | | | | | | | | | | | | | | | | - PSSCR reg comes up to invalid default. Normally STOP cycle sets to valid value, but for the master core (prior to istep 16) it is done via SBE. Thread 2/3 already had this set, but missed thread 1 for SMT1 mode Change-Id: I8358dfa3db863291d72e860c0c0475541af93bf4 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46293 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46300 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* p9_pba_coherent_utils -- remove unsafe buffer checksJoe McGill2017-09-084-78/+7
| | | | | | | | | | | | | | | Change-Id: I66696a70446bb5e7af80e46b637f445def2ac03a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45746 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45754 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* L3 update - p9_sbe_check_quiesceThi Tran2017-09-052-254/+396
| | | | | | | | | | | | | Change-Id: I12ecd934b8d99782dc947237aee4f1d42809e4e0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44496 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44506
* p9_sbe_scominit -- unmask PB EAST FIR 31 for hypervisor TIJoe McGill2017-08-251-1/+1
| | | | | | | | | | | | | | Change-Id: I584450ac1d6190c141db29a8f37d40c05f440c04 CQ: SW396917 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45058 Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45064 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support the PIB abort condition on PPE platformCHRISTINA L. GRAVES2017-08-231-32/+45
| | | | | | | | | | | | | Change-Id: I062f25ab8855faee1024eaa49d2ba40d89976316 CQ: SW386342 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38119 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38121 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Optimize p9_adu_coherent_utilsspashabk-in2017-08-211-37/+28
| | | | | | | | | | | | | | | | | Saving of 236bytes on PPE Change-Id: I70add589c31f6d076a3449abee8a5d04d4129b70 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44462 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44464 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix bug in npu quiesce sequencecrgeddes2017-08-181-57/+49
| | | | | | | | | | | | | | | | | | | | | | | There were a couple issues w/ the sequence of steps we were doing in order to quiesce the npu. The first problem was that we were doing an indirect scom incorrectly and instead of the actual value we were getting all 1's back. After fixing that we realized that the NTLs were not making it to the reset state, this was because the brick was never enabled by PHYP. A check was added to not attempt to put NTLs in reset state(step 1) if brick isnt enabled CQ: SW397252 Change-Id: I94899c73438d8bbdaf777f8aab5640992ae74db6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44707 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: James F. Mikos <mikos@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44710 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Use PHB target in p9_phb_check_quiesceSachin Gupta2017-08-141-74/+15
| | | | | | | | | | | | | Change-Id: I94fd7cc0cbf13a59afeb2516eb30efce2277ff76 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44450 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44453 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update p9_sbe_load_bootloader Hwp to receive the addr-key stash-2Raja Das2017-08-112-1/+35
| | | | | | | | | | | | | | | | Change-Id: Id27b43085d1619bc9cfbe854dc46eac6ee85e170 RTC:166124 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35883 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35889 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* L3 update -- p9_sbe_load_bootloaderJoe McGill2017-08-073-359/+558
| | | | | | | | | | | | | | | Change-Id: Ia0cb15dc2f6d8dfcfc8e9696a2878fce6a01ccbb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42673 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42677 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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