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* Backing build updateSachin Gupta2017-12-201-1/+1
| | | | | | | Change-Id: I25e8e1916282060b6343209e8be77e3cb63dbb05 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51226 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* gitRelease: Check master branch if query on rel branch failsSumit Kumar2017-12-201-0/+7
| | | | | | | | Change-Id: I1f39c95d11b9a2a0b03a7303d2024f63e295f43a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51174 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Reset MPIPL flagSachin Gupta2017-12-201-0/+9
| | | | | | | | | | | | Reset MPIPL flags if enter or continue mpipl fails Also reset the flag if contoniue mpipl pass Change-Id: I71d6ab7035431dfe3061d67108e43ca262601917 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50815 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* disable ECC bypass for Cumulus DD1.0Joe McGill2017-12-193-3/+28
| | | | | | | | | | | | | | | | | | | | | Nimbus DD2.0 disable will go into op910 only (for Boston Coral) but not into master Change-Id: I28376316be3e6700af97df83a02c48e46d715dec CQ: HW415945 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50445 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50453 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Increase cache data timeout valuesLuke C. Murray2017-12-153-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | The PCIe timeout have increased to 66-100ms, so we need to double the NCU master timeouts to be above these timeouts. This has a chain effect causing the L2/L3 master timeouts to increase which causes the tlbie snooper to increase which causes the tlbie master to increase. This would also ususally cause the core timeout to increas, but the core is already at around 13 seconds, so there is headroom there. Change-Id: I5930076151267a9bfa66e24edef0985c165db0b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50582 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50602 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP/PState: SGPE/PGPE Error Handling SupportYue Du2017-12-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon PGPE Halt 1) SGPE performs STOP Recovery Trigger to set a malfunction alert and removes PGPE IPCs from wake-up decisions. 2) CME is interrupted by QPPM OCC Heartbeat Lost that PGPE stopped updating Upon SGPE Halt 1) PGPE moves to Psafe 2) PGPE performs STOP Recovery Trigger to set a malfunction alert. This commit also includes SGPE Panic Code Cleanup such as debug halt support. However PGPE Panic Code Cleanup is dealt in a different commit Key_Cronus_Test=PM_REGRESS Change-Id: I893aa1ef21d2f684722b8c10dbbeb92b9505c1c4 CQ: SW410252 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49275 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49429 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PPE: Adjust the maximum decrementer countDoug Gilbert2017-12-151-2/+5
| | | | | | | | | | | | | | | | Change-Id: I4f59cabf7439590ac736e6f64e35acf11e6c5aa9 CQ: SW402715 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46944 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46950 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Expand PGPE optrace to Main Mem - No fnctl coreq rqmt image build vs hcodeAdam Hale2017-12-151-2/+1
| | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I823b350ffe1e07108fbadd4b0456c7188839932f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46480 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48106 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove writable property from ATTR_LINK_TRAINChristian Geddes2017-12-151-1/+0
| | | | | | | | | | | | | | | | | | This attribute was both platInit and writable, that should not be the case. After talking w/ HW guys Change-Id: I9d12581cf2772715693e8b0a8dc539aeff87cc85 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50908 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50912 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Security: add AVSBus bridge registers to whitelistGreg Still2017-12-151-0/+24
| | | | | | | | | | | | | | | | | | | | - In order to set VDN voltages across the Master->Slave FSI links from Hostboot prior to XBus training, the AVSBus bridge registers have to be accessible through the SBE. - While the present code uses only the AVSBus O2S "B" bridge, both A and B bridge addresses are added so as to not be limiting in the future. The bridges are identical and are present to allow for Firmware separation. Change-Id: Ib702c2e49a2533deb4b2898cd533faab349ddf5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50657 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50662 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Removing P9_XIP_ITEM_NOT_FOUND trace out msg from p9_xip_image.CClaus Michael Olsen2017-12-151-2/+2
| | | | | | | | | | | | | | | | Change-Id: I72d3649a173fecee990c7ec1793568675be6c53d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50831 Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50837 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Chip-op filteringspashabk-in2017-12-145-25/+64
| | | | | | | | | | | Implement chip-op filtering in secure mode Change-Id: Ia7d18de28b387615e5c61bc9693229c168f2d418 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50128 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "Adding p9a support."Jennifer A. Stofer2017-12-145-180/+34
| | | | | | | | | | | | | | This reverts commit 41352b2d444e98639eedc06b1eb0d8da89d4adb3. Change-Id: Ic3f2099eff3f5c942ef8fb6916e8ee78ca1a9e82 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50703 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50722 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove writeable tag from ATTR_PROC_FABRIC_GROUP_IDSantosh Puranik2017-12-141-4/+0
| | | | | | | | | | | | | | | Change-Id: I94211977e9eca2d26a929d59fb4d582cbcfefb61 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50746 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50750 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Enable FFDC Collection for SBE Deadman TimeoutAmit Tendolkar2017-12-147-93/+209
| | | | | | | | | | | | | | Collects SBE Async FFDC calling p9_collect_deadman_ffdc via the Get SBE FFDC chip-op, based on SBE State of the DMT failure. Misc. changes in the SBE DMT flow. Change-Id: Ie7a0347034cf447613bc206ec6fcfd13b5bc530e RTC: 179364 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49473 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add Fallback Frequency for #V Bucket SelectionDan Crowell2017-12-121-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | Created ATTR_FREQ_PB_MHZ_POUNDV_FALLBACK to handle a few cases where modules were created with invalid #V for the frequency we would like to run them at. The code will use the real powerbus frequency to find the #V bucket (no change from current behavior) but will fall back to the new attribute if no matches are found. Change-Id: Ie15190ac092ca797a8a51d41eece7c4cd2d0f136 CQ: SW410357 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50677 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50682 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* support customized application of filter PLL buckets from AW MVPD keywordJoe McGill2017-12-126-20/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pervasive_attributes.xml sbe_attributes.xml create ATTR_FILTER_PLL_BUCKET to encapsulate BGoffset selection p9.filter.pll.overlay.scan.initfile generate correct BGoffset value based on ATTR_FILTER_PLL_BUCKET value build must process 4x (ATTR values 1..4) to generate set of ring images p9_xip_customize.C consume AW keyword from MVPD, set ATTR_FILTER_PLL_BUCKET for HB platform and customize into SBE image if attribute is present in image p9_sbe_npll_initf.C p9_sbe_npll_initf_errors.xml re-scan perv_pll_bndy ring with selected BGoffset overlay when ATTR_fILTER_PLL_BUCKET is non-zero p9_sbe_chiplet_pll_initf.C p9_sbe_chiplet_pll_initf_errors.xml adapt to error XML updates in p9_sbe_npll_initf Change-Id: Id09074d12e95ffc44337e32ec683056d8ec390f3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49442 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49460 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lock"Sachin Gupta2017-12-122-95/+3
| | | | | | | | | | | | | | | | This reverts commit 702e418be9ace793c323710411c2ca6b4d032c58. Change-Id: Iebbea4e980a974a10a46345262bd475e3e340771 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50800 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50802 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lockJoachim Fenkes2017-12-113-4/+98
| | | | | | | | | | | | | | | | | | | | | | | | | As it is no longer a requirement that Spread Spectrum is enabled on all SS PLLs in a system in unison, we're better off turning on spreading as early as possible, so any link training runs off of a spread clock. The only way to enable Spread Spectrum in P9 is via the TOD Timer, so we have to set up a timer compare value of 1 and force the TOD value to 1 so that the timer is hit and the TOD's spread enable output turns on. Change-Id: I0bcd33f17ef06beafb44ba6777d32b98d0680deb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49662 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49667 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enhance SBE Deadman FFDC Format and sequencingAmit Tendolkar2017-12-115-70/+86
| | | | | | | | | | | | | | | | | | | | | | | | | 1. align data per FFDC member names 2. set the atomic lock FFDC so that errl parser works 3. collect sibling core data if in fused mode 4. do not collect ffdc on check_master_stop15 fails, as SBE will do that upon a chip-op request See https://ralgit01.raleigh.ibm.com/gerrit1/#/c/49473 for FW changes Change-Id: I9880cdd3480c84c418b662fb7174291ed7b68cdd RTC: 179364 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50648 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50653 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PGPE: STOP11+WOF+SafeMode FixesRahul Batra2017-12-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | -STOP11+WOF Fix -STOP11+WOF+Safe Mode Key_Cronus_Test=PM_REGRESS Change-Id: I7aae651213174049fa4fe89d6ac92fda2478e90a CQ: SW410652 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48989 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49320 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding p9a support.Ben Gass2017-12-095-34/+180
| | | | | | | | | | | | | | | | | | | Adding CTEPERLPATH to ENV-setup Jenkins failure CQ SW40996 Change-Id: I02a9c5f31fb0545e8f8c8cd99b528a467ae52cf8 CQ: SW409966 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45266 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50688 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enabling L2 64B store predictionLuke C. Murray2017-12-091-0/+17
| | | | | | | | | | | | | | | | | | Turning on the 64B store prediction inside the L2. This is a performance fix. Change-Id: I2e91747e2cf420ffa50efeb73b8876e54c89b8d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50531 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50542 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.npu.scom.initfile -- fix cq_sm allocation issue at low water markRyan Black2017-12-091-0/+24
| | | | | | | | | | | | | | | | Change-Id: Ibf7f3276279e99e82841d2a209230ce38081c419 CQ: HW426816 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50480 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50607 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Nimbus DD2.2 core chickenswitchesNick Klazynski2017-12-091-1/+136
| | | | | | | | | | | | | | | Change-Id: I209bf1735b7107303bbd9009d7c99201809ba8bf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50315 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50337 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Increase suspend_powman timeouts from 10 micro sec -> 10 milli secChristian Geddes2017-12-091-6/+9
| | | | | | | | | | | | | | | | | | Our timeouts for suspend_powman were way to short. This commit increases the timeouts by a factor of 1000. Per request from M. Floyd on PM team. Change-Id: I03c6e452a453979128d232c33d31ff9fd9dfbe6b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50470 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50474 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Override filter ring support for perv_pll_bndy_bucket rings.Claus Michael Olsen2017-12-094-4/+27
| | | | | | | | | | | | | | | | Change-Id: If1d4649da6da3c0d9e09ef4169d4181a1dc43bde Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49438 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49450 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cache/Core stop clocks: add shut down of Power Management to remove contentionsAmit Tendolkar2017-12-078-50/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ported changes from https://ralgit01.raleigh.ibm.com/gerrit1/#/c/44781/25 to simplify auto mirror conflicts and reuse existing SBE HWP files - Halt SGPE, PGPE and CMEs assocatiated within the targeted EQ - Clear the PCB atomic lock that may be in place by SGPE - Add core stopclocks changes - Fixed cache stop clocks XML callout - Fix atomic lock library dependencies - Only enable function on DD2 - Halt PPE only if not already in halt - Enhance PPE Halt FFDC Key_Cronus_Test=PM_REGRESS Change-Id: Id6c11176d222213bf1a01b91cade41de989f04c6 RTC: 180317 CQ: SW406569 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50415 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50420 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP Recovery: Only XIR collection in HWP error path during PM Reset.Prem Shanker Jha2017-12-071-0/+14
| | | | | | | | | | | | | | | | | CQ: SW406487 Change-Id: I97a0309261c4d3f257ade2b70d952be253dc8f65 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47124 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47128 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updated PSI and TOD regs into whitelistSrikantha Meesala2017-12-071-0/+7
| | | | | | | | | | | | | Change-Id: I5b8afde659b1c9f7c4f527791efaafb88e03380b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50482 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50487 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Error out on non-TOR ring section detection.Claus Michael Olsen2017-12-061-7/+4
| | | | | | | | | | | | | Updating ring section parsing code to error out if it detects that there is no valid TOR magic header word in the beginning of the ring section. Change-Id: If92278a16de3e4f5c1605161606ed8621e30f56e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49883 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding attribute to turn memory early data onLuke C. Murray2017-12-054-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Performance wants a way to turn memory early data on & off using just scoms. Adding one attribute to control all the needed scoms and defaulting everything so that early data is off. For the L3 disable cp_me by default using scom Changing the scom cp_me dial to disable cp_me for all systems after Nimbus DD2.0. This is expected to be the correct setup for most systems. We didn't disable the cp_me at the scan, because the scom can only disable cp_me if ON or allow the scan setting if set OFF. Some systems might want cp_me enabled by only changing a scom. So the default is to set cp_me on at the scan and off a the scom. This way only the scom has to be turned off to enable cp_me. Also update three scoms in the memory controler that are needed for early data. Change-Id: Ib2106ec4b7d26cb084601f2d6eee68833b36d30b CQ: HW426419 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49261 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49331 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Code restruct: TOR APIClaus Michael Olsen2017-12-0413-1590/+718
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key_Cronus_Test=XIP_REGRESS Code restructuring aiming at: - utilizing TOR magic header info - enforce a common approach for - extracting metadata for all image,chipType combinations - traversing images for all image,chipType combinations - shrinking code size by reusing common code segments - improve readability by - separating more clearly metadata extraction and image traversal - slight rearrange of certain code segments - remove leftover hardcoded assumptions about ring/TOR data and structs - variables appropriately renamed and now all using camel style Change-Id: I50ace8b2fdb340a97ce6d74ce545c5e1acd21c40 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38863 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: GIRISANKAR PAULRAJ <gpaulraj@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43250 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_pstate_parameter_block: support removal of VFRT VdnPrasad Bg Ranganath2017-12-041-1/+1
| | | | | | | | | | | | | | | | | RTC:179507 Change-Id: Ide07bc963d2b88fa8d95c2f2776a84316d6dac48 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49697 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49977 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_mss_eff_grouping -- fix mirrored memory mapping bug introduced by 49290Joe McGill2017-12-041-2/+7
| | | | | | | | | | | | | | | | | | | | | | | p9_fbc_utils.C return each mirorred region as two chunks, to make m.size = nm0.size + nm1.size for Cumulus p9_mss_eff_grouping.C fix off by one error in max region index calculation Change-Id: I79ac3651de048ed83a0eff704b49b25bff9a84cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50393 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: JEREMY R. NEATON <jrneaton@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50397 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Handle security security bit in p9_sbe_attr_setupspashabk-in2017-12-041-20/+38
| | | | | | | | | | | | | | | Fix enabling of security in the current power cycle Change-Id: I546407d90989a876a75b5d36312d31e438024940 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48440 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48444 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Use HCode header timebase frequency for pk traceDoug Gilbert2017-12-043-6/+13
| | | | | | | | | | | | | | | | | Change-Id: I34a9d8d1a003ae6b07b50039a9ea57ff9fd5af4d RTC: 179852 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46227 Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46233 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Chip address extension workaround for HW423589 (option2), part1Joe McGill2017-12-0115-61/+397
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml nest_attributes.xml p9_sbe_attributes.xml add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines set of chips which physically support the feature add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips which need extended address workaround for MCD issue (applied only to Nimbus EC 21) add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of memory groups formed. Written by p9_mss_eff_grouping. For HW423589_OPTION2, this will default to 512GB add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold extended address configuration. Written by p9_sbe_fabricinit (SBE) and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will default to 0b0000_111, consuming all chip ID bits for extended addressing. p9_fbc_utils.C p9_fbc_utils.H extend p9_fbc_utils_get_chip_base_address to support address extension, now outputs set of ranges in each msel based on ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID maintain original function for PPE platform which requires knowledge of non-aliased base addresses only, for code size p9_mss_eff_grouping.C p9_mss_eff_grouping_errors.xml set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform restrict size of groups formed for HW423589_OPTION2 p9_sbe_fabricinit.C set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform configure FBC/NMMU extended addressing registers p9_setup_bars.C p9_setup_bars_defs.H p9_setup_bars_errors.xml add general purpose support for extended address mode for HW423589_OPTION2, configure static MCD setup p9_hcode_image_defines.H p9_hcode_image_build.C customize SGPE image with address extension configuration to apply p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scom.initfile p9.l3.scom.initfile p9.ncu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_hcd_cache_scominit.C p9_hcd_cache_scominit.c p9_pcie_config.C set unit address extension configuration on supported chips p9_rng_init_phase2.C p9_sbe_scominit.C p9c_set_inband_addr.C p9_sbe_load_bootloader.C p9_sbe_mcs_setup.C adapt to alterations in p9_fbc_utils_get_chip_base_address Change-Id: I614d566c073f1169f04f647057e6e85889f1c237 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48892 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support for PPE commit 49883 to error out on non-TOR ring section.Claus Michael Olsen2017-12-011-0/+3
| | | | | | | | | | | | | | Change-Id: I7912c20e865aafe28c894bad98e4fbc3156d59ce Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50107 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50116
* Enable DD2.2 in op buildspashabk-in2017-12-011-5/+4
| | | | | | | | | | | Remove DD1.0 from pnor sbe partition Add DD2.2 to the sbe partition Change-Id: Idc32069a866b8d44c877eaedcf3ef8d0b4786909 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50182 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Secure Boot: Temporarily whitelist various registers to resolve blacklist issuesNick Bofferding2017-12-011-0/+34
| | | | | | | | | | | | | Change-Id: Ia467db2a17581b55945cdad2d74a3aaff7ffa210 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50201 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50215
* Modify INT FIR configuration settingsDavid Kauer2017-12-011-0/+24
| | | | | | | | | | | | | | | | | Change-Id: Id4c1686cb111a14bef856fc91053228ff2e490d4 CQ:HW426891 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49578 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49866 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SBE:putring: Ring Id validation checkPrasad Bg Ranganath2017-12-011-3/+7
| | | | | | | | | Change-Id: I6d089d488f0673fe539a9030bccdd59a504e7d59 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49349 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert ATTR_CEN_ECID back to ATTR_ECIDDan Crowell2017-12-011-4/+2
| | | | | | | | | | | | | | | | | | Firmware needs a common attribute for all chip targets Change-Id: Ia448b73bed691f493c7edb98e675e6febce74d23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49941 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49944 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* fapi2: Fix template call sites for GCC 7Joel Stanley2017-12-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following errors stop hostboot from building with modern GCC: src/import/hwpf/fapi2/include/buffer.H:710:23: error: invalid operands of types ‘<unresolved overloaded function type>’ and ‘fapi2::bufferTraits<long unsigned int, unsigned int>::bits_type {aka unsigned int}’ to binary ‘operator<’ out.insert<TS, L, SS>(iv_data); ~~~~~~~~~~^~~ src/import/hwpf/fapi2/include/buffer.H: In member function ‘fapi2::buffer<T, TT>& fapi2::buffer<T, TT>::flipBit()’: src/import/hwpf/fapi2/include/buffer.H:316:49: error: expected primary-expression before ‘)’ token iv_data ^= buffer<T>().setBit<B, C>(); ^ In both cases the call site needs to be prepended with the keyword 'template'. Otherwise the name is assumed to be a non-template (as per C++ 14.2/4). Change-Id: I925c35d51787c4f4f232372f0e1299ec2a5cab42 Signed-off-by: Joel Stanley <joel.stanley@au1.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49760 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49890 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: EX deconfigure masking for EQ chiplet FIRYue Du2017-12-011-1/+19
| | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: Ib5ec8e5b201631f264e4dba42f4bd387164664fa CQ: SW408926 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50147 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50151 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Added chiplet range for 0x107D0 scom address in BL/WL csvnagurram-in2017-11-281-1/+1
| | | | | | | | | | | | | | | | | Dump need to write data to 0x107D0 scom address for controlling the start/stop/rest trace for all perv chiplets. Hence added chiplet range for aforementioned scom address in BL/WL csv. Change-Id: I932d5275d76d2491dc0972bbfc2f25e52c59b1c3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50042 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50044 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstateJoe McGill2017-11-284-41/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_chiplet_reset remove deassertion of OBUS clk async reset, shift to p9_sbe_startclock_chiplets p9_sbe_startclock_chiplets conditionally remove workaround (assert iovalid, clock, deassert iovalid) instituted to flush DL glmux select pipeline, these will be set via scan for supported chips deassert OBUS clk async reset p9_chiplet_scominit remove assertion of NV iovalid from HB p9.npu.scan.initfile alter flush state of NVDL glsmux select pipe latches to 0b10 p9.obus.scan.initfile alter flush state of IOO PHY logic to enable lane clocks clear RX_LANE_ANA_PDWN clear RX_CLKDIST_PDWN set RX_IREF_PDWN_B Change-Id: Ib9d4bf18a181ed1cf55eaf92e1486c494757d657 CQ: HW404391 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50027 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50029 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update backing buildSachin Gupta2017-11-281-1/+1
| | | | | | | Change-Id: I3d73010267e8b47c23d53165de24d7aee1bc2e03 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50083 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Handle OCC SRAM secure mem windowspashabk-in2017-11-248-129/+228
| | | | | | | | | | Allow access to only the unsecure memory windows of OCC SRAM Change-Id: I66a9383b2470fa0124708a582db4a643738535cf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48796 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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