diff options
Diffstat (limited to 'src/test')
-rwxr-xr-x | src/test/testcases/test.xml | 1 | ||||
-rwxr-xr-x | src/test/testcases/testGetCapabilities.py | 2 | ||||
-rwxr-xr-x | src/test/testcases/testQuiesce.py | 57 | ||||
-rw-r--r-- | src/test/testcases/testQuiesce.xml | 45 |
4 files changed, 104 insertions, 1 deletions
diff --git a/src/test/testcases/test.xml b/src/test/testcases/test.xml index 32be24f4..668aa841 100755 --- a/src/test/testcases/test.xml +++ b/src/test/testcases/test.xml @@ -41,6 +41,7 @@ <include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include> <include>../simics/targets/p9_nimbus/sbeTest/testExecutorPutRing.xml</include> <include>../simics/targets/p9_nimbus/sbeTest/testGetRing.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testQuiesce.xml</include> <testcase> <simcmd>sbe-trace 0</simcmd> </testcase> diff --git a/src/test/testcases/testGetCapabilities.py b/src/test/testcases/testGetCapabilities.py index 006d17c2..33971638 100755 --- a/src/test/testcases/testGetCapabilities.py +++ b/src/test/testcases/testGetCapabilities.py @@ -48,7 +48,7 @@ EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc 0xa7,0x0,0x0,0x1, # control Instruction 0x00,0x0,0x0,0x0]; -EXPDATA3 = [0xa8,0x0,0x0,0x03, #getcapability/getSbeFFDC +EXPDATA3 = [0xa8,0x0,0x0,0x13, #getcapability/getSbeFFDC/quiesce 0x0,0x0,0x0,0x0, 0xc0,0xde,0xa8,0x02, 0x0,0x0,0x0,0x0, diff --git a/src/test/testcases/testQuiesce.py b/src/test/testcases/testQuiesce.py new file mode 100755 index 00000000..55aa2194 --- /dev/null +++ b/src/test/testcases/testQuiesce.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testQuiesce.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +TESTDATA = [0,0,0,2, + 0,0,0xA8,0x06 ] + +EXPDATA = [0xc0,0xde,0xa8,0x06, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x3]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testQuiesce.xml b/src/test/testcases/testQuiesce.xml new file mode 100644 index 00000000..8b502949 --- /dev/null +++ b/src/test/testcases/testQuiesce.xml @@ -0,0 +1,45 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testQuiesce.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <!-- SBE Quiesce Test case --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testQuiesce.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- A Get Capabilities chip-op should succeed post the Quiesce --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetCapabilities.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- A GetScom/PutScom chip-op should succeed post the Quiesce --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- An Adu put chip-op should succeed post the Quiesce --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> |