diff options
Diffstat (limited to 'src/test')
| -rwxr-xr-x | src/test/testcases/testGetCapabilities.py | 2 | ||||
| -rw-r--r-- | src/test/testcases/testGetRing.py | 8 | ||||
| -rw-r--r-- | src/test/testcases/testQuiesce.xml | 13 |
3 files changed, 15 insertions, 8 deletions
diff --git a/src/test/testcases/testGetCapabilities.py b/src/test/testcases/testGetCapabilities.py index cc66ecf1..3cc21027 100755 --- a/src/test/testcases/testGetCapabilities.py +++ b/src/test/testcases/testGetCapabilities.py @@ -32,7 +32,7 @@ TESTDATA = [0,0,0,2, EXPDATA1 = [0x0,0x0,0x0,0x0, 0x0,0x0,0x0,0x0, - 0xa1,0x0,0x0,0x01, # istep + 0xa1,0x0,0x0,0x03, # istep/suspendio 0x0,0x0,0x0,0x0, 0xa2,0x0,0x0,0x0f, #getscom/putscom/modifyscom/putscomundermask 0x0,0x0,0x0,0x0, diff --git a/src/test/testcases/testGetRing.py b/src/test/testcases/testGetRing.py index 0b47c286..e241fd54 100644 --- a/src/test/testcases/testGetRing.py +++ b/src/test/testcases/testGetRing.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -34,10 +34,10 @@ LOOP_COUNT = 1 GETRING_TESTDATA = [0,0,0,0x6, 0,0,0xA3,0x01, 0x20,0x03,0x70,0x01, # address - 0,0,0x4D,0xF1, # length of data in bits + 0,0,0x54,0xA5, # length of data in bits 0x00,0x00,0x00,0x01] -GETRING_EXPDATA = [0,0,0x4D,0xF1, # length of data in bits +GETRING_EXPDATA = [0,0,0x54,0xA5, # length of data in bits 0xc0,0xde,0xa3,0x01, 0x0,0x0,0x0,0x0, 0x00,0x0,0x0,0x03]; @@ -51,7 +51,7 @@ def main( ): # GetRing test - Aligned Data testUtil.writeUsFifo( GETRING_TESTDATA ) testUtil.writeEot( ) - testUtil.readDsEntry ( 624 ) ## 6242 entries + testUtil.readDsEntry ( 678 ) ## 6242 entries testUtil.readDsFifo( GETRING_EXPDATA ) testUtil.runCycles( 10000000 ) testUtil.readEot( ) diff --git a/src/test/testcases/testQuiesce.xml b/src/test/testcases/testQuiesce.xml index 8b502949..9619b7ae 100644 --- a/src/test/testcases/testQuiesce.xml +++ b/src/test/testcases/testQuiesce.xml @@ -5,7 +5,8 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> @@ -38,8 +39,14 @@ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd> <exitonerror>yes</exitonerror> </testcase> + <!-- Taking out this test-case since this requires clock now, and we have + already done stop clock before quiesce. Somehow there is dependency + of clock with ADU, this used to work in DD1. + We can't move stopclock testcase below this since stop clock is from + seeprom region and quiesce prohibits seeprom access. + Disabling ADU access after quiesce operation. --> <!-- An Adu put chip-op should succeed post the Quiesce --> - <testcase> + <!--<testcase> <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd> <exitonerror>yes</exitonerror> - </testcase> + </testcase> --> |
