diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/framework/etc/patches/standalone.simics.patch | 32 | ||||
| -rwxr-xr-x | src/test/testcases/testExecutorPutRing.xml | 6 | ||||
| -rw-r--r-- | src/test/testcases/testFifoReset.xml | 2 | ||||
| -rwxr-xr-x | src/test/testcases/testGetRing.xml | 6 |
4 files changed, 28 insertions, 18 deletions
diff --git a/src/test/framework/etc/patches/standalone.simics.patch b/src/test/framework/etc/patches/standalone.simics.patch index ccd5be17..da9c0e51 100644 --- a/src/test/framework/etc/patches/standalone.simics.patch +++ b/src/test/framework/etc/patches/standalone.simics.patch @@ -1,13 +1,19 @@ -70c70,77 -< ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64 ---- -> # Set the Fsp bit in MBOX3 reg (bit 3), This is to make SBE pick default HRMOR -> # i.e. 128MB instead of FspLess HRMOR address. Action files in simics are -> # hardcoded to support 128MB presently. we need to update Simic Action file to -> # be flexible and pick HRMOR basis this Fsp bit. -> # TODO - RTC 196986 -> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "90000000_00000000" 64 -> # Set security enabled bit -> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x00050001 "0C000002_00000000" 64 -74a82 -> ($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x08 "00080000" 32 +--- standalone.simics 2019-02-05 02:31:38.785109846 -0600 ++++ standalone_930.simics 2019-02-05 02:30:55.445109859 -0600 +@@ -108,7 +108,15 @@ + # Set mailbox scratch registers so that the SBE starts in plck mode + # Set Boot Freq valid bit (bit 3) and valid data bit (bit 7) + ($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003F "31000000_00000000" 64 +- ($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003A "00000000_00000000" 64 ++ ++ # Set the Fsp bit in MBOX3 reg (bit 3), This is to make SBE pick default HRMOR ++ # i.e. 128MB instead of FspLess HRMOR address. Action files in simics are ++ # hardcoded to support 128MB presently. we need to update Simic Action file to ++ # be flexible and pick HRMOR basis this Fsp bit. ++ # TODO - RTC 196986 ++ ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "90000000_00000000" 64 ++ # Set security enabled bit ++ ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x00050001 "0C000002_00000000" 64 + + # Set the Nest PLL Bucket ID to 5 in the 4th byte of Mbox Scratch Reg 4 + ($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003B "00000005_00000000" 64 diff --git a/src/test/testcases/testExecutorPutRing.xml b/src/test/testcases/testExecutorPutRing.xml index bd130b9b..085e19e5 100755 --- a/src/test/testcases/testExecutorPutRing.xml +++ b/src/test/testcases/testExecutorPutRing.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -23,9 +23,11 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <?xml version="1.0" encoding="UTF-8"?> - +<!--TODO: Uncomment the fifo reset test case once simics fixes the issue --> +<!-- <testcase> <simcmd>run-python-file targets/p9_nimbus/sbeTest/testExecutorPutRing.py</simcmd> <exitonerror>yes</exitonerror> </testcase> +--> diff --git a/src/test/testcases/testFifoReset.xml b/src/test/testcases/testFifoReset.xml index 8aacef0c..909de6b2 100644 --- a/src/test/testcases/testFifoReset.xml +++ b/src/test/testcases/testFifoReset.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> diff --git a/src/test/testcases/testGetRing.xml b/src/test/testcases/testGetRing.xml index 526ee99a..07b63bf2 100755 --- a/src/test/testcases/testGetRing.xml +++ b/src/test/testcases/testGetRing.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -22,9 +22,11 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - +<!--TODO: Uncomment the fifo reset test case once simics fixes the issue --> +<!-- <testcase> <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetRing.py</simcmd> <exitonerror>yes</exitonerror> </testcase> +--> |
