diff options
Diffstat (limited to 'src/test')
-rwxr-xr-x | src/test/framework/autocitest (renamed from src/test/citest/autocitest) | 2 | ||||
-rwxr-xr-x | src/test/framework/build-script (renamed from src/test/citest/build-script) | 4 | ||||
-rwxr-xr-x | src/test/framework/check-copyright (renamed from src/test/citest/check-copyright) | 4 | ||||
-rwxr-xr-x | src/test/framework/copyright-check.sh (renamed from src/test/citest/copyright-check.sh) | 2 | ||||
-rwxr-xr-x | src/test/framework/create-sandbox (renamed from src/test/citest/create-sandbox) | 2 | ||||
-rw-r--r-- | src/test/framework/etc/patches/chip.act.patch (renamed from src/test/citest/etc/patches/chip.act.patch) | 0 | ||||
-rw-r--r-- | src/test/framework/etc/patches/patchlist.txt (renamed from src/test/citest/etc/patches/patchlist.txt) | 0 | ||||
-rw-r--r-- | src/test/framework/etc/patches/pervasive.act.patch (renamed from src/test/citest/etc/patches/pervasive.act.patch) | 0 | ||||
-rw-r--r-- | src/test/framework/etc/patches/powermgmt.act.patch (renamed from src/test/citest/etc/patches/powermgmt.act.patch) | 0 | ||||
-rw-r--r-- | src/test/framework/etc/patches/standalone.simics.patch (renamed from src/test/citest/etc/patches/standalone.simics.patch) | 0 | ||||
-rwxr-xr-x | src/test/framework/etc/workarounds.postsimsetup (renamed from src/test/citest/etc/workarounds.postsimsetup) | 5 | ||||
-rwxr-xr-x | src/test/framework/etc/workarounds.presimsetup (renamed from src/test/citest/etc/workarounds.presimsetup) | 2 | ||||
-rwxr-xr-x | src/test/framework/populate-sandbox (renamed from src/test/citest/populate-sandbox) | 7 | ||||
-rwxr-xr-x | src/test/framework/sbetest-start.sh (renamed from src/test/citest/sbetest-start.sh) | 4 | ||||
-rwxr-xr-x | src/test/framework/setup-env (renamed from src/test/citest/setup-env) | 4 | ||||
-rwxr-xr-x | src/test/testcases/ffdc.xml (renamed from src/test/ffdc.xml) | 2 | ||||
-rwxr-xr-x | src/test/testcases/test.xml (renamed from src/test/test.xml) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testAbort.py (renamed from src/test/testAbort.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testAduMem.xml (renamed from src/test/testAduMem.xml) | 2 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_ecc.py (renamed from src/test/testAduMem_ecc.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_itag.py (renamed from src/test/testAduMem_itag.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_noEccNoItag.py (renamed from src/test/testAduMem_noEccNoItag.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_withEccItag.py (renamed from src/test/testAduMem_withEccItag.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_withEccWithItagReadWrite.py (renamed from src/test/testAduMem_withEccWithItagReadWrite.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testCntlInstruction.py (renamed from src/test/testCntlInstruction.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testCntlInstruction.xml (renamed from src/test/testCntlInstruction.xml) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testContinueMpipl.py (renamed from src/test/testContinueMpipl.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testContinueSbeBoot.py (renamed from src/test/testContinueSbeBoot.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testEnterMpipl.py (renamed from src/test/testEnterMpipl.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testExecutorMemory.py (renamed from src/test/testExecutorMemory.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testExecutorPSU.py (renamed from src/test/testExecutorPSU.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testExecutorPutRing.py (renamed from src/test/testExecutorPutRing.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testExecutorPutRing.xml (renamed from src/test/testExecutorPutRing.xml) | 2 | ||||
-rw-r--r-- | src/test/testcases/testFifoReset.py (renamed from src/test/testFifoReset.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testFifoReset.xml (renamed from src/test/testFifoReset.xml) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testGeneric.xml (renamed from src/test/testGeneric.xml) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testGetCapabilities.py (renamed from src/test/testGetCapabilities.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testGetMem.py (renamed from src/test/testGetMem.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testGetMem_expdata.py (renamed from src/test/testGetMem_expdata.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testGetRing.py (renamed from src/test/testGetRing.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testGetRing.xml (renamed from src/test/testGetRing.xml) | 2 | ||||
-rw-r--r-- | src/test/testcases/testIstep.xml (renamed from src/test/testIstep.xml) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testIstepAuto.py (renamed from src/test/testIstepAuto.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testIstepInvalid.py (renamed from src/test/testIstepInvalid.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testIstepInvalidFenced.py (renamed from src/test/testIstepInvalidFenced.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testIstepSuccess.py (renamed from src/test/testIstepSuccess.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testModifyScom.py (renamed from src/test/testModifyScom.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testPSUUserUtil.py (renamed from src/test/testPSUUserUtil.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testPSUUtil.py (renamed from src/test/testPSUUtil.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testPutGetInScom.py (renamed from src/test/testPutGetInScom.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testPutGetMem.xml (renamed from src/test/testPutGetMem.xml) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testPutGetRegFpr.py (renamed from src/test/testPutGetRegFpr.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testPutGetRegGpr.py (renamed from src/test/testPutGetRegGpr.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testPutGetRegSpr.py (renamed from src/test/testPutGetRegSpr.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testPutGetScom.py (renamed from src/test/testPutGetScom.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testPutMem.py (renamed from src/test/testPutMem.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testPutMem_fail.py (renamed from src/test/testPutMem_fail.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testPutScomUnderMask.py (renamed from src/test/testPutScomUnderMask.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testRegAccess.xml (renamed from src/test/testRegAccess.xml) | 2 | ||||
-rw-r--r-- | src/test/testcases/testRegistry.py (renamed from src/test/testRegistry.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testSbeDump.py (renamed from src/test/testSbeDump.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testScom.xml (renamed from src/test/testScom.xml) | 2 | ||||
-rw-r--r-- | src/test/testcases/testSram.py (renamed from src/test/testSram.py) | 2 | ||||
-rwxr-xr-x | src/test/testcases/testSram.xml (renamed from src/test/testSram.xml) | 2 | ||||
-rw-r--r-- | src/test/testcases/testStartInstruction.py (renamed from src/test/testStartInstruction.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testStopInstruction.py (renamed from src/test/testStopInstruction.py) | 2 | ||||
-rw-r--r-- | src/test/testcases/testUtil.py (renamed from src/test/testUtil.py) | 2 |
67 files changed, 70 insertions, 70 deletions
diff --git a/src/test/citest/autocitest b/src/test/framework/autocitest index 088bb58b..3b7332b2 100755 --- a/src/test/citest/autocitest +++ b/src/test/framework/autocitest @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/autocitest $ +# $Source: src/test/framework/autocitest $ # # OpenPOWER sbe Project # diff --git a/src/test/citest/build-script b/src/test/framework/build-script index 5ad6b1bd..486a0ac9 100755 --- a/src/test/citest/build-script +++ b/src/test/framework/build-script @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/build-script $ +# $Source: src/test/framework/build-script $ # # OpenPOWER sbe Project # @@ -31,7 +31,7 @@ if [ -z $SBEROOT ]; then source "$WORKSPACE/env.bash" fi -source "$SBEROOT/src/test/citest/setup-env" +source "$SBEROOT/src/test/framework/setup-env" # Check copyright. #check-copyright > copyright.log 2>&1 & diff --git a/src/test/citest/check-copyright b/src/test/framework/check-copyright index 28db5512..bd893b39 100755 --- a/src/test/citest/check-copyright +++ b/src/test/framework/check-copyright @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/check-copyright $ +# $Source: src/test/framework/check-copyright $ # # OpenPOWER sbe Project # @@ -23,7 +23,7 @@ # # IBM_PROLOG_END_TAG -COPYRIGHT_CHECK=${SBEROOT}/src/test/citest/copyright-check.sh +COPYRIGHT_CHECK=${SBEROOT}/src/test/framework/copyright-check.sh COMMIT_CHECK=${SBEROOT}/src/tools/hooks/verify-commit $COPYRIGHT_CHECK || exit -1 diff --git a/src/test/citest/copyright-check.sh b/src/test/framework/copyright-check.sh index 3d7c5d54..ec305360 100755 --- a/src/test/citest/copyright-check.sh +++ b/src/test/framework/copyright-check.sh @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/copyright-check.sh $ +# $Source: src/test/framework/copyright-check.sh $ # # OpenPOWER sbe Project # diff --git a/src/test/citest/create-sandbox b/src/test/framework/create-sandbox index b6a1e7e8..add0a78b 100755 --- a/src/test/citest/create-sandbox +++ b/src/test/framework/create-sandbox @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/create-sandbox $ +# $Source: src/test/framework/create-sandbox $ # # OpenPOWER sbe Project # diff --git a/src/test/citest/etc/patches/chip.act.patch b/src/test/framework/etc/patches/chip.act.patch index 0b9cf0f0..0b9cf0f0 100644 --- a/src/test/citest/etc/patches/chip.act.patch +++ b/src/test/framework/etc/patches/chip.act.patch diff --git a/src/test/citest/etc/patches/patchlist.txt b/src/test/framework/etc/patches/patchlist.txt index 4fd0444a..4fd0444a 100644 --- a/src/test/citest/etc/patches/patchlist.txt +++ b/src/test/framework/etc/patches/patchlist.txt diff --git a/src/test/citest/etc/patches/pervasive.act.patch b/src/test/framework/etc/patches/pervasive.act.patch index 5531bef6..5531bef6 100644 --- a/src/test/citest/etc/patches/pervasive.act.patch +++ b/src/test/framework/etc/patches/pervasive.act.patch diff --git a/src/test/citest/etc/patches/powermgmt.act.patch b/src/test/framework/etc/patches/powermgmt.act.patch index efb03845..efb03845 100644 --- a/src/test/citest/etc/patches/powermgmt.act.patch +++ b/src/test/framework/etc/patches/powermgmt.act.patch diff --git a/src/test/citest/etc/patches/standalone.simics.patch b/src/test/framework/etc/patches/standalone.simics.patch index bdc40fd8..bdc40fd8 100644 --- a/src/test/citest/etc/patches/standalone.simics.patch +++ b/src/test/framework/etc/patches/standalone.simics.patch diff --git a/src/test/citest/etc/workarounds.postsimsetup b/src/test/framework/etc/workarounds.postsimsetup index 057c3b00..ac7f3a29 100755 --- a/src/test/citest/etc/workarounds.postsimsetup +++ b/src/test/framework/etc/workarounds.postsimsetup @@ -2,11 +2,12 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/etc/workarounds.postsimsetup $ +# $Source: src/test/framework/etc/workarounds.postsimsetup $ # # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -39,5 +40,5 @@ echo "+++ Patching standalone.simics" mkdir -p $SANDBOXBASE/obj/ppc/simu/scripts/hbfw cp $BACKING_BUILD/obj/ppc/simu/scripts/hbfw/standalone.simics $SANDBOXBASE/obj/ppc/simu/scripts/hbfw -patch -p0 $SANDBOXBASE/obj/ppc/simu/scripts/hbfw/standalone.simics $SBEROOT/src/test/citest/etc/patches/standalone.simics.patch +patch -p0 $SANDBOXBASE/obj/ppc/simu/scripts/hbfw/standalone.simics $SBEROOT/src/test/framework/etc/patches/standalone.simics.patch diff --git a/src/test/citest/etc/workarounds.presimsetup b/src/test/framework/etc/workarounds.presimsetup index 638a1e84..e863b07d 100755 --- a/src/test/citest/etc/workarounds.presimsetup +++ b/src/test/framework/etc/workarounds.presimsetup @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/etc/workarounds.presimsetup $ +# $Source: src/test/framework/etc/workarounds.presimsetup $ # # OpenPOWER sbe Project # diff --git a/src/test/citest/populate-sandbox b/src/test/framework/populate-sandbox index 488462b1..729b61fa 100755 --- a/src/test/citest/populate-sandbox +++ b/src/test/framework/populate-sandbox @@ -2,12 +2,11 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/populate-sandbox $ +# $Source: src/test/framework/populate-sandbox $ # # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -45,7 +44,7 @@ mkdir -p $SBEFW_IMG_DIR || exit -1 # Copy sbe binaries cp $SBEROOT/images/*.bin $SBEFW_IMG_DIR/ || exit -1 -cp $SBEROOT/obj/simics.tar $SBEFW_DIR/ || exit -1 +cp $SBEROOT/images/simics.tar $SBEFW_DIR/ || exit -1 # Compile sbe code in sandbox to copy binaries at right place echo "---Setup sandbox for sbe binaries." @@ -57,5 +56,5 @@ execute_in_sandbox "cd $SBEFW_DIR; mk install_all" \ # Copy test files. -cp -r $SBEROOT/src/test/* $SBETESTDIR/ || exit -1 +cp -r $SBEROOT/src/test/testcases/* $SBETESTDIR/ || exit -1 diff --git a/src/test/citest/sbetest-start.sh b/src/test/framework/sbetest-start.sh index f39ed84e..a0d7f27a 100755 --- a/src/test/citest/sbetest-start.sh +++ b/src/test/framework/sbetest-start.sh @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/sbetest-start.sh $ +# $Source: src/test/framework/sbetest-start.sh $ # # OpenPOWER sbe Project # @@ -26,7 +26,7 @@ if [ -z $SBE_CI_ENV_SETUP ]; then unset $SANDBOXBASE unset $SANDBOXNAME - source "$SBEROOT/src/test/citest/setup-env" + source "$SBEROOT/src/test/framework/setup-env" fi # Front end to autocitest - script to execute unit tests under simics. diff --git a/src/test/citest/setup-env b/src/test/framework/setup-env index ee0bc18b..6de2d8fd 100755 --- a/src/test/citest/setup-env +++ b/src/test/framework/setup-env @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/citest/setup-env $ +# $Source: src/test/framework/setup-env $ # # OpenPOWER sbe Project # @@ -23,7 +23,7 @@ # # IBM_PROLOG_END_TAG -export CITESTPATH=${SBEROOT}/src/test/citest +export CITESTPATH=${SBEROOT}/src/test/framework export PATH=${CITESTPATH}:${PATH} # If we are running under Jenkins we need to pick a random-ish sandbox name diff --git a/src/test/ffdc.xml b/src/test/testcases/ffdc.xml index 65364249..b8773556 100755 --- a/src/test/ffdc.xml +++ b/src/test/testcases/ffdc.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/ffdc.xml $ --> +<!-- $Source: src/test/testcases/ffdc.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/test.xml b/src/test/testcases/test.xml index 2172b8f6..240ec318 100755 --- a/src/test/test.xml +++ b/src/test/testcases/test.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/test.xml $ --> +<!-- $Source: src/test/testcases/test.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testAbort.py b/src/test/testcases/testAbort.py index 7039c70b..c8be29bf 100755 --- a/src/test/testAbort.py +++ b/src/test/testcases/testAbort.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testAbort.py $ +# $Source: src/test/testcases/testAbort.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testAduMem.xml b/src/test/testcases/testAduMem.xml index 1fcbe12d..fe3194d7 100644 --- a/src/test/testAduMem.xml +++ b/src/test/testcases/testAduMem.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testAduMem.xml $ --> +<!-- $Source: src/test/testcases/testAduMem.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testAduMem_ecc.py b/src/test/testcases/testAduMem_ecc.py index f60af64e..9741d1cb 100644 --- a/src/test/testAduMem_ecc.py +++ b/src/test/testcases/testAduMem_ecc.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testAduMem_ecc.py $ +# $Source: src/test/testcases/testAduMem_ecc.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testAduMem_itag.py b/src/test/testcases/testAduMem_itag.py index 8c7d9a3c..33a594ab 100644 --- a/src/test/testAduMem_itag.py +++ b/src/test/testcases/testAduMem_itag.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testAduMem_itag.py $ +# $Source: src/test/testcases/testAduMem_itag.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testAduMem_noEccNoItag.py b/src/test/testcases/testAduMem_noEccNoItag.py index ccbad942..354ad8bd 100644 --- a/src/test/testAduMem_noEccNoItag.py +++ b/src/test/testcases/testAduMem_noEccNoItag.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testAduMem_noEccNoItag.py $ +# $Source: src/test/testcases/testAduMem_noEccNoItag.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testAduMem_withEccItag.py b/src/test/testcases/testAduMem_withEccItag.py index 7db53813..d3c9f9c0 100644 --- a/src/test/testAduMem_withEccItag.py +++ b/src/test/testcases/testAduMem_withEccItag.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testAduMem_withEccItag.py $ +# $Source: src/test/testcases/testAduMem_withEccItag.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testAduMem_withEccWithItagReadWrite.py b/src/test/testcases/testAduMem_withEccWithItagReadWrite.py index 95578979..3d294915 100644 --- a/src/test/testAduMem_withEccWithItagReadWrite.py +++ b/src/test/testcases/testAduMem_withEccWithItagReadWrite.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testAduMem_withEccWithItagReadWrite.py $ +# $Source: src/test/testcases/testAduMem_withEccWithItagReadWrite.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testCntlInstruction.py b/src/test/testcases/testCntlInstruction.py index 125b1b67..f3143e70 100644 --- a/src/test/testCntlInstruction.py +++ b/src/test/testcases/testCntlInstruction.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testCntlInstruction.py $ +# $Source: src/test/testcases/testCntlInstruction.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testCntlInstruction.xml b/src/test/testcases/testCntlInstruction.xml index 07e22ee3..ef16cd40 100755 --- a/src/test/testCntlInstruction.xml +++ b/src/test/testcases/testCntlInstruction.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testCntlInstruction.xml $ --> +<!-- $Source: src/test/testcases/testCntlInstruction.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testContinueMpipl.py b/src/test/testcases/testContinueMpipl.py index 080e479a..17f9f7fa 100755 --- a/src/test/testContinueMpipl.py +++ b/src/test/testcases/testContinueMpipl.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testContinueMpipl.py $ +# $Source: src/test/testcases/testContinueMpipl.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testContinueSbeBoot.py b/src/test/testcases/testContinueSbeBoot.py index 5f64f0fa..f3542eda 100755 --- a/src/test/testContinueSbeBoot.py +++ b/src/test/testcases/testContinueSbeBoot.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testContinueSbeBoot.py $ +# $Source: src/test/testcases/testContinueSbeBoot.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testEnterMpipl.py b/src/test/testcases/testEnterMpipl.py index 8d225831..ce99c81b 100755 --- a/src/test/testEnterMpipl.py +++ b/src/test/testcases/testEnterMpipl.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testEnterMpipl.py $ +# $Source: src/test/testcases/testEnterMpipl.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testExecutorMemory.py b/src/test/testcases/testExecutorMemory.py index 125528bf..fe1b8526 100644 --- a/src/test/testExecutorMemory.py +++ b/src/test/testcases/testExecutorMemory.py @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testExecutorMemory.py $ +# $Source: src/test/testcases/testExecutorMemory.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testExecutorPSU.py b/src/test/testcases/testExecutorPSU.py index 5c58a954..0b5d83d1 100644 --- a/src/test/testExecutorPSU.py +++ b/src/test/testcases/testExecutorPSU.py @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testExecutorPSU.py $ +# $Source: src/test/testcases/testExecutorPSU.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testExecutorPutRing.py b/src/test/testcases/testExecutorPutRing.py index d6c74bb8..59949a9f 100644 --- a/src/test/testExecutorPutRing.py +++ b/src/test/testcases/testExecutorPutRing.py @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testExecutorPutRing.py $ +# $Source: src/test/testcases/testExecutorPutRing.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testExecutorPutRing.xml b/src/test/testcases/testExecutorPutRing.xml index 56aabc0c..833484a8 100755 --- a/src/test/testExecutorPutRing.xml +++ b/src/test/testcases/testExecutorPutRing.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testExecutorPutRing.xml $ --> +<!-- $Source: src/test/testcases/testExecutorPutRing.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testFifoReset.py b/src/test/testcases/testFifoReset.py index 3b03e6c6..41eb6563 100644 --- a/src/test/testFifoReset.py +++ b/src/test/testcases/testFifoReset.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testFifoReset.py $ +# $Source: src/test/testcases/testFifoReset.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testFifoReset.xml b/src/test/testcases/testFifoReset.xml index 48b12a3e..b9ef674d 100644 --- a/src/test/testFifoReset.xml +++ b/src/test/testcases/testFifoReset.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testFifoReset.xml $ --> +<!-- $Source: src/test/testcases/testFifoReset.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testGeneric.xml b/src/test/testcases/testGeneric.xml index cc49a78b..85ce990a 100755 --- a/src/test/testGeneric.xml +++ b/src/test/testcases/testGeneric.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testGeneric.xml $ --> +<!-- $Source: src/test/testcases/testGeneric.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testGetCapabilities.py b/src/test/testcases/testGetCapabilities.py index e6831352..4a61d761 100755 --- a/src/test/testGetCapabilities.py +++ b/src/test/testcases/testGetCapabilities.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testGetCapabilities.py $ +# $Source: src/test/testcases/testGetCapabilities.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testGetMem.py b/src/test/testcases/testGetMem.py index a927f250..baf3b353 100644 --- a/src/test/testGetMem.py +++ b/src/test/testcases/testGetMem.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testGetMem.py $ +# $Source: src/test/testcases/testGetMem.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testGetMem_expdata.py b/src/test/testcases/testGetMem_expdata.py index 56b43119..df0b51f6 100644 --- a/src/test/testGetMem_expdata.py +++ b/src/test/testcases/testGetMem_expdata.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testGetMem_expdata.py $ +# $Source: src/test/testcases/testGetMem_expdata.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testGetRing.py b/src/test/testcases/testGetRing.py index d6d786b8..61fba66e 100644 --- a/src/test/testGetRing.py +++ b/src/test/testcases/testGetRing.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testGetRing.py $ +# $Source: src/test/testcases/testGetRing.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testGetRing.xml b/src/test/testcases/testGetRing.xml index a30802c2..808b2012 100755 --- a/src/test/testGetRing.xml +++ b/src/test/testcases/testGetRing.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testGetRing.xml $ --> +<!-- $Source: src/test/testcases/testGetRing.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testIstep.xml b/src/test/testcases/testIstep.xml index f0e71d61..70cf2a62 100644 --- a/src/test/testIstep.xml +++ b/src/test/testcases/testIstep.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testIstep.xml $ --> +<!-- $Source: src/test/testcases/testIstep.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testIstepAuto.py b/src/test/testcases/testIstepAuto.py index 8cbccffa..bb1fcb5f 100755 --- a/src/test/testIstepAuto.py +++ b/src/test/testcases/testIstepAuto.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testIstepAuto.py $ +# $Source: src/test/testcases/testIstepAuto.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testIstepInvalid.py b/src/test/testcases/testIstepInvalid.py index 5af909d7..cd26b209 100755 --- a/src/test/testIstepInvalid.py +++ b/src/test/testcases/testIstepInvalid.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testIstepInvalid.py $ +# $Source: src/test/testcases/testIstepInvalid.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testIstepInvalidFenced.py b/src/test/testcases/testIstepInvalidFenced.py index 568253af..f64074b8 100755 --- a/src/test/testIstepInvalidFenced.py +++ b/src/test/testcases/testIstepInvalidFenced.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testIstepInvalidFenced.py $ +# $Source: src/test/testcases/testIstepInvalidFenced.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testIstepSuccess.py b/src/test/testcases/testIstepSuccess.py index 83871896..f9e18436 100755 --- a/src/test/testIstepSuccess.py +++ b/src/test/testcases/testIstepSuccess.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testIstepSuccess.py $ +# $Source: src/test/testcases/testIstepSuccess.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testModifyScom.py b/src/test/testcases/testModifyScom.py index 703ad680..36d75aca 100755 --- a/src/test/testModifyScom.py +++ b/src/test/testcases/testModifyScom.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testModifyScom.py $ +# $Source: src/test/testcases/testModifyScom.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPSUUserUtil.py b/src/test/testcases/testPSUUserUtil.py index df586ab7..383cb97c 100644 --- a/src/test/testPSUUserUtil.py +++ b/src/test/testcases/testPSUUserUtil.py @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPSUUserUtil.py $ +# $Source: src/test/testcases/testPSUUserUtil.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPSUUtil.py b/src/test/testcases/testPSUUtil.py index 84b91ff7..efc7d5be 100644 --- a/src/test/testPSUUtil.py +++ b/src/test/testcases/testPSUUtil.py @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPSUUtil.py $ +# $Source: src/test/testcases/testPSUUtil.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutGetInScom.py b/src/test/testcases/testPutGetInScom.py index 03571eaa..2e42a253 100755 --- a/src/test/testPutGetInScom.py +++ b/src/test/testcases/testPutGetInScom.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutGetInScom.py $ +# $Source: src/test/testcases/testPutGetInScom.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutGetMem.xml b/src/test/testcases/testPutGetMem.xml index c386c933..ae82868c 100644 --- a/src/test/testPutGetMem.xml +++ b/src/test/testcases/testPutGetMem.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testPutGetMem.xml $ --> +<!-- $Source: src/test/testcases/testPutGetMem.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testPutGetRegFpr.py b/src/test/testcases/testPutGetRegFpr.py index 2b2cd75c..6bf0209e 100755 --- a/src/test/testPutGetRegFpr.py +++ b/src/test/testcases/testPutGetRegFpr.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutGetRegFpr.py $ +# $Source: src/test/testcases/testPutGetRegFpr.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutGetRegGpr.py b/src/test/testcases/testPutGetRegGpr.py index cd1e31b4..871ff375 100755 --- a/src/test/testPutGetRegGpr.py +++ b/src/test/testcases/testPutGetRegGpr.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutGetRegGpr.py $ +# $Source: src/test/testcases/testPutGetRegGpr.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutGetRegSpr.py b/src/test/testcases/testPutGetRegSpr.py index 55c6fa09..d42e4c53 100755 --- a/src/test/testPutGetRegSpr.py +++ b/src/test/testcases/testPutGetRegSpr.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutGetRegSpr.py $ +# $Source: src/test/testcases/testPutGetRegSpr.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutGetScom.py b/src/test/testcases/testPutGetScom.py index de020fb2..9c8700e4 100755 --- a/src/test/testPutGetScom.py +++ b/src/test/testcases/testPutGetScom.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutGetScom.py $ +# $Source: src/test/testcases/testPutGetScom.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutMem.py b/src/test/testcases/testPutMem.py index eec39f5f..cb0398ff 100644 --- a/src/test/testPutMem.py +++ b/src/test/testcases/testPutMem.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutMem.py $ +# $Source: src/test/testcases/testPutMem.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutMem_fail.py b/src/test/testcases/testPutMem_fail.py index b13032a1..a3ab46b5 100644 --- a/src/test/testPutMem_fail.py +++ b/src/test/testcases/testPutMem_fail.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutMem_fail.py $ +# $Source: src/test/testcases/testPutMem_fail.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testPutScomUnderMask.py b/src/test/testcases/testPutScomUnderMask.py index c8c58427..b3484bef 100755 --- a/src/test/testPutScomUnderMask.py +++ b/src/test/testcases/testPutScomUnderMask.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testPutScomUnderMask.py $ +# $Source: src/test/testcases/testPutScomUnderMask.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testRegAccess.xml b/src/test/testcases/testRegAccess.xml index a44eecac..c5876c0b 100755 --- a/src/test/testRegAccess.xml +++ b/src/test/testcases/testRegAccess.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testRegAccess.xml $ --> +<!-- $Source: src/test/testcases/testRegAccess.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testRegistry.py b/src/test/testcases/testRegistry.py index ff205dbd..dc15fc87 100644 --- a/src/test/testRegistry.py +++ b/src/test/testcases/testRegistry.py @@ -2,7 +2,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testRegistry.py $ +# $Source: src/test/testcases/testRegistry.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testSbeDump.py b/src/test/testcases/testSbeDump.py index 72d089e0..7d7a7d77 100644 --- a/src/test/testSbeDump.py +++ b/src/test/testcases/testSbeDump.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testSbeDump.py $ +# $Source: src/test/testcases/testSbeDump.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testScom.xml b/src/test/testcases/testScom.xml index d3df6196..6f59c7cd 100755 --- a/src/test/testScom.xml +++ b/src/test/testcases/testScom.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testScom.xml $ --> +<!-- $Source: src/test/testcases/testScom.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testSram.py b/src/test/testcases/testSram.py index 2b62597f..ca064c77 100644 --- a/src/test/testSram.py +++ b/src/test/testcases/testSram.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testSram.py $ +# $Source: src/test/testcases/testSram.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testSram.xml b/src/test/testcases/testSram.xml index 902786ad..a1e74162 100755 --- a/src/test/testSram.xml +++ b/src/test/testcases/testSram.xml @@ -1,7 +1,7 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/test/testSram.xml $ --> +<!-- $Source: src/test/testcases/testSram.xml $ --> <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> diff --git a/src/test/testStartInstruction.py b/src/test/testcases/testStartInstruction.py index d45e791c..cc5cba02 100644 --- a/src/test/testStartInstruction.py +++ b/src/test/testcases/testStartInstruction.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testStartInstruction.py $ +# $Source: src/test/testcases/testStartInstruction.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testStopInstruction.py b/src/test/testcases/testStopInstruction.py index a43463c7..37d79acf 100644 --- a/src/test/testStopInstruction.py +++ b/src/test/testcases/testStopInstruction.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testStopInstruction.py $ +# $Source: src/test/testcases/testStopInstruction.py $ # # OpenPOWER sbe Project # diff --git a/src/test/testUtil.py b/src/test/testcases/testUtil.py index 444319ab..2312d2b7 100644 --- a/src/test/testUtil.py +++ b/src/test/testcases/testUtil.py @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/test/testUtil.py $ +# $Source: src/test/testcases/testUtil.py $ # # OpenPOWER sbe Project # |