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-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C10
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H3
2 files changed, 12 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index fac39832..9b8cddd4 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -215,6 +215,16 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
for (auto& targ : l_perv_func_WO_Core_Cache)
{
FAPI_DBG("Configuring multicasting registers for Mc,Nest,Xb,Obus,pcie chiplets");
+
+ // if in ASYNC mode DO NOT add to multicast groups because the chiplet is non
+ // responsive. Wait until clocks are started up in hostboot
+ uint32_t l_chipletID = targ.getChipletNumber();
+
+ if((l_chipletID >= 7 && l_chipletID <= 8) && (!l_mc_sync_mode))
+ {
+ continue;
+ }
+
FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(targ));
}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
index c3b1a66b..990a01e9 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -53,6 +53,7 @@ namespace p9SbeChipletReset
{
enum P9_SBE_CHIPLET_RESET_Public_Constants
{
+ MCGR_CNFG_SETTING_EMPTY = 0xFC00000000000000ull,
MCGR_CNFG_SETTING_GROUP0 = 0xE0001C0000000000ull,
MCGR_CNFG_SETTING_GROUP1 = 0xE4001C0000000000ull,
MCGR_CNFG_SETTING_GROUP2 = 0xE8001C0000000000ull,
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