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-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index 9ec2c490..c5c3a67d 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -3077,6 +3077,34 @@
</attribute>
<attribute>
+ <id>ATTR_MSS_EFF_DPHY_WLO</id>
+ <targetType>TARGET_TYPE_MCS</targetType>
+ <description>
+ Write latency offset in number of clocks
+ </description>
+ <initToZero></initToZero>
+ <valueType>uint8</valueType>
+ <writeable/>
+ <mssUnits>nCK</mssUnits>
+ <mssAccessorName>eff_dphy_wlo</mssAccessorName>
+ <array>2</array>
+ </attribute>
+
+ <attribute>
+ <id>ATTR_MSS_EFF_DPHY_RLO</id>
+ <targetType>TARGET_TYPE_MCS</targetType>
+ <description>
+ Read latency offset in number of clocks
+ </description>
+ <initToZero></initToZero>
+ <valueType>uint8</valueType>
+ <writeable/>
+ <mssUnits>nCK</mssUnits>
+ <mssAccessorName>eff_dphy_rlo</mssAccessorName>
+ <array>2</array>
+ </attribute>
+
+ <attribute>
<id>ATTR_EFF_DRAM_TREFI</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
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