diff options
Diffstat (limited to 'src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml | 565 |
1 files changed, 509 insertions, 56 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml index 29c866d7..4b1a997d 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml @@ -25,61 +25,514 @@ <!-- This is an automatically generated file. --> <!-- File: p9_sbe_common_errors.xml. --> <!-- Halt codes for p9_sbe_common --> - <hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_ARY_ERR</rc> - <description>ary_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_ARY</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NSL_ERR</rc> - <description>nsl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_NSL</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_SL_ERR</rc> - <description>sl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_SL</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_CPLT_NOT_ALIGNED_ERR</rc> - <description>Chiplet not aligned</description> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc> - <description>Chiplet OPCG_DONE not set after clock start/stop command</description> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NEST_ARY_ERR</rc> - <description>ary_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_ARY</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NEST_NSL_ERR</rc> - <description>nsl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_NSL</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <sbeError/> - <rc>RC_NEST_SL_ERR</rc> - <description>sl_thold status not matching the expected value in clock start stop sequence</description> - <ffdc>READ_CLK_SL</ffdc> - </hwpError> - <!-- ******************************************************************** --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>ROOT_CTRL_REGISTERS_CFAM</id> + <cfamRegister>PERV_ROOT_CTRL0_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL1_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL2_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL3_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL4_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL5_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL6_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL7_FSI</cfamRegister> + <cfamRegister>PERV_ROOT_CTRL8_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>PERV_CTRL_REGISTERS_CFAM</id> + <cfamRegister>PERV_PERV_CTRL0_FSI</cfamRegister> + <cfamRegister>PERV_PERV_CTRL1_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>FSI2PIB_STATUS</id> + <cfamRegister>PERV_FSI2PIB_STATUS_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>OSC_SWITCH_SENSE_REGISTER_CFAM</id> + <cfamRegister>PERV_SNS1LTH_FSI</cfamRegister> + </registerFfdc> + <registerFfdc> + <id>OSC_SWITCH_SENSE_REGISTER</id> + <scomRegister>PERV_SNS1LTH_SCOM</scomRegister> + </registerFfdc> + <registerFfdc> + <id>OSC_ERROR_HOLD</id> + <scomRegister>PERV_TP_OSCERR_HOLD</scomRegister> + </registerFfdc> + <registerFfdc> + <id>ROOT_CTRL_REGISTERS</id> + <scomRegister>PERV_ROOT_CTRL0_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL1_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL2_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL3_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL4_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL5_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL6_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL7_SCOM</scomRegister> + <scomRegister>PERV_ROOT_CTRL8_SCOM</scomRegister> + </registerFfdc> + <registerFfdc> + <id>PERV_CTRL_REGISTERS</id> + <scomRegister>PERV_PERV_CTRL0_SCOM</scomRegister> + <scomRegister>PERV_PERV_CTRL1_SCOM</scomRegister> + </registerFfdc> + <registerFfdc> + <id>NET_CTRL_REGISTERS</id> + <scomRegister>PERV_NET_CTRL0</scomRegister> + <scomRegister>PERV_NET_CTRL1</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <scomRegister>PERV_CPLT_CTRL0</scomRegister> + <scomRegister>PERV_CPLT_CTRL1</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <scomRegister>PERV_CPLT_CONF0</scomRegister> + <scomRegister>PERV_CPLT_CONF1</scomRegister> + </registerFfdc> + <registerFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <scomRegister>PERV_CPLT_STAT0</scomRegister> + <scomRegister>PERV_CPLT_MASK0</scomRegister> + </registerFfdc> + <registerFfdc> + <id>PLL_LOCK_REG</id> + <scomRegister>PERV_PLL_LOCK_REG</scomRegister> + </registerFfdc> + <registerFfdc> + <id>I2C_REGISTERS</id> + <scomRegister>PU_CONTROL_REGISTER_B</scomRegister> + <scomRegister>PU_STATUS_REGISTER_B</scomRegister> + <scomRegister>PU_COMMAND_REGISTER_B</scomRegister> + <scomRegister>PU_MODE_REGISTER_B</scomRegister> + <scomRegister>PU_WATER_MARK_REGISTER_B</scomRegister> + <scomRegister>PU_INTERRUPT_MASK_REGISTER_READ_B</scomRegister> + <scomRegister>PU_INTERRUPT_COND_B</scomRegister> + <scomRegister>PU_INTERRUPTS_B</scomRegister> + <scomRegister>PU_STATUS_REGISTER_ENGINE_B</scomRegister> + <scomRegister>PU_EXTENDED_STATUS_B</scomRegister> + <scomRegister>PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B</scomRegister> + <scomRegister>PU_I2C_BUSY_REGISTER_B</scomRegister> + </registerFfdc> + <registerFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <scomRegister>PERV_OPCG_ALIGN</scomRegister> + <scomRegister>PERV_OPCG_REG0</scomRegister> + <scomRegister>PERV_OPCG_REG1</scomRegister> + <scomRegister>PERV_OPCG_REG2</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CC_STATUS_REGISTERS</id> + <scomRegister>PERV_SCAN_REGION_TYPE</scomRegister> + <scomRegister>PERV_CLK_REGION</scomRegister> + <scomRegister>PERV_CLOCK_STAT_SL</scomRegister> + <scomRegister>PERV_CLOCK_STAT_NSL</scomRegister> + <scomRegister>PERV_CLOCK_STAT_ARY</scomRegister> + <scomRegister>PERV_BIST</scomRegister> + </registerFfdc> + <registerFfdc> + <id>ERROR_STATUS_OF_CC</id> + <scomRegister>PERV_ERROR_STATUS</scomRegister> + </registerFfdc> + <registerFfdc> + <id>CC_REGISTERS</id> + <scomRegister>PERV_XSTOP1</scomRegister> + <scomRegister>PERV_XSTOP2</scomRegister> + <scomRegister>PERV_XSTOP3</scomRegister> + <scomRegister>PERV_OPCG_CAPT1</scomRegister> + <scomRegister>PERV_OPCG_CAPT2</scomRegister> + <scomRegister>PERV_OPCG_CAPT3</scomRegister> + <scomRegister>PERV_DBG_CBS_CC</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_ARY_ERR</rc> + <description>ary_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_ARY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NSL_ERR</rc> + <description>nsl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_NSL</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_SL_ERR</rc> + <description>sl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_SL</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_CPLT_NOT_ALIGNED_ERR</rc> + <description>Chiplet not aligned</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT0</ffdc> + <ffdc>LOOP_COUNT</ffdc> + <ffdc>HW_DELAY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc> + <description>Chiplet OPCG_DONE not set after clock start/stop command</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>PERV_CPLT_STAT0</ffdc> + <ffdc>LOOP_COUNT</ffdc> + <ffdc>HW_DELAY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NEST_ARY_ERR</rc> + <description>ary_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_ARY</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NEST_NSL_ERR</rc> + <description>nsl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_NSL</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_NEST_SL_ERR</rc> + <description>sl_thold status not matching the expected value in clock start stop sequence</description> + <ffdc>TARGET_CHIPLET</ffdc> + <collectRegisterFfdc> + <id>NET_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CPLT_CONFIG_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OTHER_CPLT_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>OPCG_CTRL_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_STATUS_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>ERROR_STATUS_OF_CC</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CC_REGISTERS</id> + <target>TARGET_CHIPLET</target> + <targetType>TARGET_TYPE_PERV</targetType> + </collectRegisterFfdc> + <ffdc>READ_CLK_SL</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> |
