diff options
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info')
3 files changed, 25 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 3f04745a..3d9b330c 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1844,10 +1844,10 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</id> + <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - DD1 only: leverage SS PLL to provide reduced frequency reference clock + DD1 only: enable use of SS PLL to provide reduced frequency reference clock (94 MHz, instead of nominal 100 MHz) for PCI PLL </description> <chipEcFeature> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 71f32599..7328a520 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -136,6 +136,24 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_DD1_SLOW_PCI_REF_CLOCK</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + MRW control to permit Normal (100 MHz) or Slow (94 MHz) operation + of PCIE reference clock. On Nimbus DD1 HW, Slow operation is required + to achieve Gen4 operation. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + NORMAL = 0x00, + SLOW = 0x01 + </enum> + <platInit/> + <writeable/> + </attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 0cfe4c8e..cb0eb8f2 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -354,10 +354,14 @@ attribute tank <virtual/> </entry> <entry> - <name>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</name> + <name>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE</name> <virtual/> </entry> <entry> + <name>ATTR_DD1_SLOW_PCI_REF_CLOCK</name> + <value>0x01</value> + </entry> + <entry> <name>ATTR_CHIP_EC_FEATURE_HW401184</name> <virtual/> </entry> |
