diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv')
84 files changed, 12083 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/Makefile b/src/import/chips/p9/procedures/hwp/perv/Makefile new file mode 100644 index 00000000..ac2ee6de --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/Makefile @@ -0,0 +1,55 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/perv/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the core hardware procedure code. See the +# "pervfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/perv +export SUB_OBJDIR = /perv + +include img_defs.mk +include pervfiles.mk + +GCC-CFLAGS += -mlongcall + +OBJS := $(addprefix $(OBJDIR)/, $(PERV_OBJECTS)) + +libperv.a: perv + $(AR) crs $(OBJDIR)/libperv.a $(OBJDIR)/*.o + +.PHONY: clean perv +perv: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C new file mode 100644 index 00000000..e850723f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C @@ -0,0 +1,173 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_dcc_skewadjust_setup.C +/// +/// @brief Drop DCCs reset and bypass, Drop skewadjust reset and bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE:SGPE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_hcd_cache_dcc_skewadjust_setup.H" +#include <p9_perv_scom_addresses.H> +#include <p9_quad_scom_addresses.H> + + + + +fapi2::ReturnCode p9_hcd_cache_dcc_skewadjust_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_cache) +{ + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = i_cache.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = i_cache.getParent<fapi2::TARGET_TYPE_PERV>(); + auto l_core_functional_vector = i_cache.getChildren<fapi2::TARGET_TYPE_CORE>(fapi2::TARGET_STATE_FUNCTIONAL); + uint8_t l_attr_chip_unit_pos = 0; + fapi2::buffer<uint64_t> l_data64; + + + FAPI_DBG("Entering ..."); + + FAPI_DBG("Release L2-0, L2-1 DC Adjust reset"); + l_data64.flush<1>(); + l_data64.clearBit<23>(); + l_data64.clearBit<24>(); + FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); + + for(auto it : l_core_functional_vector) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + it.getParent<fapi2::TARGET_TYPE_PERV>(), + l_attr_chip_unit_pos)); + + FAPI_DBG("Release CORE DC Adjust reset"); + l_data64.flush<1>(); + l_data64.clearBit<2>(); + FAPI_TRY(fapi2::putScom(l_chip, (C_NET_CTRL0_WAND + (0x1000000 * (l_attr_chip_unit_pos - 0x20))) , + l_data64)); + } + + FAPI_DBG("Scan eq_ana_bndy_bucket_0 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_0, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_0)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_1 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_1)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_2 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_2, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_2)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_3 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_3, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_3)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_4 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_4, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_4)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_5 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_5, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_5)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_6 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_6, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_6)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_7 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_7, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_7)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_8 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_8, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_8)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_9 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_9, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_9)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_10 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_10, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_10)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_11 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_11, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_11)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_12 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_12, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_12)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_13 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_13, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_13)"); + + FAPI_DBG("Release DCC bypass"); + l_data64.flush<1>(); + l_data64.clearBit<1>(); + FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_DBG("Scan eq_ana_bndy_bucket_14 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_14)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_15 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_15)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_16 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_16)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_17 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_17)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_18 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_18)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_19 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_19)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_20 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_20)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_21 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_21)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_22 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_22)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_23 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_23)"); + + FAPI_DBG("Release Progdly bypass"); + l_data64.flush<1>(); + l_data64.clearBit<2>(); + FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_DBG("Scan eq_ana_bndy_bucket_24 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_24)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_25 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_25)"); + + FAPI_DBG("Exiting ..."); +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H new file mode 100644 index 00000000..c6a0c6f2 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_dcc_skewadjust_setup.H +/// +/// @brief Drop DCCs reset and bypass, Drop skewadjust reset and bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_HCD_CACHE_DCC_SKEWADJUST_SETUP_H_ +#define _P9_HCD_CACHE_DCC_SKEWADJUST_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_hcd_cache_dcc_skewadjust_setup_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief * Start Clocks clock region = AN only +/// * Drop DCCs reset +/// Setup 6 DCCs in parallel (commands over scan with setpulse, scan region = ANEP) +/// * Drop DCCs bypass +/// * Additional DCC setup step (commands over scan with setpulse, scan region = ANEP) +/// * Drop SkewAdjust reset +/// * Setup Skewadjust (commands over scan with setpulse, scan region = ANEP) +/// * Drop SkewAdjust bypass +/// * Additional SkewAdjust setup step (commands over scan with setpulse, scan region = ANEP) +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_EQ target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_hcd_cache_dcc_skewadjust_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C new file mode 100644 index 00000000..364d4013 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C @@ -0,0 +1,479 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_perv_sbe_cmn.C +/// +/// @brief Modules for scan 0 and array init +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_perv_sbe_cmn.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_quad_scom_addresses_fld.H> +#include <p9_const_common.H> + + +enum P9_PERV_SBE_CMN_Private_Constants +{ + P9_OPCG_DONE_SCAN0_POLL_COUNT = 200, // Scan0 Poll count + P9_OPCG_DONE_SCAN0_HW_NS_DELAY = 16000, // unit is nano seconds [min : 8k cycles x 4 = 8000/2 x 4 = 16000 x 10(-9) = 16 us + // max : 8k cycles = (8000/25) x 10 (-6) = 320 us] + P9_OPCG_DONE_SCAN0_SIM_CYCLE_DELAY = 800000, // unit is cycles, to match the poll count change ( 10000 * 8 ) + P9_OPCG_DONE_ARRAYINIT_HW_NS_DELAY = 200000, // unit is nano seconds [min : 400k/2 = 200k ns = 200 us + // max : 200k /25 = 8000 us = 8 ms] + P9_OPCG_DONE_ARRAYINIT_POLL_COUNT = 400, // Arrayinit Poll count + P9_OPCG_DONE_ARRAYINIT_SIM_CYCLE_DELAY = 1120000 // unit is cycles,to match the poll count change ( 280000 * 4 ) +}; + +/// @brief Seeprom array Init Module +/// --ABISTCLK_MUXSEL +/// --ABIST modes +/// --Setup BIST regions +/// --Setup all Clock Regions and Types +/// --Setup: +/// - loopcount +/// - OPCG engine start ABIST +/// - run-N mode +/// --Setup IDLE count +/// --OPCG go +/// --Poll OPCG done bit to check for completeness +/// --Clear: +/// - loopcount +/// - OPCG engine start ABIST +/// - run-N mode +/// --Clear all Clock Regions and Types +/// --Clear ABISTCLK_MUXSEL +/// --Clear BIST register +/// +/// +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target Targets all chiplets +/// @param[in] i_regions select clk regions +/// @param[in] i_loop_counter loop count value to set opcg run-N mode +/// @param[in] i_select_sram select sram abist mode +/// @param[in] i_select_edram Set edram abist mode +/// @param[in] i_start_abist_match_value match setup idle count value +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint64_t> i_loop_counter, + const bool i_select_sram, + const bool i_select_edram, + const fapi2::buffer<uint64_t> i_start_abist_match_value) +{ + fapi2::buffer<uint16_t> l_scan_count; + fapi2::buffer<uint16_t> l_misr_a_value; + fapi2::buffer<uint16_t> l_misr_b_value; + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint64_t> l_read_reg; + bool l_abist_check = false; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + fapi2::buffer<uint64_t> l_data64_clk_region; + FAPI_INF("p9_perv_sbe_cmn_array_init_module: Entering ..."); + + i_regions.extractToRight<5, 11>(l_regions); + + FAPI_DBG("Drop vital fence (moved to arrayinit from sacn0 module)"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + //CPLT_CTRL1.TC_VITL_REGION_FENCE = 0 + l_data64.setBit<C_CPLT_CTRL1_TC_VITL_REGION_FENCE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_DBG("Setup ABISTMUX_SEL"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("setup ABIST modes , BIST REGIONS:%#018lX", i_regions); + //Setting BIST register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_BIST, l_data64)); + l_data64.clearBit<0>(); //BIST.TC_BIST_START_TEST_DC = 0 + //BIST.TC_SRAM_ABIST_MODE_DC = i_select_sram + l_data64.writeBit<PERV_1_BIST_TC_SRAM_ABIST_MODE_DC>(i_select_sram); + //BIST.TC_EDRAM_ABIST_MODE_DC = i_select_edram + l_data64.writeBit<PERV_1_BIST_TC_EDRAM_ABIST_MODE_DC>(i_select_edram); + l_data64.insertFromRight<4, 11>(l_regions); //BIST.BIST_ALL_UNITS = l_regions + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_BIST, l_data64)); + FAPI_DBG("l_data64 value:%#018lX", l_data64); + + FAPI_DBG("Setup all Clock Domains and Clock Types"); + //Setting CLK_REGION register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CLK_REGION, + l_data64_clk_region)); + //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions + l_data64_clk_region.insertFromRight<4, 11>(l_regions); + l_data64_clk_region.setBit<48, 3>(); //CLK_REGION.SEL_THOLD_ALL = 0b111 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, + l_data64_clk_region)); + + FAPI_DBG("Drop Region fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_DBG("Setup: loopcount , OPCG engine start ABIST, run-N mode"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.setBit<PERV_1_OPCG_REG0_RUNN_MODE>(); //OPCG_REG0.RUNN_MODE = 1 + l_data64.setBit<14>(); //OPCG_REG0.OPCG_STARTS_BIST = 1 + l_data64.insertFromRight<PERV_1_OPCG_REG0_LOOP_COUNT, PERV_1_OPCG_REG0_LOOP_COUNT_LEN>(( + uint64_t)(i_loop_counter)); //OPCG_REG0.LOOP_COUNT = i_loop_counter + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + i_start_abist_match_value.extractToRight<0, 12>(l_scan_count); + i_start_abist_match_value.extractToRight<12, 12>(l_misr_a_value); + i_start_abist_match_value.extractToRight<24, 12>(l_misr_b_value); + + FAPI_DBG("Setup IDLE count"); + //Setting OPCG_REG1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG1, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_REG1_SCAN_COUNT, PERV_1_OPCG_REG1_SCAN_COUNT_LEN> + (l_scan_count); //OPCG_REG1.SCAN_COUNT = l_scan_count + l_data64.insertFromRight<PERV_1_OPCG_REG1_MISR_A_VAL, PERV_1_OPCG_REG1_MISR_A_VAL_LEN> + (l_misr_a_value); //OPCG_REG1.MISR_A_VAL = l_misr_a_value + l_data64.insertFromRight<PERV_1_OPCG_REG1_MISR_B_VAL, PERV_1_OPCG_REG1_MISR_B_VAL_LEN> + (l_misr_b_value); //OPCG_REG1.MISR_B_VAL = l_misr_b_value + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG1, l_data64)); + + FAPI_DBG("opcg go"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.setBit<1>(); //OPCG_REG0.OPCG_GO = 1 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); + l_timeout = P9_OPCG_DONE_ARRAYINIT_POLL_COUNT; + + //UNTIL CPLT_STAT0.CC_CTRL_OPCG_DONE_DC == 1 + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_OPCG_DONE_DC + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(P9_OPCG_DONE_ARRAYINIT_HW_NS_DELAY, + P9_OPCG_DONE_ARRAYINIT_SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::SBE_ARRAYINIT_POLL_THRESHOLD_ERR(), + "ERROR:OPCG DONE BIT NOT SET"); + + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, + l_read_reg)); //l_read_reg = CPLT_STAT0 + + if ( i_select_sram ) + { + FAPI_DBG("Checking sram abist done"); + FAPI_ASSERT(l_read_reg.getBit<0>() == 1, + fapi2::SRAM_ABIST_DONE_BIT_ERR() + .set_READ_ABIST_DONE(l_abist_check), + "ERROR:SRAM_ABIST_DONE_BIT_NOT_SET"); + } + + if ( i_select_edram ) + { + FAPI_DBG("Checking edram abist done"); + FAPI_ASSERT(l_read_reg.getBit<1>() == 1, + fapi2::EDRAM_ABIST_DONE_BIT_ERR() + .set_READ_ABIST_DONE(l_abist_check), + "ERROR:EDRAM_ABIST_DONE_BIT_NOT_SET"); + } + + //oaim_poll_done + { + FAPI_DBG("OPCG done, clear Run-N mode"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.clearBit<PERV_1_OPCG_REG0_RUNN_MODE>(); //OPCG_REG0.RUNN_MODE = 0 + l_data64.clearBit<14>(); //OPCG_REG0.OPCG_STARTS_BIST = 0 + l_data64.clearBit<PERV_1_OPCG_REG0_LOOP_COUNT, PERV_1_OPCG_REG0_LOOP_COUNT_LEN>(); //OPCG_REG0.LOOP_COUNT = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("clear all clock REGIONS and type"); + //Setting CLK_REGION register value + //CLK_REGION = 0 + l_data64_clk_region = 0; //using variable to keep register data + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, + l_data64_clk_region)); + + FAPI_DBG("clear ABISTCLK_MUXSEL"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_DBG("clear BIST REGISTER"); + //Setting BIST register value + //BIST = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_BIST, 0)); + } + + FAPI_INF("p9_perv_sbe_cmn_array_init_module: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Region value settings +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target ATTR_PG of the corresponding chiplet +/// @param[in] i_regions_value regions except vital and pll +/// @param[out] o_regions_value regions value +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_16(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint16_t>& o_regions_value) +{ + fapi2::buffer<uint32_t> l_read_attr = 0; + fapi2::buffer<uint32_t> l_read_attr_invert = 0; + fapi2::buffer<uint32_t> l_read_attr_shift1_right = 0; + FAPI_INF("p9_perv_sbe_cmn_regions_setup_16: Entering ..."); + + FAPI_DBG("Reading ATTR_PG"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chip, l_read_attr)); + FAPI_DBG("ATTR_PG Value : %#018lX", l_read_attr); + + FAPI_DBG("i_regions_value input from calling function: %#018lX", + i_regions_value); + + if ( l_read_attr == 0x0 ) + { + o_regions_value = i_regions_value; + } + else + { + l_read_attr_invert = l_read_attr.invert(); + FAPI_DBG("ATTR_PG inverted: %#018lX", l_read_attr_invert); + l_read_attr_shift1_right = (l_read_attr_invert >> 1); + FAPI_DBG("ATTR_PG inverted and shifted right by 1 %#018lX", + l_read_attr_shift1_right); + + o_regions_value = (i_regions_value & l_read_attr_shift1_right); + } + + FAPI_INF("p9_perv_sbe_cmn_regions_setup_16: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Region value settings +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_regions_value regions except vital and pll +/// @param[out] o_regions_value Regions value +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_64(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint64_t>& o_regions_value) +{ + fapi2::buffer<uint32_t> l_read_attr = 0; + fapi2::buffer<uint32_t> l_read_attr_invert = 0; + fapi2::buffer<uint32_t> l_read_attr_shift1_right = 0; + fapi2::buffer<uint64_t> l_temp = 0; + FAPI_INF("p9_perv_sbe_cmn_regions_setup_64: Entering ..."); + + FAPI_DBG("Reading ATTR_PG"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_read_attr)); + FAPI_DBG("ATTR_PG Value : %#018lX", l_read_attr); + + FAPI_DBG("i_regions_value input from calling function: %#018lX", + i_regions_value); + + if ( l_read_attr == 0x0 ) + { + o_regions_value = (i_regions_value | l_temp); + } + else + { + l_read_attr_invert = l_read_attr.invert(); + FAPI_DBG("ATTR_PG inverted: %#018lX", l_read_attr_invert); + l_read_attr_shift1_right = (l_read_attr_invert >> 1); + FAPI_DBG("ATTR_PG inverted and shifted right by 1 %#018lX", + l_read_attr_shift1_right); + + o_regions_value = (i_regions_value & l_read_attr_shift1_right); + } + + FAPI_INF("p9_perv_sbe_cmn_regions_setup_64: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Seeprom scan0 module +/// --Raise VITAL clock region fence +/// --Write Clock Region Register +/// --Write Scan Select Register +/// --set OPCG_REG0 register bit 0='0' +/// --set OPCG_REG0 register bit 2 = '1' +/// --Poll OPCG done bit to check for scan0 completeness +/// --clear clock region register +/// --clear scan select register +/// --Drop VITAL fence +/// +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target Targets for all chiplets +/// @param[in] i_regions set the clk region +/// @param[in] i_scan_types set scan types region +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint16_t> i_scan_types) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint16_t> l_scan_types; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_perv_sbe_cmn_scan0_module: Entering ..."); + + i_regions.extractToRight<5, 11>(l_regions); + i_scan_types.extractToRight<4, 12>(l_scan_types); + + FAPI_DBG("raise Vital clock region fence"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + //CPLT_CTRL1.TC_VITL_REGION_FENCE = 1 + l_data64.setBit<C_CPLT_CTRL1_TC_VITL_REGION_FENCE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64)); + + FAPI_DBG("Raise region fences for scanned regions"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + l_data64.setBit<4, 11>(); //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = 0b11111111111 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64)); + + FAPI_DBG("Setup all Clock Domains and Clock Types"); + //Setting CLK_REGION register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CLK_REGION, l_data64)); + //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + l_data64.setBit<48, 3>(); //CLK_REGION.SEL_THOLD_ALL = 0b111 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, l_data64)); + + FAPI_DBG("Write scan select register"); + //Setting SCAN_REGION_TYPE register value + l_data64.flush<0>(); //SCAN_REGION_TYPE = 0 + //SCAN_REGION_TYPE.SCAN_REGION_ALL_UNITS = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + //SCAN_REGION_TYPE.SCAN_ALL_TYPES = l_scan_types + l_data64.insertFromRight<48, 12>(l_scan_types); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SCAN_REGION_TYPE, l_data64)); + + FAPI_DBG("set OPCG_REG0 register bit 0='0'"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.clearBit<PERV_1_OPCG_REG0_RUNN_MODE>(); //OPCG_REG0.RUNN_MODE = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("trigger Scan0"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.setBit<PERV_1_OPCG_REG0_RUN_SCAN0>(); //OPCG_REG0.RUN_SCAN0 = 1 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); + l_timeout = P9_OPCG_DONE_SCAN0_POLL_COUNT; + + //UNTIL CPLT_STAT0.CC_CTRL_OPCG_DONE_DC == 1 + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_OPCG_DONE_DC + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(P9_OPCG_DONE_SCAN0_HW_NS_DELAY, + P9_OPCG_DONE_SCAN0_SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::SBE_SCAN0_DONE_POLL_THRESHOLD_ERR(), + "ERROR:OPCG DONE BIT NOT SET"); + + //os0m_poll_done + { + FAPI_DBG("clear all clock REGIONS and type"); + //Setting CLK_REGION register value + //CLK_REGION = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, 0)); + + FAPI_DBG("Clear Scan Select Register"); + //Setting SCAN_REGION_TYPE register value + //SCAN_REGION_TYPE = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SCAN_REGION_TYPE, 0)); + } + + FAPI_INF("p9_perv_sbe_cmn_scan0_module: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H new file mode 100644 index 00000000..b2472eb3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_perv_sbe_cmn.H +/// +/// @brief Modules for scan 0 and array init +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_PERV_SBE_CMN_H_ +#define _P9_PERV_SBE_CMN_H_ + + +#include <fapi2.H> + + +fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint64_t> i_loop_counter, + const bool i_select_sram, + const bool i_select_edram, + const fapi2::buffer<uint64_t> i_start_abist_match_value); + +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_16(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint16_t>& o_regions_value); + +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_64(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint64_t>& o_regions_value); + +fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint16_t> i_scan_types); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C new file mode 100644 index 00000000..d11fe6bf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -0,0 +1,950 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_ram_core.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_core.C +/// @brief Class that implements the base ramming capability +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_core.H> +#include "p9_quad_scom_addresses.H" +#include "p9_quad_scom_addresses_fld.H" + +// identifiers for special registers +const uint32_t RAM_REG_NIA = 2000; +const uint32_t RAM_REG_MSR = 2001; +const uint32_t RAM_REG_CR = 2002; +const uint32_t RAM_REG_FPSCR = 2003; + +// opcode for ramming +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD = 0x7C1543A6; +const uint32_t OPCODE_MTSPR_FROM_GPR1_TO_SPRD = 0x7C3543A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR0 = 0x7C1542A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR1 = 0x7C3542A6; +const uint32_t OPCODE_MFSPR_FROM_SPR0_TO_GPR0 = 0x7C0002A6; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPR0 = 0x7C0003A6; +const uint32_t OPCODE_MFFPRD_FROM_FPR0_TO_GPR0 = 0x7C000066; +const uint32_t OPCODE_MTFPRD_FROM_GPR0_TO_FPR0 = 0x7C000166; +const uint32_t OPCODE_MFVSRD_FROM_VSR0_TO_GPR0 = 0x7C000066; +const uint32_t OPCODE_MFVSRD_FROM_VSR32_TO_GPR0 = 0x7C000067; +const uint32_t OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0 = 0x7C000266; +const uint32_t OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0 = 0x7C000267; +const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0 = 0x7C010366; +const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32 = 0x7C010367; +const uint32_t OPCODE_MFSPR_FROM_LR_TO_GPR0 = 0x7C0802A6; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_LR = 0x7C0803A6; +const uint32_t OPCODE_MTMSR_L0 = 0x7C000124; +const uint32_t OPCODE_MTMSRD_L0 = 0x7C000164; +const uint32_t OPCODE_MTSPR_IAMR = 0x7C1D0BA6; +const uint32_t OPCODE_MTSPR_PIDR = 0x7C100BA6; +const uint32_t OPCODE_MTSPR_LPIDR = 0x7C1F4BA6; +const uint32_t OPCODE_MTSPR_LPCR = 0x7C1E4BA6; +const uint32_t OPCODE_MTSPR_MMCRA = 0x7C12C3A6; +const uint32_t OPCODE_MTSPR_MMCR1 = 0x7C1EC3A6; +const uint32_t OPCODE_MTSPR_SEIDBAR = 0x7C1F7BA6; +const uint32_t OPCODE_MTSPR_XER = 0x7C0103A6; +const uint32_t OPCODE_MFSPR_XER = 0x7C0102A6; +const uint32_t OPCODE_MFFS = 0xFC00048E; +const uint32_t OPCODE_SLBMFEE = 0x7C000726; +const uint32_t OPCODE_SLBMFEV = 0x7C0006A6; +const uint32_t OPCODE_DCBZ = 0x7C0007EC; +const uint32_t OPCODE_DCBF = 0x7C0000AC; +const uint32_t OPCODE_LD = 0xE8000000; +const uint32_t OPCODE_STD = 0xF8000000; +const uint32_t OPCODE_LFD = 0xC8000000; +const uint32_t OPCODE_STFD = 0xD8000000; +const uint32_t OPCODE_LVX = 0x7C0000CE; +const uint32_t OPCODE_STVX = 0x7C0001CE; +const uint32_t OPCODE_LXVD2X = 0x7C000698; +const uint32_t OPCODE_STXVD2X = 0x7C000798; +const uint32_t OPCODE_MFMSR_TO_GPR0 = 0x7C0000A6; +const uint32_t OPCODE_MFCR_TO_GPR0 = 0x7C000026; +const uint32_t OPCODE_MTCRF_FROM_GPR0 = 0x7C0FF120; +const uint32_t OPCODE_MTFSF_FROM_GPR0 = 0xFE00058E; + +// TODO: make sure these special PPC are final version in PC workbook table 9-2 +const uint32_t OPCODE_MFNIA_RT = 0x001ac804; +const uint32_t OPCODE_MTNIA_LR = 0x4c1e00a4; +const uint32_t OPCODE_GPR_MOVE = 0x00000010; +const uint32_t OPCODE_VSR_MOVE_HI = 0x00000110; +const uint32_t OPCODE_VSR_MOVE_LO = 0x00000210; +const uint32_t OPCODE_XER_MOVE = 0x00000310; +const uint32_t OPCODE_CR_MOVE = 0x00000410; + +// poll count for check ram status +const uint32_t RAM_CORE_STAT_POLL_CNT = 10; + +// Scom register field +// TODO: replace the const with FLD macro define when it's ready +const uint32_t C_RAM_MODEREG_ENABLE = 0; +const uint32_t C_RAS_STATUS_CORE_MAINT = 0; +const uint32_t C_THREAD_INFO_VTID0_ACTIVE = 0; +const uint32_t C_RAM_CTRL_VTID = 0; +const uint32_t C_RAM_CTRL_VTID_LEN = 2; +const uint32_t C_RAM_CTRL_PREDECODE = 2; +const uint32_t C_RAM_CTRL_PREDECODE_LEN = 4; +const uint32_t C_RAM_CTRL_INSTRUCTION = 8; +const uint32_t C_RAM_CTRL_INSTRUCTION_LEN = 32; +const uint32_t C_RAM_STATUS_ACCESS_DURING_RECOVERY = 0; +const uint32_t C_RAM_STATUS_COMPLETION = 1; +const uint32_t C_RAM_STATUS_EXCEPTION = 2; +const uint32_t C_RAM_STATUS_LSU_EMPTY = 3; + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +RamCore::RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread) +{ + iv_target = i_target; + iv_thread = i_thread; + iv_ram_enable = false; + iv_ram_scr0_save = false; + iv_ram_setup = false; + iv_ram_err = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; + iv_backup_buf0 = 0; + iv_backup_buf1 = 0; + iv_backup_buf2 = 0; +} + +RamCore::~RamCore() +{ + if(iv_ram_setup) + { + FAPI_ERR("RamCore Destructor error: Ram is still in active state!!!"); + } +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_setup() +{ + FAPI_DBG("Start ram setup"); + fapi2::buffer<uint64_t> l_data = 0; + uint32_t l_opcode = 0; + bool l_thread_active = false; + uint8_t l_thread_stop = 0; + + // set RAM_MODEREG Scom to enable RAM mode + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data)); + l_data.setBit<C_RAM_MODEREG_ENABLE>(); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); + + // read RAS_STATUS Scom to check the thread is stopped for ramming + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_RAS_STATUS, l_data)); + FAPI_DBG("RAS_STATUS:%#lx", l_data()); + FAPI_TRY(l_data.extractToRight(l_thread_stop, C_RAS_STATUS_CORE_MAINT + 8 * iv_thread, 2)); + + FAPI_ASSERT(l_thread_stop == 3, + fapi2::P9_RAM_THREAD_NOT_STOP_ERR() + .set_THREAD(iv_thread), + "Thread to perform ram is not stopped"); + + // read THREAD_INFO Scom to check the thread is active for ramming + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_THREAD_INFO, l_data)); + FAPI_DBG("THREAD_INFO:%#lx", l_data()); + FAPI_TRY(l_data.extractToRight(l_thread_active, C_THREAD_INFO_VTID0_ACTIVE + iv_thread, 1)); + + FAPI_ASSERT(l_thread_active, + fapi2::P9_RAM_THREAD_INACTIVE_ERR() + .set_THREAD(iv_thread), + "Thread to perform ram is inactive"); + + iv_ram_enable = true; + + // backup registers SCR0/GPR0/GPR1/LR + //SCR0->iv_backup_buf0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf0)); + iv_ram_scr0_save = true; + + //GPR0->iv_backup_buf1 + //1.setup SPRC to use SCRO as SPRD + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + //2.create mtsprd<gpr0> opcode, ram into thread to get GPR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR0 from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf1)); + + //GPR1->iv_backup_buf2 + //1.create mtsprd<gpr1> opcode, ram into thread to get GPR1 + l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get GPR1 from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf2)); + + iv_ram_setup = true; + +fapi_try_exit: + + // Error happened and SCR0 saved, to restore SCR0 + // Do not use "FAPI_TRY" to avoid endless loop + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && iv_ram_scr0_save) + { + fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0); + } + + FAPI_DBG("Exiting ram setup"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_cleanup() +{ + FAPI_DBG("Start ram cleanup"); + uint32_t l_opcode = 0; + fapi2::buffer<uint64_t> l_data = 0; + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to cleanup ram without setup before"); + + // setup SPRC to use SCRO as SPRD + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + // restore GPR1 + if(!iv_write_gpr1) + { + //iv_backup_buf2->GPR1 + //1.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf2)); + + //2.create mfsprd<gpr1> opcode, ram into thread to restore GPR1 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + + // restore GPR0 + if(!iv_write_gpr0) + { + //iv_backup_buf1->GPR0 + //1.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf1)); + + //2.create mfsprd<gpr0> opcode, ram into thread to restore GPR0 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + + //iv_backup_buf0->SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); + + // set RAM_MODEREG Scom to clear RAM mode + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data)); + l_data.clearBit<C_RAM_MODEREG_ENABLE>(); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); + + iv_ram_enable = false; + iv_ram_scr0_save = false; + iv_ram_setup = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; + +fapi_try_exit: + FAPI_DBG("Exiting ram cleanup"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_opcode(const uint32_t i_opcode, const bool i_allow_mult) +{ + FAPI_DBG("Start ram opcode"); + fapi2::buffer<uint64_t> l_data = 0; + uint8_t l_predecode = 0; + uint32_t l_poll_count = RAM_CORE_STAT_POLL_CNT; + bool l_is_load_store = false; + + // check the opcode for load/store + l_is_load_store = is_load_store(i_opcode); + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_enable, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to ram opcode without enable RAM mode before"); + + // write RAM_CTRL Scom for ramming the opcode + l_data.insertFromRight<C_RAM_CTRL_VTID, C_RAM_CTRL_VTID_LEN>(iv_thread); + l_predecode = gen_predecode(i_opcode); + l_data.insertFromRight<C_RAM_CTRL_PREDECODE, C_RAM_CTRL_PREDECODE_LEN>(l_predecode); + l_data.insertFromRight<C_RAM_CTRL_INSTRUCTION, C_RAM_CTRL_INSTRUCTION_LEN>(i_opcode); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_CTRL, l_data)); + + // poll RAM_STATUS_REG Scom for the completion + l_data.flush<0>(); + + while(1) + { + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_STATUS, l_data)); + + // attempting to ram during recovery + FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_ACCESS_DURING_RECOVERY>(), + fapi2::P9_RAM_STATUS_IN_RECOVERY_ERR(), + "Attempting to ram during recovery"); + + // exception or interrupt + FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_EXCEPTION>(), + fapi2::P9_RAM_STATUS_EXCEPTION_ERR(), + "Exception or interrupt happened during ramming"); + + // load/store opcode need to check LSU empty and PPC complete + if (l_is_load_store) + { + if(l_data.getBit<C_RAM_STATUS_COMPLETION>() && l_data.getBit<C_RAM_STATUS_LSU_EMPTY>()) + { + FAPI_DBG("ram_opcode:: RAM is done"); + break; + } + } + else + { + if(l_data.getBit<C_RAM_STATUS_COMPLETION>()) + { + FAPI_DBG("ram_opcode:: RAM is done"); + break; + } + } + + --l_poll_count; + + FAPI_ASSERT(l_poll_count > 0, + fapi2::P9_RAM_STATUS_POLL_THRESHOLD_ERR(), + "Timeout for ram to complete, poll count expired"); + } + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + + if(fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) + { + iv_ram_err = true; + } + + FAPI_DBG("Exiting ram opcode"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +uint8_t RamCore::gen_predecode(const uint32_t i_opcode) +{ + //TODO: make sure they are final version in PC workbook table 9-1 and 9-2 + uint8_t l_predecode = 0; + uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE; + uint32_t l_opcode_pattern1 = i_opcode & 0xFC1FFFFE; + + if((i_opcode == OPCODE_MFNIA_RT) || + (i_opcode == OPCODE_GPR_MOVE) || + (i_opcode == OPCODE_VSR_MOVE_HI) || + (i_opcode == OPCODE_VSR_MOVE_LO) || + (i_opcode == OPCODE_XER_MOVE) || + (i_opcode == OPCODE_CR_MOVE)) + { + l_predecode = 2; + } + else if((i_opcode == OPCODE_MTNIA_LR) || + (l_opcode_pattern0 == OPCODE_MTMSR_L0) || + (l_opcode_pattern0 == OPCODE_MTMSRD_L0)) + { + l_predecode = 8; + } + else if((l_opcode_pattern1 == OPCODE_MTSPR_IAMR) || + (l_opcode_pattern1 == OPCODE_MTSPR_PIDR) || + (l_opcode_pattern1 == OPCODE_MTSPR_LPIDR) || + (l_opcode_pattern1 == OPCODE_MTSPR_LPCR) || + (l_opcode_pattern1 == OPCODE_MTSPR_MMCRA) || + (l_opcode_pattern1 == OPCODE_MTSPR_MMCR1) || + (l_opcode_pattern1 == OPCODE_MTSPR_SEIDBAR) || + (l_opcode_pattern1 == OPCODE_MTSPR_XER) || + (l_opcode_pattern1 == OPCODE_MFSPR_XER) || + (l_opcode_pattern0 == OPCODE_MFFS) || + (l_opcode_pattern0 == OPCODE_SLBMFEE) || + (l_opcode_pattern0 == OPCODE_SLBMFEV)) + { + l_predecode = 4; + } + + return l_predecode; +} + +//----------------------------------------------------------------------------------- +bool RamCore::is_load_store(const uint32_t i_opcode) +{ + //TODO: make sure they are final version in PC workbook table 9-1 + bool l_load_store = false; + uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE; + uint32_t l_opcode_pattern1 = i_opcode & 0xFC000000; + + if((l_opcode_pattern0 == OPCODE_DCBZ) || + (l_opcode_pattern0 == OPCODE_DCBF) || + (l_opcode_pattern1 == OPCODE_LD) || + (l_opcode_pattern1 == OPCODE_LFD) || + (l_opcode_pattern1 == OPCODE_STD) || + (l_opcode_pattern1 == OPCODE_LFD) || + (l_opcode_pattern1 == OPCODE_STFD) || + (l_opcode_pattern0 == OPCODE_LVX) || + (l_opcode_pattern0 == OPCODE_STVX) || + (l_opcode_pattern0 == OPCODE_LXVD2X) || + (l_opcode_pattern0 == OPCODE_STXVD2X)) + { + l_load_store = true; + } + + return l_load_store; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, + fapi2::buffer<uint64_t>* o_buffer, const bool i_allow_mult) +{ + FAPI_DBG("Start get register"); + uint32_t l_opcode = 0; + uint32_t l_spr_regnum_lo = 0; + uint32_t l_spr_regnum_hi = 0; + fapi2::buffer<uint64_t> l_backup_gpr0 = 0; + fapi2::buffer<uint64_t> l_backup_fpr0 = 0; + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to get register without setup before"); + + //backup GPR0 if it is written + if(iv_write_gpr0) + { + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0)); + } + + // get register value + if(i_type == REG_GPR) + { + //1.create mtsprd<i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_type == REG_SPR) + { + if(i_reg_num == RAM_REG_NIA) + { + //1.ram MFNIA_RT opcode + l_opcode = OPCODE_MFNIA_RT; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get NIA from GPR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_MSR) + { + //1.create mfmsr opcode, ram into thread + l_opcode = OPCODE_MFMSR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get MSR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_CR) + { + //1.create mfcr opcode, ram into thread + l_opcode = OPCODE_MFCR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get MSR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_FPSCR) + { + //1.backup FPR0 + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0)); + + //2.create mffs opcode, ram into thread + l_opcode = OPCODE_MFFS; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get FPSCR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + + //4.restore FPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else + { + //1.create mfspr<gpr0, i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPR0_TO_GPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 6); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + } + else if(i_type == REG_FPR) + { + //1.create mffprd<gpr0, i_reg_num>#SX=0 opcode, ram into thread + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + +#ifndef __PPE__ + else if(i_type == REG_VSR) + { + //1.create mfvsrd<gpr0, i_reg_num> opcode, ram into thread to get dw0 + if(i_reg_num < 32) + { + l_opcode = OPCODE_MFVSRD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MFVSRD_FROM_VSR32_TO_GPR0; + l_opcode += ((i_reg_num - 32) << 21); + } + + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get VSR dw0 value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + + //4.create mfvrld<gpr0, i_reg_num> opcode, ram into thread to get dw1 + if(i_reg_num < 32) + { + l_opcode = OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0; + l_opcode += ((i_reg_num - 32) << 21); + } + + FAPI_TRY(ram_opcode(l_opcode, true)); + + //5.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //6.get VSR dw1 value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[1])); + } + +#endif + else + { + FAPI_ASSERT(false, + fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR() + .set_REGTYPE(i_type), + "Type of reg is not supported"); + } + + //restore GPR0 if necessary + if(iv_write_gpr0) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + // Error happened and it's not ram error, call ram_cleanup to restore the backup registers + // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed + // Do not use "FAPI_TRY" to avoid endless loop + fapi2::ReturnCode first_err = fapi2::current_err; + + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup) + { + ram_cleanup(); + } + + FAPI_DBG("Exiting get register"); + return first_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, + const fapi2::buffer<uint64_t>* i_buffer, const bool i_allow_mult) +{ + FAPI_DBG("Start put register"); + uint32_t l_opcode = 0; + uint32_t l_spr_regnum_lo = 0; + uint32_t l_spr_regnum_hi = 0; + bool l_write_gpr0 = false; + fapi2::buffer<uint64_t> l_backup_lr = 0; + fapi2::buffer<uint64_t> l_backup_gpr0 = 0; + fapi2::buffer<uint64_t> l_backup_gpr1 = 0; + fapi2::buffer<uint64_t> l_backup_fpr0 = 0; + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to put register without setup before"); + + //backup GPR0 if it is written + if(iv_write_gpr0) + { + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0)); + } + +#ifndef __PPE__ + + //backup GPR1 if it is written + if(iv_write_gpr1 && (i_type == REG_VSR)) + { + l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr1)); + } + +#endif + + // put register value + if(i_type == REG_GPR) + { + //1.put GPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + if(i_reg_num == 0) + { + iv_write_gpr0 = true; + l_write_gpr0 = true; + } + + if(i_reg_num == 1) + { + iv_write_gpr1 = true; + } + } + else if(i_type == REG_SPR) + { + if(i_reg_num == RAM_REG_NIA) + { + //1.backup LR + l_opcode = OPCODE_MFSPR_FROM_LR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_lr)); + + //2.put NIA value into LR + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.ram MTNIA_LR opcode + l_opcode = OPCODE_MTNIA_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //4.restore LR + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_lr)); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_MSR) + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtmsrd opcode, ram into thread + l_opcode = OPCODE_MTMSRD_L0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_CR) + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtcrf opcode, ram into thread + l_opcode = OPCODE_MTCRF_FROM_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_FPSCR) + { + //1.backup FPR0 + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0)); + + //2.put SPR value into GPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtfsf opcode, ram into thread + l_opcode = OPCODE_MTFSF_FROM_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //4.restore FPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtspr<i_reg_num, gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 6); + FAPI_TRY(ram_opcode(l_opcode, true)); + } + } + else if(i_type == REG_FPR) + { + //1.put FPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtfprd<i_reg_num, gpr0>#TX=0 opcode, ram into thread + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#ifndef __PPE__ + else if(i_type == REG_VSR) + { + //1.put VSR dw1 value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[1])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.put VSR dw0 value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //4.create mfsprd<gpr1> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + l_opcode += (1 << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //5.create mtvsrdd<i_reg_num, gpr0, gpr1> opcode, ram into thread + if(i_reg_num < 32) + { + l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32; + l_opcode += ((i_reg_num - 32) << 21); + } + + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#endif + else + { + FAPI_ASSERT(false, + fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR() + .set_REGTYPE(i_type), + "Type of reg is not supported"); + } + + //restore GPR0 if necessary + if(iv_write_gpr0 && !l_write_gpr0) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#ifndef __PPE__ + + //restore GPR1 if necessary + if(iv_write_gpr1 && (i_type == REG_VSR)) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr1)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#endif + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + // Error happened and it's not ram error, call ram_cleanup to restore the backup registers + // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed + // Do not use "FAPI_TRY" to avoid endless loop + fapi2::ReturnCode first_err = fapi2::current_err; + + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup) + { + ram_cleanup(); + } + + FAPI_DBG("Exiting put register"); + return first_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H new file mode 100644 index 00000000..46f0eaf7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H @@ -0,0 +1,153 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_ram_core.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_core.H +/// @brief Class that implements the base ramming capability +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_CORE_H_ +#define _P9_RAM_CORE_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- +// register access type +enum Enum_RegType +{ + REG_GPR, + REG_SPR, + REG_FPR, + REG_VSR +}; + + +class RamCore +{ + public: +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Constructor of the class that implements the base ramming capability +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +// + RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread); + +//----------------------------------------------------------------------------------- +/// @brief Destructor of the class that implements the base ramming capability +// + ~RamCore(); + +//----------------------------------------------------------------------------------- +/// @brief Enable RAM mode and backup the registers(SCR0/GPR0/GPR1) that will be destroyed later during ramming +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_setup(); + +//----------------------------------------------------------------------------------- +/// @brief Perform the ram and check ram is done +/// @param[in] i_opcode => opcode to ram +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_opcode(const uint32_t i_opcode, const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Clear RAM mode and restore the backup registers +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_cleanup(); + +//----------------------------------------------------------------------------------- +/// @brief Get a register value by ramming +/// @param[in] i_type => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register nubmer +/// @param[out] o_buffer => register value +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, fapi2::buffer<uint64_t>* o_buffer, + const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Put a register value by ramming +/// @param[in] i_type => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register nubmer +/// @param[in] i_buffer => register value +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, const fapi2::buffer<uint64_t>* i_buffer, + const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Generate predecode for the opcode to ramming +/// @param[in] i_opcode => opcode to ram +/// @return the predecode +// + uint8_t gen_predecode(const uint32_t i_opcode); + +//----------------------------------------------------------------------------------- +/// @brief Check the opcode is load/store or not +/// @param[in] i_opcode => opcode to ram +/// @return TRUE if it is load/store +// + bool is_load_store(const uint32_t i_opcode); + + private: + fapi2::Target<fapi2::TARGET_TYPE_CORE> iv_target; // core target + uint8_t iv_thread; // thread number + bool iv_ram_enable; // ram mode is enabled + bool iv_ram_scr0_save; // SCR0 is saved when setup + bool iv_ram_setup; // ram mode is enabled and register backup is done + bool iv_ram_err; // error happened during ram + bool iv_write_gpr0; // putGPR0 operation is executed + bool iv_write_gpr1; // putGPR1 operatoin is executed + fapi2::buffer<uint64_t> iv_backup_buf0; // register backup data + fapi2::buffer<uint64_t> iv_backup_buf1; // register backup data + fapi2::buffer<uint64_t> iv_backup_buf2; // register backup data +}; + +#endif //_P9_RAM_CORE_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C new file mode 100644 index 00000000..79046f0e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C @@ -0,0 +1,185 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_arrayinit.C +/// +/// @brief array init procedure to be called with any chiplet target except TP,EP,EC +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_arrayinit.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +enum P9_SBE_ARRAYINIT_Private_Constants +{ + LOOP_COUNTER = 0x0000000000042FFF, + REGIONS_EXCEPT_VITAL_AND_PLL = 0x7FE, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCF, + SELECT_EDRAM = 0x0, + SELECT_SRAM = 0x1, + START_ABIST_MATCH_VALUE = 0x0000000F00000000 +}; + +static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions); + +static fapi2::ReturnCode p9_sbe_arrayinit_sdisn_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set); + +fapi2::ReturnCode p9_sbe_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint32_t> l_attr_pg; + fapi2::buffer<uint8_t> l_attr_read; + FAPI_INF("p9_sbe_arrayinit: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read)); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("set sdis_n"); + FAPI_TRY(p9_sbe_arrayinit_sdisn_setup(l_chplt_trgt, l_attr_read, true)); + + FAPI_DBG("Region setup"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_chplt_trgt, + REGIONS_EXCEPT_VITAL_AND_PLL, l_regions)); + FAPI_DBG("l_regions value: %#018lX ", l_regions); + + FAPI_DBG("Call proc_sbe_arryinit_scan0_and_arrayinit_module_function"); + FAPI_TRY(p9_sbe_arrayinit_scan0_and_arrayinit_module_function(l_chplt_trgt, + l_regions)); + + FAPI_DBG("clear sdis_n"); + FAPI_TRY(p9_sbe_arrayinit_sdisn_setup(l_chplt_trgt, l_attr_read, false)); + } + + FAPI_INF("p9_sbe_arrayinit: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --Run arrayinit on all enabled chiplets +/// --Scan flush 0 to all rings except GPTR, Time, Repair on all enabled chiplets +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_regions region value settings +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_arrayinit_scan0_and_arrayinit_module_function: Entering ..."); + + FAPI_DBG("Check for chiplet enable"); + //Getting NET_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); + //l_read_reg = NET_CTRL0.CHIPLET_ENABLE + l_read_reg = l_data64.getBit<PERV_1_NET_CTRL0_CHIPLET_ENABLE>(); + + if ( l_read_reg ) + { + FAPI_DBG("run array_init module for all chiplet except TP, EC, EP"); + FAPI_TRY(p9_perv_sbe_cmn_array_init_module(i_target_chiplet, i_regions, + LOOP_COUNTER, SELECT_SRAM, SELECT_EDRAM, START_ABIST_MATCH_VALUE)); + + FAPI_DBG("run scan0 module for region except vital and pll, scan types except GPTR TIME REPR all chiplets except TP, EC, EP"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, i_regions, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + } + + FAPI_INF("p9_sbe_arrayinit_scan0_and_arrayinit_module_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Sdis_n setup +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr Attribute to decide the sdis setup +/// @param[in] i_set set or clear the LCBES condition +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_arrayinit_sdisn_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_arrayinit_sdisn_setup: Entering ..."); + + if ( i_attr ) + { + if ( i_set ) + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 1 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_OR, l_data64)); + } + else + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 0 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_CLEAR, l_data64)); + } + } + + FAPI_INF("p9_sbe_arrayinit_sdisn_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H new file mode 100644 index 00000000..9fc72c1b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_arrayinit.H +/// +/// @brief array init procedure to be called with any chiplet target except TP,EP,EC +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ARRAYINIT_H_ +#define _P9_SBE_ARRAYINIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_arrayinit_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Array Init function call for any chiplet Target except TP,EP,EC +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C new file mode 100644 index 00000000..ee741b8c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -0,0 +1,244 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_attr_setup.C +/// +/// @brief Read scratch Regs, update ATTR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_attr_setup.H" + +#include <p9_perv_scom_addresses.H> + +fapi2::ReturnCode p9_sbe_attr_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_scratch_reg = 0; + fapi2::buffer<uint64_t> l_read_scratch8 = 0; + fapi2::buffer<uint8_t> l_read_1 = 0; + fapi2::buffer<uint8_t> l_read_2 = 0; + fapi2::buffer<uint8_t> l_read_3 = 0; + fapi2::buffer<uint16_t> l_read_4 = 0; + fapi2::buffer<uint32_t> l_read_5 = 0; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::buffer<uint64_t> l_data64; + bool sbe_slave_chip = false; + fapi2::buffer<uint64_t> l_read_device_reg = 0; + FAPI_INF("p9_sbe_attr_setup: Entering ..."); + + FAPI_DBG("Read Scratch8 for validity of Scratch register"); + //Getting SCRATCH_REGISTER_8 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_8_SCOM, + l_read_scratch8)); //l_read_scratch8 = PIB.SCRATCH_REGISTER_8 + + //set_security_acess + { + fapi2::buffer<uint64_t> l_read_reg; + + FAPI_DBG("Reading ATTR_SECURITY_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECURITY_MODE, FAPI_SYSTEM, l_read_1)); + + if ( l_read_1.getBit<7>() == 0 ) + { + FAPI_DBG("Clear Security Access Bit"); + //Setting CBS_CS register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64)); + l_data64.clearBit<4>(); //PIB.CBS_CS.CBS_CS_SECURE_ACCESS_BIT = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64)); + } + + //Getting CBS_CS register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, + l_read_reg)); //l_read_reg = PIB.CBS_CS + + l_read_1 = 0; + l_read_1.writeBit<7>(l_read_reg.getBit<4>()); + + FAPI_DBG("Setting ATTR_SECURITY_ENABLE with the SAB state"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURITY_ENABLE, FAPI_SYSTEM, l_read_1)); + + } + //read_scratch1_reg + { + if ( l_read_scratch8.getBit<0>() ) + { + FAPI_DBG("Reading Scratch_reg1"); + //Getting SCRATCH_REGISTER_1 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_1 + + l_read_scratch_reg.extract<0, 6>(l_read_1); + l_read_scratch_reg.extract<8, 24>(l_read_5); + + FAPI_DBG("Setting up ATTR_EQ_GARD, ATTR_EC_GARD"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5)); + + l_read_1 = 0; + l_read_4 = 0; + } + } + //read_scratch2_reg + { + if ( l_read_scratch8.getBit<1>() ) + { + FAPI_DBG("Reading Scratch_reg2"); + //Getting SCRATCH_REGISTER_2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2 + + l_read_scratch_reg.extractToRight<0, 16>(l_read_4); + + FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); + } + } + + //read_scratch4_reg + { + if ( l_read_scratch8.getBit<3>() ) + { + FAPI_DBG("Reading Scratch_Reg4"); + //Getting SCRATCH_REGISTER_4 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_4 + + l_read_scratch_reg.extractToRight<0, 16>(l_read_4); + l_read_scratch_reg.extractToRight<24, 8>(l_read_1); + + FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); + + l_read_1 = 0; + l_read_4 = 0; + } + } + //read_scratch5_reg + { + if ( l_read_scratch8.getBit<4>() ) + { + FAPI_DBG("Reading Scratch_reg5"); + //Getting SCRATCH_REGISTER_5 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_5_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_5 + + if (l_read_scratch_reg.getBit<0>()) + { + l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED; + } + else + { + l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL; + } + + l_read_2.writeBit<7>(l_read_scratch_reg.getBit<1>()); + + if (l_read_scratch_reg.getBit<2>()) + { + l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE; + } + else + { + l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE; + } + + FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, + l_read_2)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_3)); + + l_read_1 = 0; + l_read_2 = 0; + l_read_3 = 0; + + if (l_read_scratch_reg.getBit<3>()) + { + l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE; + } + else + { + l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE; + } + + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, + l_read_1)); + + l_read_1 = 0; + } + } + //read_scratch6_reg + { + if ( l_read_scratch8.getBit<5>() ) + { + FAPI_DBG("Reading Scratch_reg6"); + //Getting SCRATCH_REGISTER_6 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_6 + + l_read_1 = 0; + sbe_slave_chip = l_read_scratch_reg.getBit<24>(); + + if ( !sbe_slave_chip ) // 0b0 == master + { + FAPI_DBG("Reading DEVICE_ID_REG value"); + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_DEVICE_ID_REG, l_read_device_reg)); + + if (!l_read_device_reg.getBit<40>()) + { + l_read_1.setBit<7>(); + } + } + + l_read_scratch_reg.extractToRight<26, 3>(l_read_2); + l_read_scratch_reg.extractToRight<29, 3>(l_read_3); + + FAPI_DBG("Setting up MASTER_CHIP, FABRIC_GROUP_ID and CHIP_ID"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip, + l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip, + l_read_2)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip, + l_read_3)); + + } + } + + FAPI_INF("p9_sbe_attr_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H new file mode 100644 index 00000000..0a5e2a09 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_attr_setup.H +/// +/// @brief Read scratch Regs, update ATTR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ATTR_SETUP_H_ +#define _P9_SBE_ATTR_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_attr_setup_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief HWP will read the contents of Byte 0 of scratch register 8 indicates validity of mailbox register +/// and call FAPI2 APIs to set the values into the corresponding platform ATTR +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_attr_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C new file mode 100644 index 00000000..1cd61c93 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master.C +/// +/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_check_master.H" +fapi2::ReturnCode p9_sbe_check_master(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_check_master: Entering ..."); + + FAPI_DBG("p9_sbe_check_master: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H new file mode 100644 index 00000000..88c3bf21 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master.H +/// +/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHECK_MASTER_H_ +#define _P9_SBE_CHECK_MASTER_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_check_master_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief If master continue, else enable runtime chipOps +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_check_master(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C new file mode 100644 index 00000000..4d28bdbd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C @@ -0,0 +1,134 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_check_master_stop15.H +/// @brief Check if the targeted core (master) is fully in STOP15 +/// +// *HWP HWP Owner : Greg Still <stillgsg@us.ibm.com> +// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : SBE +/// +/// High-level procedure flow: +/// @verbatim +/// - Read the STOP History Register from the target core +/// - Return SUCCESS if:: +/// - STOP_GATED is set (indicating it is stopped) +/// - STOP_TRANSITION is clear (indicating it is stable) +/// - ACT_STOP_LEVEL is at the appropriate value (either 11 (0xB) or 15 (0x15) +/// - Return PENDING if +/// - STOP_TRANSITION is set (indicating transtion is progress) +/// - Return ERROR if +/// - STOP_GATED is set, STOP_TRANSITION is clear and ACT_STOP_LEVEL is not +/// appropriate +/// - STOP_TRANSITION is clear but STOP_GATED is clear +/// - Hardware access errors +/// @endverbatim + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- +#include <p9_sbe_check_master_stop15.H> +#include <p9_pm_stop_history.H> +#include <p9_quad_scom_addresses.H> + +// ----------------------------------------------------------------------------- +// Function definitions +// ----------------------------------------------------------------------------- + +// See .H for documentation +fapi2::ReturnCode p9_sbe_check_master_stop15( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_IMP("> p9_sbe_check_master_stop15"); + + fapi2::buffer<uint64_t> l_data64; + uint32_t l_stop_gated = 0; + uint32_t l_stop_transition = p9ssh::SSH_UNDEFINED; + uint32_t l_stop_requested_level = 0; // Running Level + uint32_t l_stop_actual_level = 0; // Running Level + + // Read the "Other" STOP History Register + FAPI_TRY(fapi2::getScom(i_target, C_PPM_SSHOTR, l_data64)); + + // Extract the field values + l_data64.extractToRight<p9ssh::STOP_GATED_START, + p9ssh::STOP_GATED_LEN>(l_stop_gated); + + l_data64.extractToRight<p9ssh::STOP_TRANSITION_START, + p9ssh::STOP_TRANSITION_LEN>(l_stop_transition); + + // Testing showed the above operation was sign extending into + // the l_stop_transition variable. + l_stop_transition &= 0x3; + + l_data64.extractToRight<p9ssh::STOP_REQUESTED_LEVEL_START, + p9ssh::STOP_REQUESTED_LEVEL_LEN>(l_stop_requested_level); + + l_data64.extractToRight<p9ssh::STOP_ACTUAL_LEVEL_START, + p9ssh::STOP_ACTUAL_LEVEL_LEN>(l_stop_actual_level); + +#ifndef __PPE__ + FAPI_DBG("GATED = %d; TRANSITION = %d (0x%X); REQUESTED_LEVEL = %d; ACTUAL_LEVEL = %d", + l_stop_gated, + l_stop_transition, l_stop_transition, + l_stop_requested_level, + l_stop_actual_level); +#endif + + // Check for valide reguest level + FAPI_ASSERT((l_stop_requested_level == 11 || l_stop_requested_level == 15), + fapi2::CHECK_MASTER_STOP15_INVALID_REQUEST_LEVEL() + .set_REQUESTED_LEVEL(l_stop_requested_level), + "Invalid requested STOP Level"); + + // Check for valid pending condition + FAPI_ASSERT(!(l_stop_transition == p9ssh::SSH_CORE_COMPLETE || + l_stop_transition == p9ssh::SSH_ENTERING ), + fapi2::CHECK_MASTER_STOP15_PENDING(), + "STOP 15 is still pending"); + + // Assert completion and the core gated condition. If not, something is off. + FAPI_ASSERT((l_stop_transition == p9ssh::SSH_COMPLETE && + l_stop_gated == p9ssh::SSH_GATED ), + fapi2::CHECK_MASTER_STOP15_INVALID_STATE() + .set_STOP_HISTORY(l_data64), + "STOP 15 error"); + + // Check for valid actual level + FAPI_ASSERT((l_stop_actual_level == 11 || l_stop_actual_level == 15), + fapi2::CHECK_MASTER_STOP15_INVALID_ACTUAL_LEVEL() + .set_ACTUAL_LEVEL(l_stop_actual_level), + "Invalid actual STOP Level"); + + FAPI_INF("SUCCESS!! Valid STOP entry state has been achieved.") + +fapi_try_exit: + FAPI_INF("< p9_sbe_check_master_stop15"); + + return fapi2::current_err; +} // END p9_sbe_check_master_stop15 + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H new file mode 100644 index 00000000..575536d9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master_stop15.H +/// +///------------------------------------------------------------------------------ +// *HWP HWP Owner : Greg Still <stillgsg@us.ibm.com> +// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHECK_MASTER_STOP15_H_ +#define _P9_SBE_CHECK_MASTER_STOP15_H_ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_sbe_check_master_stop15_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Check if the targeted core (master) is fully in STOP15 +/// +/// @param[in] i_target Reference to TARGET_TYPE_CORE target +/// +/// @return FAPI2_RC_SUCCESS if success +/// @return STOP15_PENDING STOP 15 not reached, but no error +/// HW state (still in progress) +/// @return Others indicate hardware failur +/// +extern "C" +{ + fapi2::ReturnCode + p9_sbe_check_master_stop15( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); +} + +#endif // _P9_SBE_CHECK_MASTER_STOP15_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C new file mode 100644 index 00000000..521078bd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C @@ -0,0 +1,70 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_init.C +/// +/// @brief init procedure for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_init.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_chiplet_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_init: Entering.."); + + FAPI_DBG("Check for XSTOP Bit"); + //Getting INTERRUPT_TYPE_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, l_data64)); + //l_read_reg = PIB.INTERRUPT_TYPE_REG.CHECKSTOP + l_read_reg = l_data64.getBit<2>(); + + FAPI_ASSERT(!(l_read_reg), + fapi2::CHECKSTOP_ERR() + .set_READ_CHECKSTOP(l_read_reg), + "ERROR:CHECKSTOP BIT GET SET "); + + FAPI_INF("p9_sbe_chiplet_init: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H new file mode 100644 index 00000000..72d20577 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_init.H +/// +/// @brief init procedure for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_INIT_H_ +#define _P9_SBE_CHIPLET_INIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_init_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief chiplet init function call on all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C new file mode 100644 index 00000000..a36fa629 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C @@ -0,0 +1,123 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_initf.C +/// +/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_pll_initf.H" +#include "p9_perv_scom_addresses.H" + +fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_chiplet_pll_initf: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI), fapi2::TARGET_STATE_FUNCTIONAL)) + { + uint8_t l_unit_pos; + RingID l_ring_id = xb_pll_bndy; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_unit_pos), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + + switch (l_unit_pos) + { + case 0x6: + FAPI_DBG("Scan xb_pll_bndy_ring"); + l_ring_id = xb_pll_bndy; + break; + + case 0x9: + FAPI_DBG("Scan ob0_pll_bndy ring"); + l_ring_id = ob0_pll_bndy; + break; + + case 0xa: + FAPI_DBG("Scan ob1_pll_bndy ring"); + l_ring_id = ob1_pll_bndy; + break; + + case 0xb: + FAPI_DBG("Scan ob2_pll_bndy ring"); + l_ring_id = ob2_pll_bndy; + break; + + case 0xc: + FAPI_DBG("Scan ob3_pll_bndy ring"); + l_ring_id = ob3_pll_bndy; + break; + + case 0xd: + FAPI_DBG("Scan pci0_pll_bndy ring"); + l_ring_id = pci0_pll_bndy; + break; + + case 0xe: + FAPI_DBG("Scan pci1_pll_bndy ring"); + l_ring_id = pci1_pll_bndy; + break; + + case 0xf: + FAPI_DBG("Scan pci2_pll_bndy ring"); + l_ring_id = pci2_pll_bndy; + break; + + default: + FAPI_ASSERT(false, + fapi2::P9_SBE_CHIPLET_PLL_INITF_INVALID_CHIPLET(). + set_TARGET(l_chplt_trgt). + set_UNIT_POS(l_unit_pos), + "Unexpected chiplet!"); + } + + FAPI_TRY(fapi2::putRing(i_target_chip, l_ring_id, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (ringID: %d)", l_ring_id); + + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Scan mc_pll_bndy_bucket_1 ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (mc_pll_bndy)"); + } + +fapi_try_exit: + FAPI_INF("p9_sbe_chiplet_pll_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H new file mode 100644 index 00000000..a45218b9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_initf.H +/// +/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_PLL_INITF_H_ +#define _P9_SBE_CHIPLET_PLL_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief If TRUE then skip MC chiplet +/// run scan0 module (scan region = PLL, scan_types = GPTR) +/// run scan0 module (scan region = PLL, scan_types = BNDY/FUNC) +/// Scan initialize PLL BNDY chain (chiplet =[CPLT], scan ring = PLL, scan type = BNDY) +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C new file mode 100644 index 00000000..a152c465 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C @@ -0,0 +1,427 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_setup.C +/// +/// @brief Setup PLL for Obus, Xbus, PCIe, DMI +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_pll_setup.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_CHIPLET_PLL_SETUP_Private_Constants +{ + NS_DELAY = 5000000, // unit is nano seconds + SIM_CYCLE_DELAY = 100000, // unit is sim cycles + CLOCK_CMD = 0x1, + CLOCK_TYPES = 0x2, + DONT_STARTMASTER = 0x0, + DONT_STARTSLAVE = 0x0, + REGIONS = 0x001 +}; + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_test_enable( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_read_attr = 0; + FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop PDLY bypass"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_bypass(l_chplt_trgt)); + } + + FAPI_DBG("Reading ATTR_mc_sync_mode"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); + + if ( l_read_attr ) + { + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("call clock start stop module and drop syncclk muxsel"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("release pll test enable for except pcie"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Release PLL reset"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Check pll lock for PCIe"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Check pll lock for Xb,Ob"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt)); + } + } + else + { + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop MCC bypass"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_dcc_bypass(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("call clock start stop module and drop syncclk_muxsel"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("release pll test enable for except pcie"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Release PLL reset"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Check pll lock for pcie"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("check pll lock for Mc,Xb,Ob"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt)); + } + } + + FAPI_INF("p9_sbe_chiplet_pll_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief check pll lock for pcie chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pci_pll_lock: Entering ..."); + + FAPI_DBG("Check PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<0>() == 1 && l_read_reg.getBit<1>() == 1, + fapi2::PLL_LOCK_ERR() + .set_PLL_READ(l_read_reg), + "ERROR:PLL LOCK NOT SET"); + + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pci_pll_lock: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief check pll lock for OB,XB,MC +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pll_lock: Entering ..."); + + FAPI_DBG("Check PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<0>() == 1 , + fapi2::PLL_LOCK_ERR() + .set_PLL_READ(l_read_reg), + "ERROR:PLL LOCK NOT SET"); + + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pll_lock: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setup PLL for XBus, OBus, PCIe, (MC) chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_function: Entering ..."); + + FAPI_DBG("Drop PLL Bypass"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_PLL_BYPASS>(); //NET_CTRL0.PLL_BYPASS = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_DBG("Set scan ratio to 4:1 as soon as PLL is out of bypass mode"); + //Setting OPCG_ALIGN register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (0x3); //OPCG_ALIGN.SCAN_RATIO = 0x3 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64)); + + FAPI_DBG("Reset PCB Slave error register"); + //Setting ERROR_REG register value + //ERROR_REG = 0xFFFFFFFFFFFFFFFF + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_ERROR_REG, 0xFFFFFFFFFFFFFFFF)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop Mc DCC bypass +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Entering ..."); + + FAPI_DBG("Drop DCC bypass"); + //Setting NET_CTRL1 register value + l_data64.flush<1>(); + //NET_CTRL1.CLK_DCC_BYPASS_EN = 0 + l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop Mc PDLY bypass +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_pdly_bypass: Entering ..."); + + FAPI_DBG("Drop PDLY bypass"); + //Setting NET_CTRL1 register value + l_data64.flush<1>(); + //NET_CTRL1.CLK_PDLY_BYPASS_EN = 0 + l_data64.clearBit<PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_pdly_bypass: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief release pll reset and wait +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_reset: Entering ..."); + + FAPI_DBG("Drop PLL Reset"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_PLL_RESET>(); //NET_CTRL0.PLL_RESET = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Release pll test enable except for pcie +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_test_enable( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_test_enable: Entering ..."); + + FAPI_DBG("Release PLL test enable for except pcie"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_PLL_TEST_EN>(); //NET_CTRL0.PLL_TEST_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_test_enable: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief start PLL clock region, NSL latches only , call module clock_start_stop +/// Drop syncclk_muxsel +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux: Entering ..."); + + FAPI_DBG("call module clock start stop"); + FAPI_TRY(p9_sbe_common_clock_start_stop(i_target_chiplet, CLOCK_CMD, + DONT_STARTSLAVE, DONT_STARTMASTER, REGIONS, CLOCK_TYPES)); + + FAPI_DBG("Drop syncclk muxsel for pcie chiplet"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H new file mode 100644 index 00000000..c2b1caad --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_setup.H +/// +/// @brief Setup PLL for Obus, Xbus, PCIe, DMI +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_PLL_SETUP_H_ +#define _P9_SBE_CHIPLET_PLL_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_setup_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Checks that the PLL locked +/// Start the VAR OSCs / Config the TANK PLLs & lock +/// In certain configs these chiplets are potentially not used +/// Must run at system frequency +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C new file mode 100644 index 00000000..951b4696 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -0,0 +1,1330 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_reset.C +/// +/// @brief Steps:- +/// 1) Identify Partical good chiplet and configure Multicasting register +/// 2) Similar way, Configure hang pulse counter for Nest/MC/OBus/XBus/PCIe +/// 3) Similar way, set fence for Nest and MC chiplet +/// 4) Similar way, Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode +/// +/// Done +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_reset.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint8_t i_reg0_val = 0xff, + const uint8_t i_reg1_val = 0xff, + const uint8_t i_reg2_val = 0xff, + const uint8_t i_reg3_val = 0xff, + const uint8_t i_reg4_val = 0xff, + const uint8_t i_reg5_val = 0xff, + const uint8_t i_reg6_val = 0xff); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_call( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_xbus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_enable_listen_to_sync( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_hsspowergate( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const bool i_drop); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint64_t i_mc_grp1_val, + const uint64_t i_mc_grp2_val = 0x0, + const uint64_t i_mc_grp3_val = 0x0); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_ob_async_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode +p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_pll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_scan0_call( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +fapi2::ReturnCode p9_sbe_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + // Local variable + //uint8_t l_mc_sync_mode = 0; + fapi2::buffer<uint8_t> l_attr_vitl_setup; + fapi2::buffer<uint8_t> l_attr_hang_cnt6_setup; + fapi2::TargetState l_target_state = fapi2::TARGET_STATE_FUNCTIONAL; + FAPI_INF("p9_sbe_chiplet_reset: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP, i_target_chip, + l_attr_vitl_setup)); + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring chiplet multicasting registers. + FAPI_DBG("Configuring multicasting registers for Nest,Xb,Obus,pcie chiplets" ); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Configuring multicast registers for MC01,MC23"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP2)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CACHES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring chiplet multicasting registers.. + FAPI_DBG("Configuring cache chiplet multicasting registers"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup_cache(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CORES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring chiplet multicasting registers.. + FAPI_DBG("Configuring core chiplet multicasting registers"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP1, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP3)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring NET control registers into Default required value + FAPI_DBG("Restore NET_CTRL0&1 init value - for all chiplets except TP"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 0 and register 6 + FAPI_DBG("Setup hang pulse counter for Mc"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, 0xff, 0xff, 0xff, 0xff, 0xff, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 0 and register 6 + FAPI_DBG("Setup hang pulse counter for Pcie - increase in hang_pulse value"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, 0xff, 0xff, 0xff, 0xff, 0xff, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 0 and register 6 + FAPI_DBG("Setup hang pulse counter for Xbus,Obus"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X04, 0xff, + 0xff, 0xff, 0xff, p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_NEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 5 + FAPI_DBG("Setup hang pulse counter for nest chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_nest_hang_cnt_setup(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CORES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 5 + FAPI_DBG("Setup hang pulse counter for core chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X1A, 0xff, + 0xff, 0xff, p9SbeChipletReset::HANG_PULSE_0X06, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CACHES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 5 + FAPI_DBG("Setup hang pulse counter for cache chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X01, + p9SbeChipletReset::HANG_PULSE_0X01, p9SbeChipletReset::HANG_PULSE_0X04, + p9SbeChipletReset::HANG_PULSE_0X00, p9SbeChipletReset::HANG_PULSE_0X06, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + FAPI_DBG("Clock mux settings"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_call(i_target_chip)); + + if ( l_attr_vitl_setup ) + { + l_target_state = fapi2::TARGET_STATE_PRESENT; + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), l_target_state)) + { + // Setting up partial good fence drop and resetting chiplet. + FAPI_DBG("PLL Setup : Enable pll"); + FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(l_target_cplt, true)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, l_target_state)) + { + FAPI_DBG("Drop clk async reset for N3 chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, l_target_state)) + { + FAPI_DBG("Drop clk async reset for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(l_target_cplt, true)); + } + + fapi2::delay(10000, (40 * 400)); + + if ( l_attr_vitl_setup ) + { + l_target_state = fapi2::TARGET_STATE_PRESENT; + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), l_target_state)) + { + // Setting up partial good fence drop and resetting chiplet. + FAPI_DBG("PLL setup : Disable pll"); + FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(l_target_cplt, false)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, l_target_state)) + { + FAPI_DBG("Raise clk async reset for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(l_target_cplt, false)); + } + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop clk async reset for N3, Mc and Obus chiplets"); + FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop clk_div_bypass for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Enable chiplet and reset error register"); + FAPI_TRY(p9_sbe_chiplet_reset_setup(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop lvltrans fence and endpoint reset"); + FAPI_TRY(p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset( + l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Initialize OPCG registers for Nest,MC,XB,OB,PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Enable listen to sync for NEST,OB,XB,PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(l_target_cplt, true)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Disable listen_to_sync for Nest,MC,XB,OB,PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(l_target_cplt, false)); + } + + FAPI_DBG("Set Chip-wide HSSPORWREN gate"); + FAPI_TRY(p9_sbe_chiplet_reset_hsspowergate(i_target_chip)); + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Setup IOP Logic for PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_setup_iop_logic(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("set scan ratio to 1:1 "); + FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_chiplet_reset_scan0_call(l_target_cplt)); + } + + FAPI_INF("p9_sbe_chiplet_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setting up hang pulse counter for all parital good chiplet except for Tp,nest, core and cache +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @param[in] i_reg0_val value for HANG_PULSE_0_REG +/// @param[in] i_reg1_val value for HANG_PULSE_1_REG +/// @param[in] i_reg2_val value for HANG_PULSE_2_REG +/// @param[in] i_reg3_val value for HANG_PULSE_3_REG +/// @param[in] i_reg4_val value for HANG_PULSE_4_REG +/// @param[in] i_reg5_val value for HANG_PULSE_5_REG +/// @param[in] i_reg6_val Hang pulse reg 6 value - for heartbeat +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint8_t i_reg0_val, + const uint8_t i_reg1_val, + const uint8_t i_reg2_val, + const uint8_t i_reg3_val, + const uint8_t i_reg4_val, + const uint8_t i_reg5_val, + const uint8_t i_reg6_val) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Entering ..."); + + //Setting HANG_PULSE_0_REG register value (Setting all fields) + if (i_reg0_val != 0xff) + { + //HANG_PULSE_0_REG.HANG_PULSE_REG_0 = (i_reg0_val != 0xff) ? i_reg0_val + l_data64.insertFromRight<0, 6>(i_reg0_val); + //HANG_PULSE_0_REG.SUPPRESS_HANG_0 = (i_reg0_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_0_REG, l_data64)); + } + + //Setting HANG_PULSE_1_REG register value (Setting all fields) + if (i_reg1_val != 0xff) + { + //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = (i_reg1_val != 0xff) ? i_reg1_val + l_data64.insertFromRight<0, 6>(i_reg1_val); + //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = (i_reg1_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); + } + + //Setting HANG_PULSE_2_REG register value (Setting all fields) + if (i_reg2_val != 0xff) + { + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = (i_reg2_val != 0xff) ? i_reg2_val + l_data64.insertFromRight<0, 6>(i_reg2_val); + //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = (i_reg2_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + } + + //Setting HANG_PULSE_3_REG register value (Setting all fields) + if (i_reg3_val != 0xff) + { + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = (i_reg3_val != 0xff) ? i_reg3_val + l_data64.insertFromRight<0, 6>(i_reg3_val); + //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = (i_reg3_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + } + + //Setting HANG_PULSE_4_REG register value (Setting all fields) + if (i_reg4_val != 0xff) + { + //HANG_PULSE_4_REG.HANG_PULSE_REG_4 = (i_reg4_val != 0xff) ? i_reg4_val + l_data64.insertFromRight<0, 6>(i_reg4_val); + //HANG_PULSE_4_REG.SUPPRESS_HANG_4 = (i_reg4_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64)); + } + + //Setting HANG_PULSE_5_REG register value (Setting all fields) + if (i_reg5_val != 0xff) + { + //HANG_PULSE_5_REG.HANG_PULSE_REG_5 = (i_reg5_val != 0xff) ? i_reg5_val + l_data64.insertFromRight<0, 6>(i_reg5_val); + //HANG_PULSE_5_REG.SUPPRESS_HANG_5 = (i_reg5_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_5_REG, l_data64)); + } + + //Setting HANG_PULSE_6_REG register value (Setting all fields) + if (i_reg6_val != 0xff) + { + //HANG_PULSE_6_REG.HANG_PULSE_REG_6 = (i_reg6_val != 0xff) ? i_reg6_val + l_data64.insertFromRight<0, 6>(i_reg6_val); + //HANG_PULSE_6_REG.SUPPRESS_HANG_6 = (i_reg6_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_6_REG, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Configuring NET control registers into Default required value +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + fapi2::buffer<uint8_t> l_read_attr; + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup: Entering ..."); + + //Setting NET_CTRL0 register value + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = + i_target_cplt.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + FAPI_DBG("Disable local clock gating VITAL"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING, + l_chip, l_read_attr)); + + if (l_read_attr) + { + //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0, + p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1)); + } + else + { + //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0, + p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE)); + } + + //Setting NET_CTRL1 register value + //NET_CTRL1 = p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL1, + p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE)); + + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup:Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for Mc chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC: Entering ..."); + + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<3>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<3>()); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief call all the related mux settings on chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_call( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet) +{ + fapi2::buffer<uint32_t> l_read_attr; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_call: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chiplet, + l_read_attr)); + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_MC(l_target_cplt, l_read_attr)); + } + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for OB chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_obus(l_target_cplt, l_read_attr)); + } + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for XB chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_xbus(l_target_cplt, l_read_attr)); + } + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for Pcie chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_pcie(l_target_cplt, l_read_attr)); + } + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_call: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for OB chiplet +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value Clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + uint8_t l_attr_unit_pos = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, + l_attr_unit_pos)); + + if ( l_attr_unit_pos == 0x09 ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<6>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<6>()); + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL> + (i_clk_mux_value.getBit<13>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<13>() + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL> + (i_clk_mux_value.getBit<15>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<15>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + if ( l_attr_unit_pos == 0x0A ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL> + (i_clk_mux_value.getBit<16>()); //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<16>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + if ( l_attr_unit_pos == 0x0B ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL> + (i_clk_mux_value.getBit<17>()); //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<17>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + if ( l_attr_unit_pos == 0x0C ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<7>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<7>()); + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL> + (i_clk_mux_value.getBit<9>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<9>() + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL> + (i_clk_mux_value.getBit<14>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<14>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for Pcie chiplet +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + uint8_t l_attr_unit_pos = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, + l_attr_unit_pos)); + + if ( l_attr_unit_pos != 0x0E ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>((l_attr_unit_pos == 0x0D) ? + i_clk_mux_value.getBit<5>() : + i_clk_mux_value.getBit<4>()); //NET_CTRL1.PLL_CLKIN_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<5>() : i_clk_mux_value.getBit<4>() + + if (l_attr_unit_pos == 0x0D) + { + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL> + (i_clk_mux_value.getBit<10>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<10>() + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL> + (i_clk_mux_value.getBit<11>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<11>() + } + + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for XB chiplet +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_xbus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_xbus: Entering ..."); + + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<8>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<8>()); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_xbus: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop clk div bypass for Mc chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Entering ..."); + + FAPI_DBG("drop clk_div_bypass_en"); + //Setting NET_CTRL1 register value + l_data64.flush<1>(); + //NET_CTRL1.CLK_DIV_BYPASS_EN = 0 + l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Enable listen_to_sync mode for all chiplets except MC +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_enable if TRUE - enable, FALSE - disable +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_enable_listen_to_sync( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable) +{ + FAPI_INF("p9_sbe_chiplet_reset_enable_listen_to_sync: Entering ..."); + + //Setting SYNC_CONFIG register value + //SYNC_CONFIG = i_enable? p9SbeChipletReset::SYNC_CONFIG_DEFAULT : p9SbeChipletReset::SYNC_CONFIG_4TO1 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SYNC_CONFIG, + i_enable ? p9SbeChipletReset::SYNC_CONFIG_DEFAULT : + p9SbeChipletReset::SYNC_CONFIG_4TO1)); + + FAPI_INF("p9_sbe_chiplet_reset_enable_listen_to_sync: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Set Chip-wide HSSPORWREN gate +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_hsspowergate( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_chiplet_reset_hsspowergate: Entering ..."); + + //Getting ROOT_CTRL2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, + l_read_reg)); //l_read_reg = PIB.ROOT_CTRL2 + + l_read_reg.setBit<20>(); + + FAPI_DBG("Set Chip-wide HSSPORWREN gate"); + //Setting ROOT_CTRL2 register value + //PIB.ROOT_CTRL2 = l_read_reg + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_read_reg)); + + FAPI_INF("p9_sbe_chiplet_reset_hsspowergate: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop/ raise MC async reset +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_drop Raise/drop mc async reset +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const bool i_drop) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_mc_async_reset_setup: Entering ..."); + + if ( i_drop ) + { + FAPI_DBG("Drop mc async reset"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.CLK_ASYNC_RESET = 0 + l_data64.clearBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); + } + else + { + if ( !(i_target_chip.isFunctional()) ) + { + FAPI_DBG("Raise mc async reset"); + //Setting NET_CTRL0 register value + l_data64.flush<0>(); + //NET_CTRL0.CLK_ASYNC_RESET = 1 + l_data64.setBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WOR, l_data64)); + } + } + + FAPI_INF("p9_sbe_chiplet_reset_mc_async_reset_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Configuring multicast registers for nest, cache, core +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_mc_grp1_val value for MULTICAST_GROUP1 register +/// @param[in] i_mc_grp2_val value for MULTICAST_GROUP2 register +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint64_t i_mc_grp1_val, + const uint64_t i_mc_grp2_val, + const uint64_t i_mc_grp3_val) +{ + FAPI_INF("p9_sbe_chiplet_reset_mc_setup: Entering ..."); + + //Setting MULTICAST_GROUP_1 register value + //MULTICAST_GROUP_1 (register) = i_mc_grp1_val + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1, + i_mc_grp1_val)); + + //Setting MULTICAST_GROUP_2 register value + if (i_mc_grp2_val != 0x0) + { + //MULTICAST_GROUP_2 (register) = (i_mc_grp2_val != 0x0) ? i_mc_grp2_val + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2, + i_mc_grp2_val)); + } + + //Setting MULTICAST_GROUP_3 register value + if (i_mc_grp3_val != 0x0) + { + //MULTICAST_GROUP_REGISTER_3 = (i_mc_grp3_val != 0x0) ? i_mc_grp3_val + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3, + i_mc_grp3_val)); + } + + FAPI_INF("p9_sbe_chiplet_reset_mc_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Multicast register setup for Cache chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + uint32_t l_attr_pg = 0; + FAPI_INF("p9_sbe_chiplet_reset_mc_setup_cache: Entering ..."); + + FAPI_DBG("Reading ATTR_PG"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); + + FAPI_DBG("Setting Multicast register 1&2 for cache chiplet"); + //Setting MULTICAST_GROUP_1 register value + //MULTICAST_GROUP_1 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0)); + //Setting MULTICAST_GROUP_2 register value + //MULTICAST_GROUP_2 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4)); + + if ( ( l_attr_pg & 0x1EBA ) == 0x0 ) // Check good EP chiplet clockdomains excluding l31, l21, refr1 + { + FAPI_DBG("Setting up multicast register 3 for even cache chiplet"); + //Setting MULTICAST_GROUP_3 register value + //MULTICAST_GROUP_3 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5)); + } + + if ( ( l_attr_pg & 0x1D76 ) == 0x0 ) // Check good EP chiplet clockdomains excluding l30, l20, refr0 + { + FAPI_DBG("Setting up multicast register 4 for odd cache chiplet"); + //Setting MULTICAST_GROUP_4 register value + //MULTICAST_GROUP_4 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_4, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6)); + } + + FAPI_INF("p9_sbe_chiplet_reset_mc_setup_cache: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setting up hang pulse counter for partial good Nest chiplet +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + // Local variables + // + uint8_t l_attr_chipunit_pos = 0; + const uint8_t l_n0 = 0x02; + const uint8_t l_n1 = 0x03; + const uint8_t l_n2 = 0x04; + const uint8_t l_n3 = 0x05; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_nest_hang_cnt_setup: Entering ..."); + + // Collecting partial good and chiplet unit position attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_cplt, + l_attr_chipunit_pos)); + + //Setting HANG_PULSE_0_REG register value (Setting all fields) + //HANG_PULSE_0_REG.HANG_PULSE_REG_0 = p9SbeChipletReset::HANG_PULSE_0X10 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X10); + l_data64.clearBit<6>(); //HANG_PULSE_0_REG.SUPPRESS_HANG_0 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_0_REG, l_data64)); + //Setting HANG_PULSE_5_REG register value (Setting all fields) + //HANG_PULSE_5_REG.HANG_PULSE_REG_5 = p9SbeChipletReset::HANG_PULSE_0X06 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X06); + l_data64.clearBit<6>(); //HANG_PULSE_5_REG.SUPPRESS_HANG_5 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_5_REG, l_data64)); + //Setting HANG_PULSE_6_REG register value (Setting all fields) + //HANG_PULSE_6_REG.HANG_PULSE_REG_6 = p9SbeChipletReset::HANG_PULSE_0X08 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X08); + l_data64.clearBit<6>(); //HANG_PULSE_6_REG.SUPPRESS_HANG_6 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_6_REG, l_data64)); + + if ( l_attr_chipunit_pos == l_n0 ) + { + //Setting HANG_PULSE_1_REG register value (Setting all fields) + //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X18 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X18); + l_data64.clearBit<6>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X23 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X23); + l_data64.clearBit<6>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X12); + l_data64.clearBit<6>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + } + + if ( l_attr_chipunit_pos == l_n1 ) + { + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X0F + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X0F); + l_data64.clearBit<6>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + } + + if ( l_attr_chipunit_pos == l_n2 ) + { + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X12); + l_data64.clearBit<6>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + } + + if ( l_attr_chipunit_pos == l_n3 ) + { + //Setting HANG_PULSE_1_REG register value (Setting all fields) + //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X17 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X17); + l_data64.clearBit<6>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X13 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X13); + l_data64.clearBit<6>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X0F + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X0F); + l_data64.clearBit<6>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + //Setting HANG_PULSE_4_REG register value (Setting all fields) + //HANG_PULSE_4_REG.HANG_PULSE_REG_4 = p9SbeChipletReset::HANG_PULSE_0X1C + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X1C); + l_data64.clearBit<6>(); //HANG_PULSE_4_REG.SUPPRESS_HANG_4 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_nest_hang_cnt_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Dropping the net_ctrl0 clock_async_reset +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_ob_async_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_nest_ob_async_reset: Entering ..."); + + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.CLK_ASYNC_RESET = 0 + l_data64.clearBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_nest_ob_async_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop Endpoint reset +/// Drop lvltrans fence +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode +p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset: Entering ..."); + + FAPI_DBG("Drop lvltrans fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.LVLTRANS_FENCE = 0b0 + l_data64.clearBit<PERV_1_NET_CTRL0_LVLTRANS_FENCE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_DBG("Drop endpoint reset"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.PCB_EP_RESET = 0b0 + l_data64.clearBit<PERV_1_NET_CTRL0_PCB_EP_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief configuring Nest chiplet OPCG registers +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg: Entering ..."); + + //Setting OPCG_ALIGN register value + l_data64 = + p9SbeChipletReset::OPCG_ALIGN_SETTING; //OPCG_ALIGN = p9SbeChipletReset::OPCG_ALIGN_SETTING + //OPCG_ALIGN.INOP_ALIGN = p9SbeChipletReset::INOP_ALIGN_SETTING_0X5 + l_data64.insertFromRight<0, 4>(p9SbeChipletReset::INOP_ALIGN_SETTING_0X5); + l_data64.clearBit<PERV_1_OPCG_ALIGN_INOP_WAIT, PERV_1_OPCG_ALIGN_INOP_WAIT_LEN>(); //OPCG_ALIGN.INOP_WAIT = 0 + //OPCG_ALIGN.OPCG_WAIT_CYCLES = p9SbeChipletReset::OPCG_WAIT_CYCLE_0X020 + l_data64.insertFromRight<52, 12>(p9SbeChipletReset::OPCG_WAIT_CYCLE_0X020); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (p9SbeChipletReset::SCAN_RATIO_0X3); //OPCG_ALIGN.SCAN_RATIO = p9SbeChipletReset::SCAN_RATIO_0X3 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief set scan ratio to 1:1 as long as PLL is in bypass mode +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio: Entering ..."); + + FAPI_DBG("Set scan ratio to 1:1 as long as PLL is in bypass mode"); + //Setting OPCG_ALIGN register value + FAPI_TRY(fapi2::getScom(i_target_cplt, PERV_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (p9SbeChipletReset::SCAN_RATIO_0X0); //OPCG_ALIGN.SCAN_RATIO = p9SbeChipletReset::SCAN_RATIO_0X0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_OPCG_ALIGN, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Enable PLL +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_enable enable/disable pll +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_pll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable) +{ + fapi2::buffer<uint64_t> l_data;; + FAPI_INF("p9_sbe_chiplet_reset_pll_setup: Entering ..."); + + if ( i_enable ) + { + l_data.flush<0>(); + l_data.setBit<31>(); + + FAPI_DBG("Enable pll"); + //Setting NET_CTRL0 register value + //NET_CTRL0 = l_data + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data)); + } + else + { + if ( !(i_target_chiplet.isFunctional()) ) + { + l_data.flush<1>(); + l_data.clearBit<31>(); + + FAPI_DBG("Disable PLL"); + //Setting NET_CTRL0 register value + //NET_CTRL0 = l_data + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data)); + } + } + + FAPI_INF("p9_sbe_chiplet_reset_pll_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Scan0 module call +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_scan0_call( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + FAPI_INF("p9_sbe_chiplet_reset_scan0_call: Entering ..."); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(i_target_chip, + p9SbeChipletReset::REGIONS_EXCEPT_VITAL, l_regions)); + + FAPI_DBG("run scan0 module for region except vital and pll, scan types GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chip, l_regions, + p9SbeChipletReset::SCAN_TYPES_TIME_GPTR_REPR)); + + FAPI_DBG("run scan0 module for region except vital and pll, scan types except GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chip, l_regions, + p9SbeChipletReset::SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + + FAPI_INF("p9_sbe_chiplet_reset_scan0_call: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Dorping fence on Partial good chiplet and resetting it. +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + // Local variable and constant definition + const uint64_t l_error_default_value = 0xFFFFFFFFFFFFFFFFull; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_setup: Entering ..."); + + // EP Reset all chiplet with in multicasting group + //Setting NET_CTRL0 register value + l_data64.flush<0>(); + //NET_CTRL0.CHIPLET_ENABLE = 0b1 + l_data64.setBit<PERV_1_NET_CTRL0_CHIPLET_ENABLE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64)); + + //Setting ERROR_REG register value + //ERROR_REG = l_error_default_value + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_ERROR_REG, + l_error_default_value)); + + FAPI_INF("p9_sbe_chiplet_reset_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setup IOP Logic for PCIe +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_setup_iop_logic: Entering ..."); + + //Setting CPLT_CONF1 register value + l_data64.flush<0>(); + l_data64.setBit<30>(); //CPLT_CONF1.TC_IOP_HSSPORWREN = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF1_OR, l_data64)); + + fapi2::delay(p9SbeChipletReset::HW_NS_DELAY, + p9SbeChipletReset::SIM_CYCLE_DELAY); + + //Setting CPLT_CONF1 register value + l_data64.flush<0>(); + l_data64.setBit<28>(); //CPLT_CONF1.TC_IOP_SYS_RESET_PCS = 0b1 + l_data64.setBit<29>(); //CPLT_CONF1.TC_IOP_SYS_RESET_PMA = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF1_OR, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_setup_iop_logic:Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H new file mode 100644 index 00000000..feeec54b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -0,0 +1,125 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_reset.H +/// +/// @brief Steps:- +/// 1) Identify Partical good chiplet and configure Multicasting register +/// 2) Similar way, Configure hang pulse counter for Nest/MC/OBus/XBus/PCIe +/// 3) Similar way, set fence for Nest and MC chiplet +/// 4) Similar way, Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode +/// +/// Done +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_RESET_H_ +#define _P9_SBE_CHIPLET_RESET_H_ + + +#include <fapi2.H> + + +namespace p9SbeChipletReset +{ +enum P9_SBE_CHIPLET_RESET_Public_Constants +{ + MCGR_CNFG_SETTING_GROUP0 = 0xE0001C0000000000ull, + MCGR_CNFG_SETTING_GROUP1 = 0xE4001C0000000000ull, + MCGR_CNFG_SETTING_GROUP2 = 0xE8001C0000000000ull, + MCGR_CNFG_SETTING_GROUP3 = 0xEC001C0000000000ull, + MCGR_CNFG_SETTING_GROUP4 = 0xF0001C0000000000ull, + MCGR_CNFG_SETTING_GROUP5 = 0xF4001C0000000000ull, + MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull, + NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull, + NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull, + HANG_PULSE_0X10 = 0x10, + HANG_PULSE_0X0F = 0x0F, + HANG_PULSE_0X06 = 0x06, + HANG_PULSE_0X17 = 0x17, + HANG_PULSE_0X18 = 0x18, + HANG_PULSE_0X22 = 0x22, + HANG_PULSE_0X23 = 0x23, + HANG_PULSE_0X13 = 0x13, + HANG_PULSE_0X03 = 0x03, + OPCG_ALIGN_SETTING = 0x5000000000003020ull, + INOP_ALIGN_SETTING_0X5 = 0x5, + OPCG_WAIT_CYCLE_0X020 = 0x020, + SCAN_RATIO_0X3 = 0x3, + SYNC_PULSE_DELAY_0X0 = 0X00, + SYNC_CONFIG_DEFAULT = 0X0000000000000000, + HANG_PULSE_0X00 = 0x00, + HANG_PULSE_0X01 = 0x01, + HANG_PULSE_0X04 = 0x04, + HANG_PULSE_0X1A = 0x1A, + NET_CNTL1_HW_INIT_VALUE = 0x7200000000000000ull, + REGIONS_EXCEPT_VITAL = 0x7FF, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE, + SCAN_TYPES_TIME_GPTR_REPR = 0x230, + SCAN_RATIO_0X0 = 0x0, + SYNC_CONFIG_4TO1 = 0X0800000000000000, + HW_NS_DELAY = 200000, // unit is nano seconds + SIM_CYCLE_DELAY = 10000, // unit is cycles + HANG_PULSE_0X12 = 0x12, + HANG_PULSE_0X1C = 0x1C, + HANG_PULSE_0X08 = 0x08 +}; +} + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_reset_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Identify all good chiplets excluding EQ/EC +/// -- All chiplets will be reset and PLLs started +/// -- Partial bad - All nest Chiplets must be good, MC, IO can be partial bad +/// Setup multicast groups for all chiplets +/// -- Can't use the multicast for all non-nest chiplets +/// -- This is intended to be the eventual product setting +/// -- This includes the core/cache chiplets +/// For all good chiplets excluding EQ/EC +/// -- Setup Chiplet GP3 regs +/// -- Reset to default state +/// -- Set chiplet enable on all all good chiplets excluding EQ/EC +/// For all enabled chiplets excluding EQ/EC/Buses +/// -- Start vital clocks and release endpoint reset +/// -- PCB Slave error register Reset +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C new file mode 100644 index 00000000..3a8a765c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_clock_test2.C +/// +/// @brief sbe_clock_test2 for enabling osc-check +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_clock_test2.H" + + + +fapi2::ReturnCode p9_sbe_clock_test2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet) +{ + FAPI_INF("Entering ..."); + + FAPI_INF("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H new file mode 100644 index 00000000..180d8c66 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_clock_test2.H +/// +/// @brief sbe_clock_test2 for enabling osc-check +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CLOCK_TEST2_H_ +#define _P9_SBE_CLOCK_TEST2_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_clock_test2_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief enable osc checking +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_clock_test2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C new file mode 100644 index 00000000..c9586829 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -0,0 +1,658 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_common.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_common.C +/// +/// @brief Common Modules for SBE +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_common.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_const_common.H> + + +enum P9_SBE_COMMON_Private_Constants +{ + NS_DELAY = 100000, // unit in nano seconds + SIM_CYCLE_DELAY = 1000, // unit in cycles + CPLT_ALIGN_CHECK_POLL_COUNT = 10, // count to wait for chiplet aligned + CPLT_OPCG_DONE_DC_POLL_COUNT = 10 // count to wait for chiplet opcg done +}; + +/// @brief --For all chiplets exit flush +/// --For all chiplets enable alignment +/// --For all chiplets disable alignemnt +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_align_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets) +{ + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_sbe_common_align_chiplets: Entering ..."); + + FAPI_DBG("For all chiplets: exit flush"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("For all chiplets: enable alignement"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("Clear chiplet is aligned"); + //Setting SYNC_CONFIG register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b1 + l_data64.setBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + + FAPI_DBG("Unset Clear chiplet is aligned"); + //Setting SYNC_CONFIG register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b0 + l_data64.clearBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); + l_timeout = CPLT_ALIGN_CHECK_POLL_COUNT; + + //UNTIL CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC == 1 + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::CPLT_NOT_ALIGNED_ERR(), + "ERROR:CHIPLET NOT ALIGNED"); + + FAPI_DBG("For all chiplets: disable alignement"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_common_align_chiplets: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief To do check on Clock controller status for chiplets +/// +/// @param[in] i_target Reference to TARGET_TYPE_PERV target Reference to TARGET_TYPE_PERV target +/// @param[in] i_clock_cmd Issue clock controller command (START/STOP) +/// @param[in] i_regions Enable required REGIONS +/// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_cc_status_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types) +{ + bool l_reg_sl = false; + bool l_reg_nsl = false; + bool l_reg_ary = false; + fapi2::buffer<uint64_t> l_sl_clock_status; + fapi2::buffer<uint64_t> l_nsl_clock_status; + fapi2::buffer<uint64_t> l_ary_clock_status; + fapi2::buffer<uint16_t> l_sl_clkregion_status; + fapi2::buffer<uint16_t> l_nsl_clkregion_status; + fapi2::buffer<uint16_t> l_ary_clkregion_status; + fapi2::buffer<uint16_t> l_regions; + FAPI_INF("p9_sbe_common_check_cc_status_function: Entering ..."); + + l_reg_sl = i_clock_types.getBit<5>(); + l_reg_nsl = i_clock_types.getBit<6>(); + l_reg_ary = i_clock_types.getBit<7>(); + i_regions.extractToRight<5, 11>(l_regions); + + if ( l_reg_sl ) + { + FAPI_DBG("Check for Clocks running SL"); + //Getting CLOCK_STAT_SL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, + l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL + FAPI_DBG("SL Clock status register is %#018lX", l_sl_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_sl_clkregion_status.flush<1>(); + l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); + l_sl_clkregion_status.invert(); + l_sl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_sl_clkregion_status == l_regions, + fapi2::NEST_SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "Clock running for sl type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_sl_clkregion_status.flush<0>(); + l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); + l_sl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_sl_clkregion_status == l_regions, + fapi2::NEST_SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "Clock running for sl type not matching with expected values"); + } + } + + if ( l_reg_nsl ) + { + FAPI_DBG("Check for clocks running NSL"); + //Getting CLOCK_STAT_NSL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, + l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL + FAPI_DBG("NSL Clock status register is %#018lX", l_nsl_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_nsl_clkregion_status.flush<1>(); + l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); + l_nsl_clkregion_status.invert(); + l_nsl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_nsl_clkregion_status == l_regions, + fapi2::NEST_NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "Clock running for nsl type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_nsl_clkregion_status.flush<0>(); + l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); + l_nsl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_nsl_clkregion_status == l_regions, + fapi2::NEST_NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "Clock running for nsl type not matching with expected values"); + } + } + + if ( l_reg_ary ) + { + FAPI_DBG("Check for clocks running ARY"); + //Getting CLOCK_STAT_ARY register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, + l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY + FAPI_DBG("ARY Clock status register is %#018lX", l_ary_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_ary_clkregion_status.flush<1>(); + l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); + l_ary_clkregion_status.invert(); + l_ary_clkregion_status &= l_regions; + + FAPI_ASSERT(l_ary_clkregion_status == l_regions, + fapi2::NEST_ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "Clock running for ary type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_ary_clkregion_status.flush<0>(); + l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); + l_ary_clkregion_status &= l_regions; + + FAPI_ASSERT(l_ary_clkregion_status == l_regions, + fapi2::NEST_ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "Clock running for ary type not matching with expected values"); + } + } + + FAPI_INF("p9_sbe_common_check_cc_status_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --check checkstop register +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_checkstop_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_common_check_checkstop_function: Entering ..."); + + FAPI_DBG("Check checkstop register"); + //Getting XFIR register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_XFIR, + l_read_reg)); //l_read_reg = XFIR + + FAPI_ASSERT(l_read_reg == 0, + fapi2::READ_ALL_CHECKSTOP_ERR() + .set_READ_ALL_CHECKSTOP(l_read_reg), + "ERROR: COMBINE ALL CHECKSTOP ERROR"); + + FAPI_INF("p9_sbe_common_check_checkstop_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief check clocks status +/// +/// @param[in] i_regions regions from upper level input +/// @param[in] i_clock_status clock status +/// @param[in] i_reg bit status +/// @param[in] i_clock_cmd clock command +/// @param[out] o_exp_clock_status expected clock status +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer<uint64_t> + i_regions, + const fapi2::buffer<uint64_t> i_clock_status, + const bool i_reg, + const fapi2::buffer<uint8_t> i_clock_cmd, + fapi2::buffer<uint64_t>& o_exp_clock_status) +{ + FAPI_INF("p9_sbe_common_check_status: Entering ..."); + + if ( (i_reg) && (i_clock_cmd == 0b01) ) + { + o_exp_clock_status = i_clock_status & (~(i_regions << 49)); + } + else + { + if ( (i_reg) && (i_clock_cmd == 0b10) ) + { + o_exp_clock_status = i_clock_status | (i_regions << 49); + } + else + { + o_exp_clock_status = i_clock_status; + } + } + + FAPI_INF("p9_sbe_common_check_status: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} + +/// @brief -- Utility function that can be used to start clocks for a specific input regions +/// -- i_regions is to input regions +/// +/// +/// @param[in] i_target Reference to TARGET_TYPE_PERV target +/// @param[in] i_clock_cmd Issue clock controller command (START/STOP) +/// @param[in] i_startslave Bit to configure to start Slave +/// @param[in] i_startmaster Bit to configure to start Master +/// @param[in] i_regions Enable required REGIONS +/// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_clock_start_stop(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const bool i_startslave, + const bool i_startmaster, + const fapi2::buffer<uint64_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types) +{ + fapi2::buffer<uint64_t> l_sl_clock_status; + fapi2::buffer<uint64_t> l_nsl_clock_status; + fapi2::buffer<uint64_t> l_ary_clock_status; + fapi2::buffer<uint64_t> l_exp_sl_clock_status; + fapi2::buffer<uint64_t> l_exp_nsl_clock_status; + fapi2::buffer<uint64_t> l_exp_ary_clock_status; + fapi2::buffer<uint8_t> l_clk_cmd; + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint8_t> l_reg_all; + bool l_reg_sl = false; + bool l_reg_nsl = false; + bool l_reg_ary = false; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_sbe_common_clock_start_stop: Entering ..."); + + i_regions.extractToRight<53, 11>(l_regions); + i_clock_types.extractToRight<5, 3>(l_reg_all); + l_reg_sl = i_clock_types.getBit<5>(); + l_reg_nsl = i_clock_types.getBit<6>(); + l_reg_ary = i_clock_types.getBit<7>(); + + FAPI_DBG("Chiplet exit flush"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + FAPI_TRY(fapi2::putScom(i_target, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("Clear Scan region type register"); + //Setting SCAN_REGION_TYPE register value + //SCAN_REGION_TYPE = 0 + FAPI_TRY(fapi2::putScom(i_target, PERV_SCAN_REGION_TYPE, 0)); + + FAPI_DBG("Reading the initial status of clock controller"); + //Getting CLOCK_STAT_SL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, + l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL + //Getting CLOCK_STAT_NSL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, + l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL + //Getting CLOCK_STAT_ARY register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, + l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY + FAPI_DBG("Clock status of SL_Register:%#018lX NSL_Register:%#018lX ARY_Register:%#018lX", + l_sl_clock_status, l_nsl_clock_status, l_ary_clock_status); + + i_clock_cmd.extractToRight<6, 2>(l_clk_cmd); + + FAPI_DBG("Setup all Clock Domains and Clock Types"); + //Setting CLK_REGION register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLK_REGION, l_data64)); + l_data64.insertFromRight<PERV_1_CLK_REGION_CLOCK_CMD, PERV_1_CLK_REGION_CLOCK_CMD_LEN> + (l_clk_cmd); //CLK_REGION.CLOCK_CMD = l_clk_cmd + //CLK_REGION.SLAVE_MODE = i_startslave + l_data64.writeBit<PERV_1_CLK_REGION_SLAVE_MODE>(i_startslave); + //CLK_REGION.MASTER_MODE = i_startmaster + l_data64.writeBit<PERV_1_CLK_REGION_MASTER_MODE>(i_startmaster); + //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + //CLK_REGION.SEL_THOLD_ALL = l_reg_all + l_data64.insertFromRight<48, 3>(l_reg_all); + FAPI_TRY(fapi2::putScom(i_target, PERV_CLK_REGION, l_data64)); + + // To wait until OPCG Done - CPLT_STAT0.cc_cplt_opcg_done_dc = 1 + FAPI_DBG("Poll OPCG done bit to check for completeness"); + l_data64.flush<0>(); + l_timeout = CPLT_OPCG_DONE_DC_POLL_COUNT; + + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>(); + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::CPLT_OPCG_DONE_NOT_SET_ERR(), + "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD"); + + //To do do checking only for chiplets that dont have Master-slave mode enabled + + if ( !i_startslave && !i_startmaster ) + { + // Calculating the Expected clock status + + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_sl_clock_status, l_reg_sl, + i_clock_cmd, l_exp_sl_clock_status)); + + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_nsl_clock_status, l_reg_nsl, + i_clock_cmd, l_exp_nsl_clock_status)); + + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_ary_clock_status, l_reg_ary, + i_clock_cmd, l_exp_ary_clock_status)); + + FAPI_DBG("Check for clocks running SL"); + //Getting CLOCK_STAT_SL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, + l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", + l_exp_sl_clock_status, l_sl_clock_status); + + FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, + fapi2::SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); + + FAPI_DBG("Check for clocks running NSL"); + //Getting CLOCK_STAT_NSL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, + l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", + l_exp_nsl_clock_status, l_nsl_clock_status); + + FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, + fapi2::NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); + + FAPI_DBG("Check for clocks running ARY"); + //Getting CLOCK_STAT_ARY register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, + l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", + l_exp_ary_clock_status, l_ary_clock_status); + + FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, + fapi2::ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); + } + + FAPI_INF("p9_sbe_common_clock_start_stop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --drop vital fence +/// --reset abstclk muxsel,syncclk_muxsel +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr_pg ATTR_PG for the corresponding chiplet +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_attr_pg) +{ + // Local variable and constant definition + fapi2::buffer <uint16_t> l_cplt_ctrl_init; + fapi2::buffer<uint32_t> l_attr_pg; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_common_cplt_ctrl_action_function: Entering ..."); + + l_attr_pg = i_attr_pg; + l_attr_pg.invert(); + l_attr_pg.extractToRight<20, 11>(l_cplt_ctrl_init); + + // Not needed as have only nest chiplet (no dual clock controller) Bit 62 ->0 + // + FAPI_DBG("Drop partial good fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + l_data64.writeBit<PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE> + (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_cplt_ctrl_init + l_data64.insertFromRight<4, 11>(l_cplt_ctrl_init); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_DBG("reset abistclk_muxsel and syncclk_muxsel"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>(); + //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_common_cplt_ctrl_action_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief will force all chiplets out of flush +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_flushmode(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_common_flushmode: Entering ..."); + + FAPI_DBG("Clear flush_inhibit to go in to flush mode"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_common_flushmode: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief get children for all chiplets : Perv, Nest +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[out] o_pg_vector vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_get_pg_vector(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + fapi2::buffer<uint64_t>& o_pg_vector) +{ + fapi2::buffer<uint8_t> l_read_attrunitpos; + FAPI_INF("p9_sbe_common_get_pg_vector: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chip, + l_read_attrunitpos)); + + if ( l_read_attrunitpos == 0x01 ) + { + o_pg_vector.setBit<0>(); + } + + if ( l_read_attrunitpos == 0x02 ) + { + o_pg_vector.setBit<1>(); + } + + if ( l_read_attrunitpos == 0x03 ) + { + o_pg_vector.setBit<2>(); + } + + if ( l_read_attrunitpos == 0x04 ) + { + o_pg_vector.setBit<3>(); + } + + if ( l_read_attrunitpos == 0x05 ) + { + o_pg_vector.setBit<4>(); + } + + FAPI_INF("p9_sbe_common_get_pg_vector: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --Setting Scan ratio +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_common_set_scan_ratio: Entering ..."); + + //Setting OPCG_ALIGN register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (0xE0); //OPCG_ALIGN.SCAN_RATIO = 0xE0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64)); + + FAPI_INF("p9_sbe_common_set_scan_ratio: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H new file mode 100644 index 00000000..f3876594 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H @@ -0,0 +1,90 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_common.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_common.H +/// +/// @brief Common Modules for SBE +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_COMMON_H_ +#define _P9_SBE_COMMON_H_ + + +#include <fapi2.H> + + +fapi2::ReturnCode p9_sbe_common_align_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets); + +fapi2::ReturnCode p9_sbe_common_check_cc_status_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types); + +fapi2::ReturnCode p9_sbe_common_check_checkstop_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer<uint64_t> + i_regions, + const fapi2::buffer<uint64_t> i_clock_status, + const bool i_reg, + const fapi2::buffer<uint8_t> i_clock_cmd, + fapi2::buffer<uint64_t>& o_exp_clock_status); + +fapi2::ReturnCode p9_sbe_common_clock_start_allRegions(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_anychiplet); + +fapi2::ReturnCode p9_sbe_common_clock_start_stop(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const bool i_startslave, + const bool i_startmaster, + const fapi2::buffer<uint64_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types); + +fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_attr_pg); + +fapi2::ReturnCode p9_sbe_common_flushmode(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_common_get_pg_vector(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + fapi2::buffer<uint64_t>& o_pg_vector); + +fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C new file mode 100644 index 00000000..d9a3f2d5 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_enable_seeprom.C +/// +/// @brief SBE enable SEEPROM (runs from OTPROM) +/// +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_enable_seeprom.H" +fapi2::ReturnCode p9_sbe_enable_seeprom(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_enable_seeprom: Entering ..."); + + FAPI_DBG("p9_sbe_enable_seeprom: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H new file mode 100644 index 00000000..00a5ebc6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_enable_seeprom.H +/// +/// @brief SBE enable SEEPROM (runs from OTPROM) +/// +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ENABLE_SEEPROM_H_ +#define _P9_SBE_ENABLE_SEEPROM_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_enable_seeprom_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Check SBE Vital Register for selected SEEPROM image +/// -- Update SBE FI2C_E0_PARAM register +/// -- Check for valid SEEPROM image +/// -- Branch to SEEPROM +/// +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_enable_seeprom(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C new file mode 100644 index 00000000..25d61ad0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C @@ -0,0 +1,154 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gear_switcher.C +/// +/// @brief Modules for I2C Bit rate divisor setting +/// And stop sequence on I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_gear_switcher.H" + +#include "p9_misc_scom_addresses.H" +#include "p9_perv_scom_addresses.H" + + +enum P9_SBE_GEAR_SWITCHER_Private_Constants +{ + DEFAULT_MB_BIT_RATE_DIVISOR = 0x00000000, + BUS_STATUS_BUSY_POLL_COUNT = 64 +}; + +/// @brief --adjust I2C bit rate divisor setting in I2CM B mode reg +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_scratch_reg = 0; + uint16_t l_mb_bit_rate_divisor = 0; + FAPI_DBG("Entering ..."); + + FAPI_INF("Check Mailbox for Valid I2C bit rate divisor setting"); + //Getting SCRATCH_REGISTER_2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2 + + if ( !l_read_scratch_reg ) + { + FAPI_INF("Set with Default value if Mailbox empty"); + //Setting MODE_REGISTER_B register value + //PIB.MODE_REGISTER_B = DEFAULT_MB_BIT_RATE_DIVISOR + FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B, + DEFAULT_MB_BIT_RATE_DIVISOR)); + } + else + { + l_read_scratch_reg.extractToRight<0, 16>(l_mb_bit_rate_divisor); + + FAPI_INF("Adjust I2C bit rate divisor setting in I2CM B Mode Reg"); + //Setting MODE_REGISTER_B register value + //PIB.MODE_REGISTER_B = l_mb_bit_rate_divisor + FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B, + l_mb_bit_rate_divisor)); + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --send a stop sequence on I2C +/// --poll for stop command completion +/// --check for magic number +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_read_attr = 0; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_DBG("Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BACKUP_SEEPROM_SELECT, i_target_chip, + l_read_attr)); + + // WRITE Control register + // enable enhance mode + // Point to port_0 where the Primary SEEPROM Sits + FAPI_INF("Send a STOP sequence on I2C"); + //Setting CONTROL_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64)); + l_data64.setBit<3>(); //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_BIT_WITHSTOP_0 = 1 + //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_PORT_NUMBER_0 = l_read_attr + l_data64.insertFromRight<18, 5>(l_read_attr); + l_data64.setBit<26>(); //PIB.CONTROL_REGISTER_B.ENH_MODE_0 = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64)); + + FAPI_INF("Poll for stop command completion"); + l_timeout = BUS_STATUS_BUSY_POLL_COUNT; + + //UNTIL STATUS_REGISTER_B.BUS_STATUS_BUSY_0 == 0 + while (l_timeout != 0) + { + //Getting STATUS_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64)); + //bool l_poll_data = PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0 + bool l_poll_data = l_data64.getBit<44>(); + + if (l_poll_data == 0) + { + break; + } + + --l_timeout; + } + + FAPI_INF("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::BUS_STATUS_BUSY_0(), + "ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0"); + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H new file mode 100644 index 00000000..845b68e9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gear_switcher.H +/// +/// @brief Modules for I2C Bit rate divisor setting +/// And stop sequence on I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_GEAR_SWITCHER_H_ +#define _P9_SBE_GEAR_SWITCHER_H_ + + +#include <fapi2.H> + + +fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C new file mode 100644 index 00000000..ce8302a9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C @@ -0,0 +1,288 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_initf.C +/// +/// @brief Load time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#include "p9_sbe_gptr_time_initf.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + + FAPI_INF("p9_sbe_gptr_time_initf: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST> + (fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Scan mc_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_gptr), + "Error from putRing (mc_gptr)"); + FAPI_DBG("Scan mc_iom01_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_gptr), + "Error from putRing (mc_iom01_gptr)"); + FAPI_DBG("Scan mc_iom23_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_gptr), + "Error from putRing (mc_iom23_gptr)"); + FAPI_DBG("Scan mc_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_gptr), + "Error from putRing (mc_pll_gptr)"); + FAPI_DBG("Scan mc_time ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_time), + "Error from putRing (mc_time)"); + } + + for( auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + ( fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + + if ((l_attr_chip_unit_pos == 0x9))/* OBUS0 Chiplet */ + { + FAPI_DBG("Scan ob0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_gptr), + "Error from putRing (ob0_gptr)"); + FAPI_DBG("Scan ob0_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_pll_gptr), + "Error from putRing (ob0_pll_gptr)"); + FAPI_DBG("Scan ob0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_time), + "Error from putRing (ob0_time)"); + } + + if ((l_attr_chip_unit_pos == 0xA))/* OBUS1 Chiplet */ + { + FAPI_DBG("Scan ob1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_gptr), + "Error from putRing (ob1_gptr)"); + FAPI_DBG("Scan ob1_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_pll_gptr), + "Error from putRing (ob1_pll_gptr)"); + FAPI_DBG("Scan ob1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_time), + "Error from putRing (ob1_time)"); + } + + if ((l_attr_chip_unit_pos == 0xB))/* OBUS2 Chiplet */ + { + FAPI_DBG("Scan ob2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_gptr), + "Error from putRing (ob2_gptr)"); + FAPI_DBG("Scan ob2_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_pll_gptr), + "Error from putRing (ob2_pll_gptr)"); + FAPI_DBG("Scan ob2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_time), + "Error from putRing (ob2_time)"); + } + + if ((l_attr_chip_unit_pos == 0xC))/* OBUS3 Chiplet */ + { + FAPI_DBG("Scan ob3_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_gptr), + "Error from putRing (ob3_gptr)"); + FAPI_DBG("Scan ob3_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_pll_gptr), + "Error from putRing (ob3_pll_gptr)"); + FAPI_DBG("Scan ob3_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_time), + "Error from putRing (ob3_time)"); + } + + if ((l_attr_chip_unit_pos == 0x6))/* XBUS Chiplet */ + { + FAPI_DBG("Scan xb_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_gptr), + "Error from putRing (xb_gptr)"); + FAPI_DBG("Scan xb_io1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_gptr), + "Error from putRing (xb_io1_gptr)"); + FAPI_DBG("Scan xb_io2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_gptr), + "Error from putRing (xb_io2_gptr)"); + FAPI_DBG("Scan xb_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_pll_gptr), + "Error from putRing (xb_pll_gptr)"); + FAPI_DBG("Scan xb_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_time), + "Error from putRing (xb_time)"); + FAPI_DBG("Scan xb_io1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_time), + "Error from putRing (xb_io1_time)"); + FAPI_DBG("Scan xb_io2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_time), + "Error from putRing (xb_io2_time)"); + } + + if ((l_attr_chip_unit_pos == 0xD))/* PCI0 Chiplet */ + { + FAPI_DBG("Scan pci0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_gptr), + "Error from putRing (pci0_gptr)"); + FAPI_DBG("Scan pci0_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_pll_gptr), + "Error from putRing (pci0_pll_gptr)"); + FAPI_DBG("Scan pci0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_time), + "Error from putRing (pci0_time)"); + } + + if ((l_attr_chip_unit_pos == 0xE))/* PCI1 Chiplet */ + { + FAPI_DBG("Scan pci1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_gptr), + "Error from putRing (pci1_gptr)"); + FAPI_DBG("Scan pci1_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_pll_gptr), + "Error from putRing (pci1_pll_gptr)"); + FAPI_DBG("Scan pci1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_time), + "Error from putRing (pci1_time)"); + } + + if ((l_attr_chip_unit_pos == 0xF))/* PCI2 Chiplet */ + { + FAPI_DBG("Scan pci2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_gptr), + "Error from putRing (pci2_gptr)"); + FAPI_DBG("Scan pci2_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_pll_gptr), + "Error from putRing (pci2_pll_gptr)"); + FAPI_DBG("Scan pci2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_time), + "Error from putRing (pci2_time)"); + } + + if ((l_attr_chip_unit_pos == 0x2))/* N0 Chiplet */ + { + FAPI_DBG("Scan n0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_gptr), + "Error from putRing (n0_gptr)"); + FAPI_DBG("Scan n0_nx_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_gptr), + "Error from putRing (n0_nx_gptr)"); + FAPI_DBG("Scan n0_cxa0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_gptr), + "Error from putRing (n0_cxa0_gptr)"); + FAPI_DBG("Scan n0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_time), + "Error from putRing (n0_time)"); + FAPI_DBG("Scan n0_nx_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_time), + "Error from putRing (n0_nx_time)"); + FAPI_DBG("Scan n0_cxa0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_time), + "Error from putRing (n0_cxa0_time)"); + } + + if ((l_attr_chip_unit_pos == 0x3))/* N1 Chiplet */ + { + FAPI_DBG("Scan n1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_gptr), + "Error from putRing (n1_gptr)"); + FAPI_DBG("Scan n1_ioo0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_gptr), + "Error from putRing (n1_ioo0_gptr)"); + FAPI_DBG("Scan n1_ioo1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_gptr), + "Error from putRing (n1_ioo1_gptr)"); + FAPI_DBG("Scan n1_mcs23_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_gptr), + "Error from putRing (n1_mcs23_gptr)"); + FAPI_DBG("Scan n1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_time), + "Error from putRing (n1_time)"); + FAPI_DBG("Scan n1_ioo0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_time), + "Error from putRing (n1_ioo0_time)"); + FAPI_DBG("Scan n1_ioo1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_time), + "Error from putRing (n1_ioo1_time)"); + FAPI_DBG("Scan n1_mcs23_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_time), + "Error from putRing (n1_mcs23_time)"); + } + + if ((l_attr_chip_unit_pos == 0x4))/* N2 Chiplet */ + { + FAPI_DBG("Scan n2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_gptr), + "Error from putRing (n2_gptr)"); + FAPI_DBG("Scan n2_psi_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_gptr), + "Error from putRing (n2_psi_gptr)"); + FAPI_DBG("Scan n2_cxa1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_gptr), + "Error from putRing (n2_cxa1_gptr)"); + FAPI_DBG("Scan n2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_time), + "Error from putRing (n2_time)"); + FAPI_DBG("Scan n2_cxa1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_time), + "Error from putRing (n2_cxa1_time)"); + } + + if ((l_attr_chip_unit_pos == 0x5))/* N3 Chiplet */ + { + FAPI_DBG("Scan n3_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_gptr), + "Error from putRing (n3_gptr)"); + FAPI_DBG("Scan n3_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_time), + "Error from putRing (n3_time)"); + FAPI_DBG("Scan n3_np_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_gptr), + "Error from putRing (n3_np_gptr)"); + FAPI_DBG("Scan n3_mcs01_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_gptr), + "Error from putRing (n3_mcs01_gptr)"); + FAPI_DBG("Scan n3_mcs01_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_time), + "Error from putRing (n3_mcs01_time)"); + FAPI_DBG("Scan n3_np_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_time), + "Error from putRing (n3_np_time)"); + } + } + +fapi_try_exit: + FAPI_INF("p9_sbe_gptr_time_initf: Exiting ..."); + return fapi2::current_err; + +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H new file mode 100644 index 00000000..5a048f1d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_initf.H +/// +/// @brief Load time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_GPTR_TIME_INITF_H_ +#define _P9_SBE_GPTR_TIME_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_gptr_time_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Scan all rings on all enabled chiplets (except for TP) +/// Load Time and GPTR rings for all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C new file mode 100644 index 00000000..ff4bde17 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_repr_initf.C +/// +/// @brief Scan0 and Load repair, time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_gptr_time_repr_initf.H" + +#include "p9_perv_scom_addresses.H" +#include "p9_perv_sbe_cmn.H" + + +enum P9_SBE_GPTR_TIME_REPR_INITF_Private_Constants +{ + REGIONS_EXCEPT_VITAL = 0x7FF, + SCAN_TYPES_TIME_GPTR_REPR = 0x230 +}; + +static fapi2::ReturnCode +p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + auto l_perv_functional_vector = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_STATE_FUNCTIONAL); + FAPI_DBG("Entering ..."); + + for (auto l_chplt_trgt : l_perv_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, + l_attr_chip_unit_pos)); + + if (!((l_attr_chip_unit_pos == 0x07 + || l_attr_chip_unit_pos == 0x08/* McChiplet */) || + (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03 + || l_attr_chip_unit_pos == 0x04 + || l_attr_chip_unit_pos == 0x05/* NestChiplet */) || + (l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A + || l_attr_chip_unit_pos == 0x0B + || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) || + (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E + || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) || + (l_attr_chip_unit_pos == 0x06/* XbusChiplet */))) + { + continue; + } + + FAPI_INF("Call sbe_gptr_time_repr_initf_scan0_and_ring_module_function"); + FAPI_TRY(p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function( + l_chplt_trgt)); + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Scan 0 on time, repair, gptr on all enabled chiplets +/// scan initialize GPTR,TIME and REPR Rings +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode +p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("Entering ..."); + + FAPI_INF("Check for chiplet enable"); + //Getting NET_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); + l_read_reg = l_data64.getBit<0>(); //l_read_reg = NET_CTRL0.CHIPLET_ENABLE + + if ( l_read_reg ) + { + FAPI_INF("run scan0 module for regions except vital scan types GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, REGIONS_EXCEPT_VITAL, + SCAN_TYPES_TIME_GPTR_REPR)); + + + //TODO:Load Ring Module : Scan initialize PLL BNDY chain + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H new file mode 100644 index 00000000..da24195e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_repr_initf.H +/// +/// @brief Scan0 and Load repair, time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_GPTR_TIME_REPR_INITF_H_ +#define _P9_SBE_GPTR_TIME_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_gptr_time_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Scan 0 all rings on all enabled chiplets (except for TP) +/// Load Repair, Time and GPTR rings for all enabled chiplets +/// -- All chip customization data is within the repair and time rings -- array repair, DTS setting +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C new file mode 100644 index 00000000..00e00d24 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C @@ -0,0 +1,134 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_io_initf.C +/// +/// @brief Initialize necessary latches in IP chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_io_initf.H" +#include "p9_perv_scom_addresses.H" +#include "p9_perv_scom_addresses_fld.H" + +fapi2::ReturnCode p9_sbe_io_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_io_initf: Entering ..."); + uint8_t l_attr_chip_unit_pos = 0; + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + +#if 0 + { + // PCIx FURE rings require deterministic scan enable + // no current plan to scan these during mainline IPL, but recipe is below if needed + fapi2::buffer<uint64_t> l_data64; + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC>(); + + if (l_attr_chip_unit_pos == 0xD)/* PCI0 Chiplet */ + { + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI0_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan pci0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_fure), + "Error from putRing (pci0_fure)"); + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI0_CPLT_CTRL0_CLEAR, l_data64)); + } + + if (l_attr_chip_unit_pos == 0xE)/* PCI1 Chiplet */ + { + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI1_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan pci1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_fure), + "Error from putRing (pci1_fure)"); + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI1_CPLT_CTRL0_CLEAR, l_data64)); + } + + if (l_attr_chip_unit_pos == 0xF)/* PCI2 Chiplet */ + { + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI2_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan pci2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_fure), + "Error from putRing (pci2_fure)"); + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI2_CPLT_CTRL0_CLEAR, l_data64)); + } + } +#endif + + if (l_attr_chip_unit_pos == 0x9)/* OBUS0 Chiplet */ + { + FAPI_DBG("Scan ob0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_fure), + "Error from putRing (ob0_fure)"); + } + + if (l_attr_chip_unit_pos == 0xA)/* OBUS1 Chiplet */ + { + FAPI_DBG("Scan ob1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_fure), + "Error from putRing (ob1_fure)"); + } + + if (l_attr_chip_unit_pos == 0xB)/* OBUS2 Chiplet */ + { + FAPI_DBG("Scan ob2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_fure), + "Error from putRing (ob2_fure)"); + } + + if (l_attr_chip_unit_pos == 0xC)/* OBUS3 Chiplet */ + { + FAPI_DBG("Scan ob3_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_fure), + "Error from putRing (ob3_fure)"); + } + + if (l_attr_chip_unit_pos == 0x6)/* XBUS Chiplet */ + { + FAPI_DBG("Scan xb_io1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_fure), + "Error from putRing (xb_io1_fure)"); + FAPI_DBG("Scan xb_io2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_fure), + "Error from putRing (xb_io2_fure)"); + FAPI_DBG("Scan xb_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_fure), + "Error from putRing (xb_fure)"); + } + } + +fapi_try_exit: + FAPI_INF("p9_sbe_io_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H new file mode 100644 index 00000000..c1f186bd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_io_initf.H +/// +/// @brief Initialize necessary latches in IP chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_IO_INITF_H_ +#define _P9_SBE_IO_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_io_initf_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Apply init file for IO (Xbus, Abus and Pcie) chiplets. +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_io_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C new file mode 100644 index 00000000..25336c49 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_lpc_init.C +/// +/// @brief procedure to initialize LPC to enable communictation to PNOR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_lpc_init.H" + +#include "p9_perv_scom_addresses.H" +#include "p9_perv_scom_addresses_fld.H" + +fapi2::ReturnCode p9_sbe_lpc_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("p9_sbe_lpc_init: Entering ..."); + + // set LPC clock mux select to internal clock + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + l_data64.setBit<1>(); //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_OR, l_data64)); + + // set LPC clock mux select to external clock + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + l_data64.setBit<1>(); //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_CLEAR, l_data64)); + + //Settting registers to do an LPC functional reset + l_data64.flush<0>().setBit<CPLT_CONF1_TC_LP_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_OR, l_data64)); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_CLEAR, l_data64)); + + FAPI_DBG("p9_sbe_lpc_init: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H new file mode 100644 index 00000000..eabe73f1 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_lpc_init.H +/// +/// @brief procedure to initialize LPC to enable communictation to PNOR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_LPC_INIT_H_ +#define _P9_SBE_LPC_INIT_H_ + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_lpc_init_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief LPC init to enable connection to PNOR +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + const uint32_t CPLT_CONF1_TC_LP_RESET = 12; + fapi2::ReturnCode p9_sbe_lpc_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C new file mode 100644 index 00000000..63bbe75e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C @@ -0,0 +1,113 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_enable_ridi.C +/// +/// @brief Enable ridi controls for NEST logic +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_enable_ridi.H" + +#include "p9_perv_scom_addresses.H" + +static fapi2::ReturnCode p9_sbe_nest_enable_ridi_net_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_nest_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + auto l_perv_functional_vector = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_STATE_FUNCTIONAL); + FAPI_DBG("p9_sbe_nest_enable_ridi: Entering ..."); + + for (auto l_chplt_trgt : l_perv_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, + l_attr_chip_unit_pos)); + + if (!((l_attr_chip_unit_pos == 0x07 + || l_attr_chip_unit_pos == 0x08/* McChiplet */) || + (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03 + || l_attr_chip_unit_pos == 0x04 + || l_attr_chip_unit_pos == 0x05/* NestChiplet */))) + { + continue; + } + + FAPI_INF("Call p9_sbe_nest_enable_ridi_net_ctrl_action_function"); + FAPI_TRY(p9_sbe_nest_enable_ridi_net_ctrl_action_function(l_chplt_trgt)); + } + + FAPI_DBG("p9_sbe_nest_enable_ridi: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Enable Drivers/Recievers of Nest chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_enable_ridi_net_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("p9_sbe_nest_enable_ridi_net_ctrl_action_function: Entering ..."); + + FAPI_INF("Check for chiplet enable"); + //Getting NET_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); + l_read_reg = l_data64.getBit<0>(); //l_read_reg = NET_CTRL0.CHIPLET_ENABLE + + if ( l_read_reg ) + { + FAPI_INF("Enable Recievers, Drivers DI1 & DI2"); + //Setting NET_CTRL0 register value + l_data64.flush<0>(); + l_data64.setBit<19>(); //NET_CTRL0.RI_N = 1 + l_data64.setBit<20>(); //NET_CTRL0.DI1_N = 1 + l_data64.setBit<21>(); //NET_CTRL0.DI2_N = 1 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64)); + } + + FAPI_DBG("p9_sbe_nest_enable_ridi_net_ctrl_action_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H new file mode 100644 index 00000000..6c7b2dfb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_enable_ridi.H +/// +/// @brief Enable ridi controls for NEST logic +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_ENABLE_RIDI_H_ +#define _P9_SBE_NEST_ENABLE_RIDI_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_nest_enable_ridi_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Enable Drivers/Receivers of Nest Chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C new file mode 100644 index 00000000..434e0137 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C @@ -0,0 +1,135 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_initf.C +/// +/// @brief Scan rings for Nest and Mc chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_initf.H" +#include "p9_perv_scom_addresses.H" +#include "p9_perv_scom_addresses_fld.H" + +fapi2::ReturnCode p9_sbe_nest_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("Entering ..."); + uint8_t l_attr_chip_unit_pos = 0; + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + + if (l_attr_chip_unit_pos == 0x2)/* N0 Chiplet */ + { + FAPI_DBG("Scan n0_cxa_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_fure), + "Error from putRing (n0_cxa0_fure)"); + FAPI_DBG("Scan n0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_fure), + "Error from putRing (n0_fure)"); + FAPI_DBG("Scan n0_nx_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_fure), + "Error from putRing (n0_nx_fure)"); + } + + if (l_attr_chip_unit_pos == 0x3)/* N1 Chiplet */ + { + FAPI_DBG("Scan n1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_fure), + "Error from putRing (n1_fure)"); + FAPI_DBG("Scan n1_ioo0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_fure), + "Error from putRing (n1_ioo0_fure)"); + FAPI_DBG("Scan n1_ioo1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_fure), + "Error from putRing (n1_ioo1_fure)"); + FAPI_DBG("Scan n1_mcs23_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_fure), + "Error from putRing (n1_mcs23_fure)"); + } + + if (l_attr_chip_unit_pos == 0x4)/* N2 Chiplet */ + { + FAPI_DBG("Scan n2_cxa1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_fure), + "Error from putRing (n2_cxa1_fure)"); + FAPI_DBG("Scan n2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_fure), + "Error from putRing (n2_fure)"); + FAPI_DBG("Scan n2_psi_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_fure), + "Error from putRing (n2_psi_fure)"); + } + + if (l_attr_chip_unit_pos == 0x05)/* N3 Chiplet */ + { + FAPI_DBG("Scan n3_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_fure), + "Error from putRing (n3_fure)"); + FAPI_DBG("Scan n3_mcs01_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_fure), + "Error from putRing (n3_mcs01_fure)"); + FAPI_DBG("Scan n3_np_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_fure), + "Error from putRing (n3_np_fure)"); + } + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_fure)); +#if 0 + { + // MC IOMxx FURE rings require deterministic scan enable + // no current plan to scan these during mainline IPL, but recipe is below if needed + fapi2::buffer<uint64_t> l_data64; + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC>(); + FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan mc_iom01_fure ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_fure), + "Error from putRing (mc_iom01_fure)"); + FAPI_DBG("Scan mc_iom23_fure ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_fure), + "Error from putRing (mc_iom23_fure)"); + FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_CLEAR, l_data64)); + } +#endif + + } + +fapi_try_exit: + FAPI_INF("Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H new file mode 100644 index 00000000..90a8321e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_initf.C +/// +/// @brief Scan rings for Nest and Mc chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_NEST_INITF_H_ +#define _P9_SBE_NEST_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_nest_initf_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief apply init file +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C new file mode 100644 index 00000000..d0737f78 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C @@ -0,0 +1,388 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_startclocks.C +/// +/// @brief start PB and Nest clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_startclocks.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_NEST_STARTCLOCKS_Private_Constants +{ + CLOCK_CMD = 0x1, + STARTSLAVE = 0x1, + STARTMASTER = 0x1, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE, + CLOCK_TYPES = 0x7, + DONT_STARTMASTER = 0x0, + DONT_STARTSLAVE = 0x0 +}; + +static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg); + +static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_nest_startclocks_nest_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +fapi2::ReturnCode p9_sbe_nest_startclocks(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_read_attr = 0; + fapi2::buffer<uint8_t> l_read_flush_attr; + fapi2::buffer<uint32_t> l_attr_pg; + fapi2::buffer<uint64_t> l_pg_vector; + fapi2::buffer<uint64_t> l_clock_regions; + fapi2::buffer<uint64_t> l_n3_clock_regions; + fapi2::buffer<uint16_t> l_ccstatus_regions; + fapi2::buffer<uint16_t> l_n3_ccstatus_regions; + FAPI_INF("p9_sbe_nest_startclocks: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE, i_target_chip, + l_read_flush_attr)); + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_target_cplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_n3_clock_regions)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_target_cplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_n3_ccstatus_regions)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + FAPI_INF("Reading ATTR_MC_SYNC_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); + + fapi2::TargetFilter l_nest_filter, l_nest_tp_filter, l_dd1_filter_without_N3; + + if (l_read_attr) + { + l_nest_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST); + l_nest_tp_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC + | fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP); + l_dd1_filter_without_N3 = static_cast<fapi2::TargetFilter> + (fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST | + fapi2::TARGET_FILTER_TP); + } + else + { + l_nest_filter = fapi2::TARGET_FILTER_ALL_NEST; + l_nest_tp_filter = static_cast<fapi2::TargetFilter> + (fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP); + l_dd1_filter_without_N3 = static_cast<fapi2::TargetFilter> + (fapi2::TARGET_FILTER_NEST_NORTH | fapi2::TARGET_FILTER_NEST_SOUTH | + fapi2::TARGET_FILTER_NEST_EAST | fapi2::TARGET_FILTER_TP); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for N3"); + FAPI_TRY(p9_sbe_nest_startclocks_N3_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for N0,N1,N2"); + FAPI_TRY(p9_sbe_nest_startclocks_nest_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + if ( l_read_attr ) + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for MC"); + FAPI_TRY(p9_sbe_nest_startclocks_mc_fence_drop(l_trgt_chplt, l_pg_vector)); + } + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_nest_filter, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_nest_startclocks_get_attr_pg(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Call common_cplt_ctrl_action_function for Nest and Mc chiplets"); + FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_nest_tp_filter, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Call module align chiplets for Nest and Mc chiplets"); + FAPI_TRY(p9_sbe_common_align_chiplets(l_trgt_chplt)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Regions value: %#018lX", l_clock_regions); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_clock_regions)); + + FAPI_DBG("Call module clock start stop for N0, N1, N2"); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, STARTSLAVE, + DONT_STARTMASTER, l_clock_regions, CLOCK_TYPES)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_common_clock_start_stop(l_target_cplt, CLOCK_CMD, + DONT_STARTSLAVE, STARTMASTER, l_n3_clock_regions, CLOCK_TYPES)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_ccstatus_regions)); + FAPI_DBG("Regions value: %#018lX", l_ccstatus_regions); + + FAPI_DBG("Call clockstatus check function for N0,N1,N2"); + FAPI_TRY(p9_sbe_common_check_cc_status_function(l_trgt_chplt, CLOCK_CMD, + l_ccstatus_regions, CLOCK_TYPES)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Call clockstatus check function for N3"); + FAPI_TRY(p9_sbe_common_check_cc_status_function(l_target_cplt, CLOCK_CMD, + l_n3_ccstatus_regions, CLOCK_TYPES)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + if ( l_read_attr ) + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_clock_regions)); + FAPI_DBG("Regions value: %#018lX", l_clock_regions); + + FAPI_DBG("Call module clock start stop for MC01, MC23."); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, + DONT_STARTSLAVE, DONT_STARTMASTER, l_clock_regions, CLOCK_TYPES)); + } + } + + if ( l_read_flush_attr ) + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_dd1_filter_without_N3, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("clear flush_inhibit to go into flush mode"); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); + } + } + else + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_nest_tp_filter, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("clear flush_inhibit to go into flush mode"); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); + } + } + + FAPI_INF("p9_sbe_nest_startclocks: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for OB chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_nest_startclocks_N3_fence_drop: Entering ..."); + + if ( i_pg_vector.getBit<0>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_nest_startclocks_N3_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief get attr_pg for the chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[out] o_attr_pg ATTR_PG for the chiplet +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg) +{ + FAPI_INF("p9_sbe_nest_startclocks_get_attr_pg: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, o_attr_pg)); + + FAPI_INF("p9_sbe_nest_startclocks_get_attr_pg: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for MC +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + uint8_t l_read_attrunitpos = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_nest_startclocks_mc_fence_drop: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, + l_read_attrunitpos)); + + if ( l_read_attrunitpos == 0x07 ) + { + if ( i_pg_vector.getBit<4>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + } + + if ( l_read_attrunitpos == 0x08 ) + { + if ( i_pg_vector.getBit<2>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + } + + FAPI_INF("p9_sbe_nest_startclocks_mc_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for pcie chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_nest_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_nest_startclocks_nest_fence_drop: Entering ..."); + + if ( i_pg_vector.getBit<4>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_nest_startclocks_nest_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H new file mode 100644 index 00000000..efc40a97 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H @@ -0,0 +1,66 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_startclocks.H +/// +/// @brief start PB and Nest clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_STARTCLOCKS_H_ +#define _P9_SBE_NEST_STARTCLOCKS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_nest_startclocks_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --drop vital fence +/// --reset abstclk muxsel and syncclk muxsel +/// --Module align chiplets +/// --Module clock start stop +/// --Check clock stat SL, NSL , ARY +/// --drop chiplet fence +/// --check checkstop register +/// --clear flush inhibit to go into flush mode +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_startclocks(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C new file mode 100644 index 00000000..79e0c0e3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C @@ -0,0 +1,91 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_initf.C +/// +/// @brief apply initfile for level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_npll_initf.H" + +fapi2::ReturnCode p9_sbe_npll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_npll_initf: Entering ..."); + + uint8_t l_read_attr = 0; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + RingID ringID = perv_pll_bndy_bucket_1; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM , l_read_attr), + "Error from FAPI_ATTR_GET (ATTR_NEST_PLL_BUCKET)"); + + switch(l_read_attr) + { + case 1: + ringID = perv_pll_bndy_bucket_1; + break; + + case 2: + ringID = perv_pll_bndy_bucket_2; + break; + + case 3: + ringID = perv_pll_bndy_bucket_3; + break; + + case 4: + ringID = perv_pll_bndy_bucket_4; + break; + + case 5: + ringID = perv_pll_bndy_bucket_5; + break; + + default: + FAPI_ASSERT(false, + fapi2::P9_SBE_NPLL_INITF_UNSUPPORTED_BUCKET(). + set_TARGET(i_target_chip). + set_BUCKET_INDEX(l_read_attr), + "Unsupported Nest PLL bucket value!"); + } + + FAPI_DBG("Scan perv_pll_bndy_bucket_%d ring", l_read_attr); + FAPI_TRY(fapi2::putRing(i_target_chip, ringID, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (perv_pll_bndy, ringID: %d)", ringID); + +fapi_try_exit: + FAPI_INF("p9_sbe_npll_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H new file mode 100644 index 00000000..025d2377 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_initf.H +/// +/// @brief apply initfile for level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NPLL_INITF_H_ +#define _P9_SBE_NPLL_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_npll_initf_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --run scan0 module (scan region = PLL, scan_types = GPTR) +/// --run scan0 module (scan region = PLL, scan_types = BNDY/FUNC) +/// --Scan initialize PLL BNDY chain (chiplet = PERV, scan ring = PLL, scan type = BNDY) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_npll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C new file mode 100644 index 00000000..331fa528 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C @@ -0,0 +1,242 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_setup.C +/// +/// @brief scan initialize level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_npll_setup.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> + + +enum P9_SBE_NPLL_SETUP_Private_Constants +{ + NS_DELAY = 5000000, // unit is nano seconds + SIM_CYCLE_DELAY = 1000 // unit is sim cycles +}; + +fapi2::ReturnCode p9_sbe_npll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + uint8_t l_read_attr = 0; + fapi2::buffer<uint64_t> l_data64_root_ctrl8; + fapi2::buffer<uint64_t> l_data64_perv_ctrl0; + FAPI_INF("p9_sbe_npll_setup: Entering ..."); + + FAPI_DBG("Reading ROOT_CTRL8 register value"); + //Getting ROOT_CTRL8 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); //l_data64_root_ctrl8 = PIB.ROOT_CTRL8 + + + FAPI_DBG("Reading ATTR_SS_FILTER_BYPASS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, + l_read_attr)); + + if ( l_read_attr == 0x0 ) + { + FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_SS0_PLL_TEST_EN = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + FAPI_DBG("Release SS PLL reset"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_SS0_PLL_RESET = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check SS PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<0>(), + fapi2::SS_PLL_LOCK_ERR() + .set_SS_PLL_READ(l_read_reg), + "ERROR:SS PLL LOCK NOT SET"); + + FAPI_DBG("Release SS PLL Bypass"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_SS0_PLL_BYPASS = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Reading ATTR_CP_FILTER_BYPASS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, + l_read_attr)); + + if ( l_read_attr == 0x0 ) + { + FAPI_DBG("Drop PLL test enable for CP Filter PLL"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT1_PLL_TEST_EN = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + FAPI_DBG("Release CP Filter PLL reset"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT1_PLL_RESET = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<1>(), + fapi2::CP_FILTER_PLL_LOCK_ERR() + .set_CP_FILTER_PLL_READ(l_read_reg), + "ERROR:CP FILTER PLL LOCK NOT SET"); + + FAPI_DBG("Release CP filter PLL Bypass Signal"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT1_PLL_BYPASS = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Reading ATTR_IO_FILTER_BYPASS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, + l_read_attr)); + + if ( l_read_attr == 0x0 ) + { + FAPI_DBG("Drop PLL test enable for IO Filter PLL"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT0_PLL_TEST_EN = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + FAPI_DBG("Release IO Filter PLL reset"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT0_PLL_RESET = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<2>(), + fapi2::IO_FILTER_PLL_LOCK_ERR() + .set_IO_FILTER_PLL_READ(l_read_reg), + "ERROR:IO FILTER PLL LOCK NOT SET"); + + FAPI_DBG("Release IO filter PLL Bypass Signal"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT0_PLL_BYPASS = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Drop PLL test enable for Nest PLL"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + //PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + + FAPI_DBG("Reading ATTR_MC_SYNC_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); + + if ( l_read_attr == 1 ) + { + FAPI_DBG("Set MUX to Nest Clock input"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_PLL_CLKIN_SEL4_DC = 1 + l_data64_root_ctrl8.setBit<PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Release Nest PLL reset"); + //Setting PERV_CTRL0 register value + //PIB.PERV_CTRL0.TP_PLLRST_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check NEST PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<3>(), + fapi2::NEST_PLL_ERR() + .set_NEST_PLL_READ(l_read_reg), + "ERROR:NEST PLL LOCK NOT SET"); + + FAPI_DBG("Release PLL bypass2"); + //Setting PERV_CTRL0 register value + //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + + FAPI_INF("p9_sbe_npll_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H new file mode 100644 index 00000000..b05c7db1 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H @@ -0,0 +1,71 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_setup.H +/// +/// @brief scan initialize level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NPLL_SETUP_H_ +#define _P9_SBE_NPLL_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_npll_setup_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Release PLL test enable for SS, Filt & NEST PLLs +/// --Release SS PLL reset0 +/// --check SS PLL lock +/// --Release SS PLL bypass0 +/// --Release Filter PLL reset1 +/// --check PLL lock for Filter PLLs +/// --Release Filter PLL bypass signals +/// --Switch MC meshs to Nest mesh +/// --Release test_pll_bypass2 +/// --Release Tank PLL reset2 +/// --check Nest PLL lock +/// --Release Tank PLL bypass2 +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_npll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C new file mode 100644 index 00000000..9dc91da6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C @@ -0,0 +1,177 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_repr_initf.C +/// +/// @brief Load Repair rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#include "p9_sbe_repr_initf.H" +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_attr_chip_unit_pos = 0; + FAPI_INF("p9_sbe_repr_initf: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_repr)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + + if (l_attr_chip_unit_pos == 0x9)/* OBUS0 Chiplet */ + { + FAPI_DBG("Scan ob0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_repr), + "Error from putRing (ob0_repr)"); + } + + if (l_attr_chip_unit_pos == 0xA)/* OBUS1 Chiplet */ + { + FAPI_DBG("Scan ob1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_repr), + "Error from putRing (ob1_repr)"); + } + + if (l_attr_chip_unit_pos == 0xB)/* OBUS2 Chiplet */ + { + FAPI_DBG("Scan ob2_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_repr), + "Error from putRing (ob2_repr)"); + } + + if (l_attr_chip_unit_pos == 0xC)/* OBUS3 Chiplet */ + { + FAPI_DBG("Scan ob3_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_repr), + "Error from putRing (ob3_repr)"); + } + + if (l_attr_chip_unit_pos == 0x6)/* XBUS Chiplet */ + { + FAPI_DBG("Scan xb_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_repr), + "Error from putRing (xb_repr)"); + FAPI_DBG("Scan xb_io1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_repr), + "Error from putRing (xb_io1_repr)"); + FAPI_DBG("Scan xb_io2_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_repr), + "Error from putRing (xb_io2_repr)"); + } + + if (l_attr_chip_unit_pos == 0xD)/* PCI0 Chiplet */ + { + FAPI_DBG("Scan pci0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_repr), + "Error from putRing (pci0_repr)"); + } + + if (l_attr_chip_unit_pos == 0xE)/* PCI1 Chiplet */ + { + FAPI_DBG("Scan pci1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_repr), + "Error from putRing (pci1_repr)"); + } + + if (l_attr_chip_unit_pos == 0xF)/* PCI2 Chiplet */ + { + FAPI_DBG("Scan pci2_repr_ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_repr), + "Error from putRing (pci2_repr)"); + } + + if (l_attr_chip_unit_pos == 0x2)/* N0 Chiplet */ + { + FAPI_DBG("Scan n0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_repr), + "Error from putRing (n0_repr)"); + FAPI_DBG("Scan n0_nx_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_repr), + "Error from putRing (n0_nx_repr)"); + FAPI_DBG("Scan n0_cxa0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_repr), + "Error from putRing (n0_cxa0_repr)"); + } + + if (l_attr_chip_unit_pos == 0x3)/* N1 Chiplet */ + { + FAPI_DBG("Scan n1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_repr), + "Error from putRing (n1_repr)"); + FAPI_DBG("Scan n1_ioo0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_repr), + "Error from putRing (n1_ioo0_repr)"); + FAPI_DBG("Scan n1_ioo1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_repr), + "Error from putRing (n1_ioo1_repr)"); + FAPI_DBG("Scan n1_mcs23_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_repr), + "Error from putRing (n1_mcs23_repr)"); + } + + if (l_attr_chip_unit_pos == 0x4)/* N2 Chiplet */ + { + FAPI_DBG("Scan n2_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_repr), + "Error from putRing (n2_repr)"); + FAPI_DBG("Scan n2_cxa1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_repr), + "Error from putRing (n2_cxa1_repr)"); + } + + if (l_attr_chip_unit_pos == 0x5)/* N3 Chiplet */ + { + FAPI_DBG("Scan n3_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_repr), + "Error from putRing (n3_repr)"); + FAPI_DBG("Scan n3_mcs01_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_repr), + "Error from putRing (n3_mcs01_repr)"); + FAPI_DBG("Scan n3_np_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_repr), + "Error from putRing (n3_np_repr)"); + } + } + +fapi_try_exit: + FAPI_INF("p9_sbe_repr_initf: Exiting ..."); + return fapi2::current_err; + +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H new file mode 100644 index 00000000..b5dbbe99 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_repr_initf.C +/// +/// @brief Initialize REPR for PERV chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_REPR_INITF_H_ +#define _P9_SBE_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Scan Repair for all Perv Chiplets except TP, EC, EP +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C new file mode 100644 index 00000000..af7c2299 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C @@ -0,0 +1,494 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_select_ex.C +/// @brief Select the Hostboot core from the available cores on the chip +/// +// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: SBE +/// +/// +/// +/// High-level procedure flow: +/// @verbatim +/// Following MC groups are needed to be setup for istep 4 use: +/// - MC group 3: Core(s) (eg ECs); use EC MC group register 3 +/// - MC group 4: EQ(s); use EQ MC group register 2 +/// - MC group 5: Even EXs; use EQ MC group register 3 +/// - MC group 6: Odd Exs; use EQ MC group register 4 +/// +/// Prerequisite: istep 2 will setup the above groups with ALL the good +/// elements represented. +/// +/// This procedure will REMOVE entities from these groups in SINGLE mode; +/// in ALL mode, the groups are not changed. In either case, the OCC +/// registers are written with the valid configuration. Additionally, +/// default PFET controller delays are written into all configured +/// EC and EQ chiplets so that istep 4 power-on operations will +/// succeed. +/// +/// Parameter indicates single core or all (controlled by Cronus/SBE) +/// +/// loop over functional cores { +/// if mode == SINGLE { +/// if first one { +/// Record the master core, EX and EQ number +/// } +/// else { +/// Remove from MC Group 3 +/// } +/// } +/// Set bits in core and EX scoreboard for later updating the OCC +/// Set default PFET controller delay values into Core +/// } +/// +/// loop over functional EQs { +/// if mode == SINGLE { +/// if not master EQ { +/// Remove from MC Groups 4 +/// for the EXs in the EQ { +/// if not master EX && bit is set in EX scoreboard +/// Remove from MC Group 5 if Even (EX0) +/// Remove from MC Group 6 if Odd (EX1) +/// } +/// Set default PFET controller delay values into EQ +/// } +/// +/// Write resultant scoreboard EQ/Core mask into OCC complex +/// - This is the "master record " of the enabled cores/quad in the system +/// - This is only for during the IPL (will be updated later in step 15) +/// @endverbatim + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- +#include "p9_sbe_select_ex.H" +#include "p9_common_poweronoff.H" + +// ----------------------------------------------------------------------------- +// Definitions +// ----------------------------------------------------------------------------- + +static const uint32_t NUM_EX_PER_EQ = 2; + +static const uint8_t CORE_CHIPLET_START = 0x20; +static const uint8_t CORE_CHIPLET_COUNT = 24; + +static const uint8_t CORE_STOP_MC_GROUP = 3; +static const uint8_t EQ_STOP_MC_GROUP = 4; +static const uint8_t EX_EVEN_STOP_MC_GROUP = 5; +static const uint8_t EX_ODD_STOP_MC_GROUP = 6; +static const uint8_t BROADCAST_GROUP = 7; + +// Use PERV addressses as the accesses to the cores and EQ use PERV targets +static const uint64_t CORE_MC_REG = PERV_MULTICAST_GROUP_3; +static const uint64_t EQ_MC_REG = PERV_MULTICAST_GROUP_2; +static const uint64_t EX_EVEN_MC_REG = PERV_MULTICAST_GROUP_3; +static const uint64_t EX_ODD_MC_REG = PERV_MULTICAST_GROUP_4; + +// Note: in the above, the EX MC groups really live in the EQ chiplet, not the +// core! + +static const uint8_t PERV_EQ_START = 0x10; +static const uint8_t PERV_EQ_COUNT = 6; +static const uint8_t PERV_CORE_START = 0x20; +static const uint8_t PERV_CORE_COUNT = 24; + +// ----------------------------------------------------------------------------- +// Function prototypes +// ----------------------------------------------------------------------------- + +fapi2::ReturnCode select_ex_remove_core_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +fapi2::ReturnCode select_ex_remove_ex_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint32_t i_ex_num); + +fapi2::ReturnCode select_ex_remove_eq_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +// ----------------------------------------------------------------------------- +// Function definitions +// ----------------------------------------------------------------------------- + +// See .H for documentation +fapi2::ReturnCode p9_sbe_select_ex( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9selectex::MODE i_mode) +{ + FAPI_IMP("> p9_sbe_select_ex"); + + fapi2::buffer<uint64_t> l_core_config = 0; + fapi2::buffer<uint64_t> l_quad_config = 0; + fapi2::buffer<uint64_t> l_data64 = 0; + uint8_t attr_force_all = 0; + bool b_single = true; + bool b_host_core_found = false; + bool b_processing_host_core = false; + + uint32_t l_master_ex_num = 0xFF; // invalid EX number initialized + uint32_t l_master_eq_num = 0xFF; // invalid EQ number initialized + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + + auto l_core_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CORES, + fapi2::TARGET_STATE_FUNCTIONAL ); + + auto l_eq_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CACHES, + fapi2::TARGET_STATE_FUNCTIONAL ); + + // Read the "FORCE_ALL" attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, + FAPI_SYSTEM, + attr_force_all)); + + // Set the flow mode and respect the force mode + if (attr_force_all || i_mode == p9selectex::ALL) + { + b_single = false; + FAPI_DBG("All cores mode"); + } + else + { + FAPI_DBG("Single core mode: Number of candidate cores = %d, Number of candidate caches = %d", + l_core_functional_vector.size(), + l_eq_functional_vector.size()); + } + + // Loop through the core functional vector. The first core in the vector + // is going to be the hostboot core as the FAPI platform code is expected + // to return the vector elements in acsending order; thus, the first vector + // entry is the lowest numbered, valid core. + // + // Two buffers track the core and EX configuration as though "ALL" is the + // mode chosen. This is done to reduce conditional processing within the + // vector loop to allow for better prefetch utilization. + + for (auto core : l_core_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + core, + l_attr_chip_unit_pos)); + + // Needed as core is a PERV target + uint32_t l_core_num = static_cast<uint32_t>(l_attr_chip_unit_pos - PERV_CORE_START); + + FAPI_DBG("Functional core l_attr_chip_unit_pos 0x%02X, l_core_num = 0x%02X", + l_attr_chip_unit_pos, l_core_num); + + uint32_t l_ex_num = l_core_num / 2; + uint32_t l_eq_num = l_core_num / 4; + + if (b_single) + { + b_processing_host_core = false; + + if (!b_host_core_found) + { + + l_master_ex_num = l_ex_num; + l_master_eq_num = l_eq_num; + + uint8_t l_short_core_num = static_cast<uint8_t>(l_core_num); + FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_MASTER_CORE, + i_target, + l_short_core_num)); + + uint8_t l_short_ex_num = static_cast<uint8_t>(l_ex_num); + FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_MASTER_EX, + i_target, + l_short_ex_num)); + + FAPI_DBG("MASTER core chiplet %d 0x%02X; EX %d 0x%02X", + l_core_num, l_core_num, + l_master_ex_num, l_master_ex_num); + + b_host_core_found = true; + b_processing_host_core = true; + + } // host_core_found + + // Remove the core from the apppropriate multicast group if not + // the host core + if (!b_processing_host_core) + { + FAPI_TRY(select_ex_remove_core_from_mc_group(core)); + } + + } // Single + + // To save code space in the SBE, the assumption is made that if the core + // is good (eg in the core functional vector), then the EX associated with + // it is also good. No checking is performed on the associated the EX + // targets to check this. + // + // Thus, set the bits in the buffers for the OCC configuration register + // update + FAPI_DBG("core num = %d, ex num = %d", + l_core_num, l_ex_num); + l_core_config.setBit(l_core_num); + l_quad_config.setBit(l_ex_num); + + FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX EX 0x%016llX", + l_core_config, l_quad_config); + + // Write the default PFET Controller Delay values for the Core + // as it will be used for istep 4 + FAPI_DBG("Setting PFET Delays in core %d", l_core_num); + + l_data64.flush<0>() + .insertFromRight<0, 4>(p9power::PFET_DELAY_POWERDOWN_CORE) + .insertFromRight<4, 4>(p9power::PFET_DELAY_POWERUP_CORE); + + FAPI_TRY(fapi2::putScom(core, + C_PPM_PFDLY - 0x20000000, // Create chip address base + l_data64), + "Error: Core PFET Delay register"); + + } // Core loop + + // Process the good EQs + for (auto eq : l_eq_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + eq, + l_attr_chip_unit_pos)); + + // Needed as eq is a PERV target + uint32_t l_eq_num = static_cast<uint32_t>(l_attr_chip_unit_pos - PERV_EQ_START); + + FAPI_DBG("Functional EQ l_attr_chip_unit_pos 0x%02X, l_eq_num = 0x%02X", + l_attr_chip_unit_pos, l_eq_num); + + if (b_single) + { + if (l_eq_num != l_master_eq_num) + { + FAPI_TRY(select_ex_remove_eq_from_mc_group(eq)); + } + + for (auto i = l_eq_num * NUM_EX_PER_EQ; i < (l_eq_num + 1)*NUM_EX_PER_EQ; ++i) + { + FAPI_DBG("ex = %d, master ex = %d, quad bit[%d] = %d", + i, l_master_ex_num, i, l_quad_config.getBit(i)); + + // Remove from MC group if not master EX and configured + if ((i != l_master_ex_num) && l_quad_config.getBit(i)) + { + FAPI_TRY(select_ex_remove_ex_from_mc_group(eq, i)); + } + } + + } // Single + + FAPI_DBG("Setting PFET Delays in EQ %d", l_eq_num); + + // Write the default PFET Controller Delay values for the EQs + // that will be used for istep 4 + l_data64.flush<0>() + .insertFromRight<0, 4>(p9power::PFET_DELAY_POWERDOWN_EQ) + .insertFromRight<4, 4>(p9power::PFET_DELAY_POWERUP_EQ); + + FAPI_TRY(fapi2::putScom(eq, + EQ_PPM_PFDLY - 0x10000000, // Create chip address base + l_data64), + "Error: EQ PFET Delay register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + + + } // EQ loop + + + // Write to the OCC Core Configuration Status Register + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_CCSR_SCOM2, l_core_config)); + + // Write to the OCC Quad Configuration Status Register + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QCSR_SCOM2, l_quad_config)); + + // Write default value the OCC Quad Status Status Register + l_data64.flush<0>() + .setBit<0, 12>() // L2 Stopped + .setBit<14, 6>(); // Quad Stopped + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QSSR_SCOM2, l_data64)); + +fapi_try_exit: + FAPI_INF("< p9_sbe_select_ex"); + + return fapi2::current_err; +} // END p9_sbe_select_ex + +///----------------------------------------------------------------------------- +/// @brief Remve core chiplet from Dynamic cores multicast group +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// that is a core +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode select_ex_remove_core_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + FAPI_INF("> remove_from_core_mc_group..."); + + fapi2::buffer<uint64_t> l_data64 = 0; + + // Entering group + l_data64.insertFromRight<0, 3>(0x7); + l_data64.insertFromRight<3, 3>(BROADCAST_GROUP); + // Removed group + l_data64.insertFromRight<19, 3>(CORE_STOP_MC_GROUP); + +#ifndef __PPE__ + uint8_t l_attr_chip_unit_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + i_target_cplt, + l_attr_chip_unit_pos)); + + FAPI_DBG("Removing Core %d from MC group %d", + l_attr_chip_unit_pos - PERV_CORE_START, + CORE_STOP_MC_GROUP ); +#endif + + FAPI_TRY(fapi2::putScom(i_target_cplt, + CORE_MC_REG, + l_data64), + "Error: Core MC group register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + +fapi_try_exit: + FAPI_INF("< remove_from_core_mc_group..."); + return fapi2::current_err; + +} + +///----------------------------------------------------------------------------- +/// @brief Remove EX from multicast group +/// +/// @param[in] i_ex_num EX number that needs to be removed from an MC group +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode select_ex_remove_ex_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint32_t i_ex_num) +{ + FAPI_INF("> select_ex_remove_ex_from_mc_group..."); + + // If the Core is in a even EX, then put the EQ chiplet in the EQ MC group + // and the EX Even MC group. + + // If the Core is in a odd EX, then put the EQ chiplet in the EQ MC group + // and the EX Odd MC group. + + fapi2::buffer<uint64_t> l_data64 = 0; + + // Entering group + l_data64.insertFromRight<0, 3>(0x7); + l_data64.insertFromRight<3, 3>(BROADCAST_GROUP); + + if (i_ex_num % 2) // Odd EX + { + FAPI_DBG("Removing EX %d (Odd) from MC group %d", + i_ex_num, + EX_ODD_STOP_MC_GROUP); + + // Removed group + l_data64.insertFromRight<19, 3>(EX_ODD_STOP_MC_GROUP); + + FAPI_TRY(fapi2::putScom(i_target_cplt, + EX_ODD_MC_REG, + l_data64), + "Error: EX Odd MC group register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + + } + else // Even EX + { + FAPI_DBG("Removing EX %d (Even) from MC group %d", + i_ex_num, + EX_EVEN_STOP_MC_GROUP); + + + // Removed group + l_data64.insertFromRight<19, 3>(EX_EVEN_STOP_MC_GROUP); + + FAPI_TRY(fapi2::putScom(i_target_cplt, + EX_EVEN_MC_REG, + l_data64), + "Error: EX Even MC group register, rc 0x%.16X", + (uint32_t)fapi2::current_err); + } + +fapi_try_exit: + FAPI_INF("< select_ex_remove_ex_from_mc_group..."); + return fapi2::current_err; + +} + +///----------------------------------------------------------------------------- +/// @brief Remove EX from multicast group +/// +/// @param[in] i_ex_num EX number for which the EQ needs to be in MC group +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode select_ex_remove_eq_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + FAPI_INF("> select_ex_remove_eq_from_mc_group..."); + + fapi2::buffer<uint64_t> l_data64; + + // Entering group + l_data64.insertFromRight<0, 3>(0x7); + l_data64.insertFromRight<3, 3>(BROADCAST_GROUP); + // Removed group + l_data64.insertFromRight<19, 3>(EQ_STOP_MC_GROUP); + +#ifndef __PPE__ + uint8_t l_attr_chip_unit_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + i_target_cplt, + l_attr_chip_unit_pos)); + + FAPI_DBG("Removing EQ %d from MC group %d", + l_attr_chip_unit_pos - PERV_EQ_START, + EQ_STOP_MC_GROUP ); +#endif + + FAPI_TRY(fapi2::putScom(i_target_cplt, + EQ_MC_REG, + l_data64), + "Error: EQ MC group register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + +fapi_try_exit: + FAPI_INF("< select_ex_remove_eq_from_mc_group..."); + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H new file mode 100644 index 00000000..3c40e9aa --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H @@ -0,0 +1,85 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_select_ex.H +/// @brief Select the Hostboot core from the available cores on the chip +/// +// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: SBE +/// + +#ifndef _P9_SBE_SELECT_EX_H_ +#define _P9_SBE_SELECT_EX_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi2.H> +#include <p9_misc_scom_addresses.H> +#include <p9_quad_scom_addresses.H> +#include <p9_perv_scom_addresses.H> + + +namespace p9selectex +{ +// valid domain options +enum MODE +{ + SINGLE, // Only the first core + ALL // All Core +}; + +} // namespace p9selectex + + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_select_ex_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + p9selectex::MODE); + +extern "C" { + +// ----------------------------------------------------------------------------- +// Function prototype +// ----------------------------------------------------------------------------- + +/// @brief Select the Hostboot core from the available cores on the chip +/// +/// @param [in] i_target Chip target +/// @param [in] i_mode SINGLE core (enable only the first core found); +/// ALL cores (enable all configured cores found) +/// + fapi2::ReturnCode p9_sbe_select_ex( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + p9selectex::MODE i_mode); + +} // extern "C" + +#endif // _P9_SBE_SELECT_EX_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C new file mode 100644 index 00000000..420680f7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C @@ -0,0 +1,151 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_sbe_setup_boot_freq.C +/// @brief Setup Boot Frequency +/// +// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : SBE +// *Level : 2 +/// +/// @verbatim +/// +/// Procedure Summary: +/// - Read frequency ATTR and write to the Quad PPM DPLL Freq Ctrl register +/// +/// @endverbatim + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +#include "p9_sbe_setup_boot_freq.H" +#include "p9_quad_scom_addresses.H" + +enum P9_SBE_SETUP_BOOT_FREQ_CONSTANTS +{ + +// Default configuration settings + +// Default boot_frequency in terms of a multiplier of the refclk frequency/8 +// This is value used if the mailbox value is zero +// +// Value implemented is 3.0GHz, @todo, RTC 140053 - Should it be 2 GHz for P9 ? +// +// 3000MHz / 16.667MHz = ~180 => 0xB4 +// +// Note: the above is aligned, as a value, to 0:10, written as bits 17:27 of PPM DPLL freq ctrl register +// Bits 0:7 are DPLL.MULT_INTG(0:7), and Bits 8:10 are DPLL.MULT_FRAC(0:2) +// + DEFAULT_BOOT_FREQUENCY_MULTIPLIER = 0x00B4, + +}; + +//----------------------------------------------------------------------------- +// Procedure +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +BootFreqInitAttributes(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + uint16_t& i_boot_frequency_multiplier) +{ + + i_boot_frequency_multiplier = DEFAULT_BOOT_FREQUENCY_MULTIPLIER; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target, i_boot_frequency_multiplier)); + + // If attribute values are zero, use the default values (hardcoded) + + // check BOOT FREQ MULT + if (i_boot_frequency_multiplier == 0) + { + // Default voltage if mailbox value is not set + + // @todo, L3 phase Eventually, this should replaced with an error point + // to indicate that the mailbox -> attributes haven't been setup + + i_boot_frequency_multiplier = DEFAULT_BOOT_FREQUENCY_MULTIPLIER; + FAPI_INF("DPLL boot frequency not set in attributes. Setting to default of %d (%x)", + i_boot_frequency_multiplier, i_boot_frequency_multiplier); + } + else + { + FAPI_INF("DPLL boot frequency = %d (%x)", + i_boot_frequency_multiplier, i_boot_frequency_multiplier); + } + +fapi_try_exit: + return fapi2::current_err; +} // BootFreqInitAttributes + + +fapi2::ReturnCode +setDPLLFrequency(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint16_t i_DpllBootFreqMult + ) +{ + fapi2::buffer<uint64_t> l_data; + + + auto l_present_eqs = i_target.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL); + + l_data.insertFromRight<17, 11>(i_DpllBootFreqMult); + + for(auto l_tlst : l_present_eqs) + { + FAPI_TRY(fapi2::putScom(l_tlst, EQ_QPPM_DPLL_FREQ, l_data)); + //@todo,Determine ff_slew rate value RTC 140053 + FAPI_TRY(fapi2::putScom(l_tlst, EQ_QPPM_DPLL_CTRL, 0)); + + } + +fapi_try_exit: + return fapi2::current_err; +} + + +// Hardware procedure +fapi2::ReturnCode +p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + // Boot frequency variable + uint16_t l_boot_frequency_multiplier; + + // Read Boot freq mult attribute + FAPI_TRY(BootFreqInitAttributes(i_target, l_boot_frequency_multiplier)); + + // Set Boot Frequency + + FAPI_TRY(setDPLLFrequency(i_target, + l_boot_frequency_multiplier), + "Setting Boot Frequency"); + +fapi_try_exit: + return fapi2::current_err; + +} // Procedure diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H new file mode 100644 index 00000000..c41909ae --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_sbe_setup_boot_freq.H +/// @brief Setup Boot Frequency +/// +/// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +/// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *Team : PM +/// *Consumed by : SBE +/// *Level : 2 +/// + +#ifndef __P9_SBE_SETUP_BOOT_FREQ_H__ +#define __P9_SBE_SETUP_BOOT_FREQ_H__ + +/// @typedef p9_sbe_setup_boot_freq_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_setup_boot_freq_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +extern "C" +{ + +/// @brief Read an attribute containing the boot frequency and set that +/// into each configured EQ chiplet. +/// @param [in] i_target TARGET_TYPE_PROC_CHIP +/// @attr +/// @attritem ATTR_BOOT_FREQ_MULT - 11 bit frequency multiplier of refclk +/// @return FAPI2_RC_SUCCESS + fapi2::ReturnCode + p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +} // extern C + +#endif // __P9_SBE_SETUP_BOOT_FREQ_H__ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C new file mode 100644 index 00000000..e7797e75 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C @@ -0,0 +1,82 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_setup_evid.C +/// @brief Setup External Voltage IDs and Boot Frequency +/// +// *HW Owner : Greg Still <stillgs@us.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : SBE +// *Level : 1 +/// +/// @verbatim +/// Procedure Summary: +/// - Use Attributes to send VDD, VCS via the AVS bus to VRMs +/// - Use Attributes to adjust the VDN and send via I2C to VRM +/// - Read core frequency ATTR and write to the Quad PPM +/// @endverbatim + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +#include "p9_sbe_setup_evid.H" + +//----------------------------------------------------------------------------- +// Procedure +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + + //fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + + // Substep indicators + + // commented out in Level 1 to not have "unused variable" warnings + // until the SBE substep management "macro" or "call" is defined. + + // const uint32_t STEP_SBE_EVID_START = 0x1; + // const uint32_t STEP_SBE_EVID_CONFIG = 0x2; + // const uint32_t STEP_SBE_EVID_WRITE_VDN = 0x3; + // const uint32_t STEP_SBE_EVID_POLL_VDN_STATUS = 0x4; + // const uint32_t STEP_SBE_EVID_WRITE_VDD = 0x5; + // const uint32_t STEP_SBE_EVID_POLL_VDD_STATUS = 0x6; + // const uint32_t STEP_SBE_EVID_WRITE_VCS = 0x7; + // const uint32_t STEP_SBE_EVID_POLL_VCS_STATUS = 0x8; + // const uint32_t STEP_SBE_EVID_TIMEOUT = 0x9; + // const uint32_t STEP_SBE_EVID_BOOT_FREQ = 0xA; + // const uint32_t STEP_SBE_EVID_COMPLETE = 0xB; + +// The inclusion of the following will cause a "label 'fapi_try_exit' defined but not used" +// compile error in Cronus. This will be uncommented when FAPI_TRY functions are added +// during the real procedure development. However, this is NOT needed for Level 1. +//fapi_try_exit: + return fapi2::current_err; + +} // Procedure + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H new file mode 100644 index 00000000..a1ab2263 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_setup_evid.H +/// @brief Setup External Voltage IDs and Boot Frequency +/// +/// *HW Owner : Greg Still <stillgs@us.ibm.com> +/// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *Team : PM +/// *Consumed by : SBE +/// *Level : 1 +/// + +#ifndef __P9_SBE_SETUP_EVID_H__ +#define __P9_SBE_SETUP_EVID_H__ + +extern "C" +{ + +/// @typedef p9_sbe_setup_evid_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_sbe_setup_evid_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Read attributes containing this part's boot voltages (VDD, VCS and VDN) +/// and set these voltage using the AVSBUS interface (VDD, VCS) an I2C (VDN). +/// Also reads a differnt attribute containing the boot frequency and set that +/// into each configured EQ chiplet. +/// @param [in] i_target TARGET_TYPE_PROC_CHIP +/// @attr +/// @attritem ATTR_BOOT_FREQ uint16_t - 9 bit frequency multiplier of the refclk right justified +/// @attritem ATTR_VCS_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VCS rail +/// @attritem ATTR_VDD_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VDD rail +/// @attritem ATTR_VDN_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VDN rail +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + + +} // extern C + +#endif // __P9_SBE_SETUP_EVID_H__ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C new file mode 100644 index 00000000..f55ae68d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C @@ -0,0 +1,327 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.C +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_startclock_chiplets.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_STARTCLOCK_CHIPLETS_Private_Constants +{ + DONT_STARTMASTER = 0x0, + DONT_STARTSLAVE = 0x0, + CLOCK_CMD = 0x1, + CLOCK_TYPES = 0x7, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE +}; + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint8_t i_attr); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_sync_config( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_xb_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_pg_vector; + fapi2::buffer<uint64_t> l_regions; + fapi2::buffer<uint8_t> l_attr_obus_ratio; + fapi2::buffer<uint32_t> l_attr_pg; + FAPI_INF("p9_sbe_startclock_chiplets: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, + l_attr_obus_ratio)); + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_startclock_chiplets_set_ob_ratio(l_trgt_chplt, + l_attr_obus_ratio)); + } + + for (auto l_target_cplt : + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector)); + FAPI_DBG("partial good targets vector: %#018lX", l_pg_vector); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_startclock_chiplets_get_attr_pg(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Call p9_sbe_common_cplt_ctrl_action_function for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Disable listen to sync for all non-master/slave chiplets"); + FAPI_TRY(p9_sbe_startclock_chiplets_sync_config(l_trgt_chplt)); + + FAPI_DBG("call module align chiplets for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_align_chiplets(l_trgt_chplt)); + + FAPI_DBG("Region setup "); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_regions)); + FAPI_DBG("Regions value: %#018lX", l_regions); + + FAPI_DBG("Call module clock start stop for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, + DONT_STARTSLAVE, DONT_STARTMASTER, l_regions, CLOCK_TYPES)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for Xbus"); + FAPI_TRY(p9_sbe_startclock_chiplets_xb_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop Chiplet fence for Obus"); + FAPI_TRY(p9_sbe_startclock_chiplets_ob_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for PCIe"); + FAPI_TRY(p9_sbe_startclock_chiplets_pci_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("call sbe_common_flushmode for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); + } + + FAPI_INF("p9_sbe_startclock_chiplets: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief get attr_pg for the chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[out] o_attr_pg ATTR_PG for the chiplet +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg) +{ + FAPI_INF("p9_sbe_startclock_chiplets_get_attr_pg: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, o_attr_pg)); + + FAPI_INF("p9_sbe_startclock_chiplets_get_attr_pg: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for OB chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_ob_fence_drop: Entering ..."); + + FAPI_INF("Drop chiplet fence"); + + //Setting NET_CTRL0 register value + if (i_pg_vector.getBit<2>() == 1) + { + l_data64.flush<1>(); + //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<2>() == 1) ? 0 + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_startclock_chiplets_ob_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for pcie chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_pci_fence_drop: Entering ..."); + + FAPI_INF("Drop chiplet fence"); + + //Setting NET_CTRL0 register value + if (i_pg_vector.getBit<3>() == 1) + { + l_data64.flush<1>(); + //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<3>() == 1) ? 0 + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_startclock_chiplets_pci_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief set obus ratio +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr Attribute that holds the OBUS ratio value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint8_t i_attr) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_set_ob_ratio: Entering ..."); + + //Setting CPLT_CONF1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_CPLT_CONF1, l_data64)); + l_data64.insertFromRight<16, 2>(i_attr); //CPLT_CONF1.TC_OB_RATIO_DC = i_attr + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CONF1, l_data64)); + + FAPI_INF("p9_sbe_startclock_chiplets_set_ob_ratio: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Disable listen to sync for all non-master / slave chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_sync_config( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_sync_config: Entering ..."); + + //Setting SYNC_CONFIG register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_SYNC_CONFIG, l_data64)); + l_data64.setBit<4>(); //SYNC_CONFIG.LISTEN_TO_SYNC_PULSE_DIS = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SYNC_CONFIG, l_data64)); + + FAPI_INF("p9_sbe_startclock_chiplets_sync_config: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for XB chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_xb_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_xb_fence_drop: Entering ..."); + + FAPI_INF("Drop chiplet fence"); + + //Setting NET_CTRL0 register value + if (i_pg_vector.getBit<1>() == 1) + { + l_data64.flush<1>(); + //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<1>() == 1) ? 0 + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_startclock_chiplets_xb_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H new file mode 100644 index 00000000..a9e777f6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.H +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_STARTCLOCK_CHIPLETS_H_ +#define _P9_SBE_STARTCLOCK_CHIPLETS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_startclock_chiplets_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Start Xbus, Obus, PCIe clocks +/// Start clocks on configured chiplets for all chips (master and slaves) +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplets); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C new file mode 100644 index 00000000..151aa89d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C @@ -0,0 +1,159 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_arrayinit.C +/// +/// @brief SBE PRV Array Init Procedure +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_arrayinit.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +enum P9_SBE_TP_ARRAYINIT_Private_Constants +{ + REGIONS_EXCEPT_PIB_NET_PLL = 0x4FE, + SCAN_TYPES = 0xDCF, + LOOP_COUNTER = 0x0000000000042FFF, + START_ABIST_MATCH_VALUE = 0x0000000F00000000, + SELECT_SRAM = 0x1, + SELECT_EDRAM = 0x0, + PIBMEM_EXCLUDE_ABIST = 0xC000000000000000, + PIBMEM_INCLUDE_ABIST = 0x8000000000000000 +}; + +static fapi2::ReturnCode p9_sbe_tp_arrayinit_sdisn_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set); + +fapi2::ReturnCode p9_sbe_tp_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint8_t> l_attr_read; + + FAPI_INF("p9_sbe_tp_arrayinit: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read)); + + FAPI_DBG("Exclude PIBMEM from TP array init"); + //Setting PIBMEM_REPAIR_REGISTER_0 register value + //PIB.PIBMEM_REPAIR_REGISTER_0 = 0xC000000000000000 + FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0, PIBMEM_EXCLUDE_ABIST )); + + FAPI_DBG("set sdis_n"); + FAPI_TRY(p9_sbe_tp_arrayinit_sdisn_setup( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_attr_read, true)); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_PIB_NET_PLL, l_regions)); + FAPI_DBG("l_regions value: %#018lX", l_regions); + + FAPI_DBG("Call ARRAY INIT Module for Pervasive Chiplet"); + FAPI_TRY(p9_perv_sbe_cmn_array_init_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, LOOP_COUNTER, SELECT_SRAM, + SELECT_EDRAM, START_ABIST_MATCH_VALUE)); + + FAPI_DBG("Call SCAN0 Module for Pervasive Chiplet"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES)); + + FAPI_DBG("clear sdis_n"); + FAPI_TRY(p9_sbe_tp_arrayinit_sdisn_setup( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_attr_read, false)); + + FAPI_DBG("Add PIBMEM back to TP array init"); + //Setting PIBMEM_REPAIR_REGISTER_0 register value + //PIB.PIBMEM_REPAIR_REGISTER_0 = 0x8000000000000000 + FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0, PIBMEM_INCLUDE_ABIST)); + + FAPI_INF("p9_sbe_tp_arrayinit: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Sdis_n set or clear +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr Attribute to decide to sdis_n setup +/// @param[in] i_set set or clear the LCBES condition +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_tp_arrayinit_sdisn_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_arrayinit_sdisn_setup: Entering ..."); + + if ( i_attr ) + { + if ( i_set ) + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 1 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_OR, l_data64)); + } + else + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 0 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_CLEAR, l_data64)); + } + } + + FAPI_INF("p9_sbe_tp_arrayinit_sdisn_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H new file mode 100644 index 00000000..9ab5e359 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_arrayinit.H +/// +/// @brief SBE PRV Array Init Procedure +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_ARRAYINIT_H_ +#define _P9_SBE_TP_ARRAYINIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_arrayinit_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Array Init for PRV Cplt +/// -- Scan0 of PRV Chiplet (except PIB/PCB) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C new file mode 100644 index 00000000..c953c3cf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C @@ -0,0 +1,134 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init1.C +/// +/// @brief Initial steps of PIB AND PCB +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init1.H" +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +enum P9_SBE_TP_CHIPLET_INIT1_Private_Constants +{ + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE, + REGIONS_EXCEPT_VITAL_PIB_NET = 0x4FF, // Regions excluding VITAL, PIB and NET + SCAN_TYPES_TIME_GPTR_REPR = 0x230 +}; + +fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint64_t> l_data64; + fapi2::buffer<uint8_t> l_read_attr; + FAPI_INF("p9_sbe_tp_chiplet_init1: Entering ..."); + + FAPI_DBG("Disable local clock gating VITAL"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING, + i_target_chip, l_read_attr)); + FAPI_DBG("l_read_attr is %d", l_read_attr); + + if (l_read_attr) + { + //Getting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64)) + //PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC = 1 + l_data64.setBit<PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64)); + } + + FAPI_DBG("Release PCB Reset"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + //PIB.ROOT_CTRL0.PCB_RESET_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Set Chiplet Enable"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1 + l_data64.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Drop TP Chiplet Fence Enable"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0 + l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Drop Global Endpoint reset"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL0_SET_GLOBAL_EP_RESET_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + FAPI_DBG("Switching PIB trace bus to SBE tracing"); + + FAPI_DBG("Drop OOB Mux"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>(); //PIB.ROOT_CTRL0.OOB_MUX = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Region setup call"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET, l_regions)); + FAPI_DBG("l_regions value : %#018lX", l_regions); + + FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES_TIME_GPTR_REPR)); + + FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types except GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + + FAPI_INF("p9_sbe_tp_chiplet_init1: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H new file mode 100644 index 00000000..39383792 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init1.H +/// +/// @brief Initial steps of PIB AND PCB +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT1_H_ +#define _P9_SBE_TP_CHIPLET_INIT1_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Releases the Pervasive Control Bus (PCB) reset +/// Sets TP chiplet enable +/// Drops pervasive chiplet fences +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C new file mode 100644 index 00000000..69c6f6c3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init2.C +/// +/// @brief Run scan 0 module for pervasive +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init2.H" + + +fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + + FAPI_INF("p9_sbe_tp_chiplet_init2: Entering ..."); + + + FAPI_INF("p9_sbe_tp_chiplet_init2: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H new file mode 100644 index 00000000..34d94425 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init2.H +/// +/// @brief Run scan 0 module for pervasive +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT2_H_ +#define _P9_SBE_TP_CHIPLET_INIT2_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init2_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Initialize TP Hangcounter 6 +/// -- Scan Repair, Time and GPTR for PRV Chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C new file mode 100644 index 00000000..c7af39d3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C @@ -0,0 +1,371 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init3.C +/// +/// @brief TP Chiplet Start Clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init3.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_TP_CHIPLET_INIT3_Private_Constants +{ + START_CMD = 0x1, + REGIONS_ALL_EXCEPT_PIB_NET = 0x4FF, + CLOCK_TYPES = 0x7, + HW_NS_DELAY = 100000, // unit is nano seconds + SIM_CYCLE_DELAY = 1000, // unit is sim cycles + POLL_COUNT = 300, // Observed Number of times CBS read for CBS_INTERNAL_STATE_VECTOR + OSC_ERROR_MASK = 0xF700000000000000, // Mask OSC errors + LFIR_ACTION0_VALUE = 0x0000000000000000, + LFIR_ACTION1_VALUE = 0xFFFFBC2BFC7FFFFF, + FIR_MASK_VALUE = 0x0000000000000000 +}; + +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + bool l_read_reg = 0; + fapi2::buffer<uint32_t> l_pfet_value; + fapi2::buffer<uint32_t> l_attr_pfet; + fapi2::buffer<uint64_t> l_regions; + fapi2::buffer<uint64_t> l_kvref_reg; + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_tpchiplet = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0]; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_sbe_tp_chiplet_init3: Entering ..."); + + FAPI_DBG("Reading ATTR_PFET_OFF_CONTROLS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PFET_OFF_CONTROLS, i_target_chip, + l_pfet_value)); + + FAPI_DBG("Switch pervasive chiplet OOB mux"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>(); //PIB.ROOT_CTRL0.OOB_MUX = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Reset PCB Master Interrupt Register"); + //Setting INTERRUPT_TYPE_REG register value + //PIB.INTERRUPT_TYPE_REG = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, 0)); + + FAPI_DBG("Clear pervasive chiplet region fence"); + FAPI_TRY(p9_sbe_tp_chiplet_init3_region_fence_setup(l_tpchiplet)); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_tpchiplet, + REGIONS_ALL_EXCEPT_PIB_NET, l_regions)); + FAPI_DBG("l_regions value: %#018lX", l_regions); + + FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_regions, + CLOCK_TYPES)); + + FAPI_DBG("Calling clock_test2"); + FAPI_TRY(p9_sbe_tp_chiplet_init3_clock_test2(i_target_chip)); + + FAPI_DBG("Drop FSI fence 5"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + //PIB.ROOT_CTRL0.FENCE5_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL0_SET_FENCE5_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + l_pfet_value.extractToRight<0, 30>(l_attr_pfet); + + FAPI_DBG("Set pfet off controls"); + //Setting DISABLE_FORCE_PFET_OFF register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_DISABLE_FORCE_PFET_OFF, l_data64)); + //PIB.DISABLE_FORCE_PFET_OFF.DISABLE_FORCE_PFET_OFF_REG = l_attr_pfet + l_data64.insertFromRight<0, 30>(l_attr_pfet); + FAPI_TRY(fapi2::putScom(i_target_chip, PU_DISABLE_FORCE_PFET_OFF, l_data64)); + + FAPI_DBG("Drop EDRAM control gate and pfet_force_off"); + //Setting ROOT_CTRL2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_data64)); + l_data64.clearBit<16>(); //PIB.ROOT_CTRL2.ROOT_CTRL2_16_FREE_USAGE = 0 + //PIB.ROOT_CTRL2.TPFSI_TP_PFET_FORCE_OFF_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_FORCE_OFF_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_data64)); + + //TOD error reg; + //config TOD error mask reg; + //clear TOD error reg; + + FAPI_DBG("Clear pervasive LFIR"); + //Setting LOCAL_FIR register value + //PERV.LOCAL_FIR = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_AND, 0)); + + FAPI_DBG("Configure pervasive LFIR" ); + //Setting LOCAL_FIR_ACTION0 register value + //PERV.LOCAL_FIR_ACTION0 = LFIR_ACTION0_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_ACTION0, + LFIR_ACTION0_VALUE)); + //Setting LOCAL_FIR_ACTION1 register value + //PERV.LOCAL_FIR_ACTION1 = LFIR_ACTION1_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_ACTION1, + LFIR_ACTION1_VALUE)); + //Setting LOCAL_FIR_MASK register value + //PERV.LOCAL_FIR_MASK = FIR_MASK_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_MASK, FIR_MASK_VALUE)); + + // Enables any checkstop if set, to propogate to FSP and get notified + // + FAPI_DBG("p9_sbe_tp_chiplet_init3: Unmask CFIR Mask"); + //Setting FIR_MASK register value + //PERV.FIR_MASK = FIR_MASK_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_FIR_MASK, FIR_MASK_VALUE)); + + FAPI_DBG("Setup Pervasive Hangcounter 0:Thermal, 1:OCC/SBE, 2:PBA hang, 3:Nest freq for TOD hang, 5:malefunction alert"); + //Setting HANG_PULSE_0_REG register value (Setting all fields) + //PERV.HANG_PULSE_0_REG.HANG_PULSE_REG_0 = 0b010000 + l_data64.insertFromRight<0, 6>(0b010000); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_0_REG.SUPPRESS_HANG_0 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_0_REG, l_data64)); + //Setting HANG_PULSE_1_REG register value (Setting all fields) + //PERV.HANG_PULSE_1_REG.HANG_PULSE_REG_1 = 0b000100 + l_data64.insertFromRight<0, 6>(0b000100); + l_data64.setBit<6>(); //PERV.HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_1_REG, l_data64)); + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //PERV.HANG_PULSE_2_REG.HANG_PULSE_REG_2 = 0b010010 + l_data64.insertFromRight<0, 6>(0b010010); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_2_REG, l_data64)); + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //PERV.HANG_PULSE_3_REG.HANG_PULSE_REG_3 = 0b000001 + l_data64.insertFromRight<0, 6>(0b000001); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_3_REG, l_data64)); + //Setting HANG_PULSE_5_REG register value (Setting all fields) + //PERV.HANG_PULSE_5_REG.HANG_PULSE_REG_5 = 0b000110 + l_data64.insertFromRight<0, 6>(0b000110); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_5_REG.SUPPRESS_HANG_5 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_5_REG, l_data64)); + + FAPI_DBG("CHECK FOR XSTOP"); + //Getting INTERRUPT_TYPE_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, l_data64)); + //l_read_reg = PIB.INTERRUPT_TYPE_REG.CHECKSTOP + l_read_reg = l_data64.getBit<PERV_INTERRUPT_TYPE_REG_CHECKSTOP>(); + + FAPI_ASSERT(l_read_reg == 0, + fapi2::XSTOP_ERR() + .set_READ_XSTOP(l_read_reg), + "XSTOP BIT GET SET"); + + FAPI_DBG("Start calibration"); + //Setting KVREF_AND_VMEAS_MODE_STATUS_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64)); + l_data64.setBit<0>(); //KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_START_CAL = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64)); + + FAPI_DBG("Check for calibration done"); + l_timeout = POLL_COUNT; + + //UNTIL KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_CAL_DONE == 1 + while (l_timeout != 0) + { + //Getting KVREF_AND_VMEAS_MODE_STATUS_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64)); + //bool l_poll_data = KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_CAL_DONE + bool l_poll_data = l_data64.getBit<16>(); + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(HW_NS_DELAY, SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::CALIBRATION_NOT_DONE(), + "Calibration not done, bit16 not set"); + + FAPI_INF("p9_sbe_tp_chiplet_init3: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock test +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read ; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_chiplet_init3_clock_test2: Entering ..."); + + FAPI_DBG("unfence 281D"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<0>(); //PIB.ROOT_CTRL0.TPFSI_SBE_FENCE_VTLIO_DC_UNUSED = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + //Getting ROOT_CTRL3 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, + l_read)); //l_read = PIB.ROOT_CTRL3 + + l_read.setBit<27>(); + + FAPI_DBG("Set osc_ok latch active"); + //Setting ROOT_CTRL3 register value + //PIB.ROOT_CTRL3 = l_read + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read)); + + FAPI_DBG("Turn on oscilate pgood"); + //Setting ROOT_CTRL6 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL6_SCOM, l_data64)); + //PIB.ROOT_CTRL6.TPFSI_OSCSW1_PGOOD = 1 + l_data64.setBit<PERV_ROOT_CTRL6_SET_TPFSI_OSCSW1_PGOOD>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL6_SCOM, l_data64)); + + //Getting ROOT_CTRL3 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, + l_read)); //l_read = PIB.ROOT_CTRL3 + + l_read.clearBit<17>(); + + FAPI_DBG("turn off use_osc_1_0"); + //Setting ROOT_CTRL3 register value + //PIB.ROOT_CTRL3 = l_read + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read)); + + FAPI_DBG("Mask OSC err"); + //Setting OSCERR_MASK register value + //PIB.OSCERR_MASK = OSC_ERROR_MASK + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_OSCERR_MASK, OSC_ERROR_MASK)); + + FAPI_DBG("reset osc-error_reg"); + //Setting OSCERR_HOLD register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_OSCERR_HOLD, l_data64)); + l_data64.clearBit<4, 4>(); //PERV.OSCERR_HOLD.OSCERR_MEM = 0000 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_OSCERR_HOLD, l_data64)); + + FAPI_DBG("Resets FIR"); + //Setting LOCAL_FIR register value + l_data64.flush<1>(); + l_data64.clearBit<36>(); + l_data64.clearBit<37>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_AND, l_data64)); + +#ifndef SIM_ONLY_OSC_SWC_CHK + + FAPI_DBG("check for OSC ok"); + //Getting SNS1LTH register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SNS1LTH_SCOM, + l_read)); //l_read = PIB.SNS1LTH + + FAPI_ASSERT(l_read.getBit<21>() == 0 && l_read.getBit<28>() == 1, + fapi2::MF_OSC_NOT_TOGGLE() + .set_READ_SNS1LTH(l_read), + "MF oscillator not toggling"); + + FAPI_DBG("Osc error active"); + //Getting OSCERR_HOLD register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_OSCERR_HOLD, + l_read)); //l_read = PERV.OSCERR_HOLD + + FAPI_ASSERT(l_read.getBit<4>() == 0, + fapi2::MF_OSC_ERR() + .set_READ_OSCERR_HOLD(l_read), + "MF oscillator error active"); + +#endif + + FAPI_INF("p9_sbe_tp_chiplet_init3_clock_test2: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief region fence setup +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + // Local variable and constant definition + fapi2::buffer <uint32_t> l_attr_pg; + fapi2::buffer <uint16_t> l_attr_pg_data; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_chiplet_init3_region_fence_setup: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); + + l_attr_pg.invert(); + l_attr_pg.extractToRight<20, 11>(l_attr_pg_data); + + FAPI_DBG("Drop partial good fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + l_data64.writeBit<PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE> + (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_attr_pg_data + l_data64.insertFromRight<4, 11>(l_attr_pg_data); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_tp_chiplet_init3_region_fence_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H new file mode 100644 index 00000000..c5367d97 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H @@ -0,0 +1,66 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init3.H +/// +/// @brief TP Chiplet Start Clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT3_H_ +#define _P9_SBE_TP_CHIPLET_INIT3_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init3_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Switches PRV Chiplet OOB mux +/// -- Reset PCB Master Interrupt Register +/// -- Drop Pervasive and OCC2PIB Fence in GP0 (bits 19 & 63) +/// --"Clock Start" command (all other clk domains) +/// -- Clear force_align in chiplet GP0 +/// -- Clear flushmode_inhibit in chiplet GP0 +/// -- Drop FSI fence 5 (checkstop, interrupt conditions) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C new file mode 100644 index 00000000..f7960207 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_reset.C +/// +/// @brief setup hangcounter 6 for TP chiplet +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_reset.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_chiplet_reset: Entering ..."); + + FAPI_DBG("Initializing Hangcounter 6 for PRV Cplt"); + //Setting HANG_PULSE_6_REG register value + //PERV.HANG_PULSE_6_REG = HANG_PULSE_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_6_REG, + HANG_PULSE_VALUE)); + + FAPI_DBG("p9_sbe_tp_chiplet_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H new file mode 100644 index 00000000..441a7a6e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_reset.H +/// +/// @brief setup hangcounter 6 for TP chiplet +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_RESET_H_ +#define _P9_SBE_TP_CHIPLET_RESET_H_ + + +#include <fapi2.H> + + +enum P9_SBE_TP_CHIPLET_RESET_Constants +{ + HANG_PULSE_VALUE = 0x1400000000000000 +}; + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_reset_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Setup hang counter for PCB slaves/master +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C new file mode 100644 index 00000000..b8c22322 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_enable_ridi.C +/// +/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_enable_ridi.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_tp_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("p9_sbe_tp_enable_ridi: Entering ..."); + + FAPI_INF("Enable Recievers, Drivers DI1 & DI2"); + //Setting ROOT_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + l_data64.setBit<19>(); //PIB.ROOT_CTRL1.TP_RI_DC_B = 1 + l_data64.setBit<20>(); //PIB.ROOT_CTRL1.TP_DI1_DC_B = 1 + l_data64.setBit<21>(); //PIB.ROOT_CTRL1.TP_DI2_DC_B = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + + FAPI_DBG("p9_sbe_tp_enable_ridi: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H new file mode 100644 index 00000000..c18e9a7f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_enable_ridi.H +/// +/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_ENABLE_RIDI_H_ +#define _P9_SBE_TP_ENABLE_RIDI_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_enable_ridi_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Enable drivers/receivers for PRV chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C new file mode 100644 index 00000000..42957145 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_initf.C +/// +/// @brief Scan initialize GPTR, TIME for PERV chiplet +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ + +#include "p9_sbe_tp_gptr_time_initf.H" + +fapi2::ReturnCode p9_sbe_tp_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_tp_gptr_time_initf: Entering ..."); + + FAPI_DBG("Scan perv_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_gptr), + "Error from putRing (perv_gptr)"); + FAPI_DBG("Scan perv_ana_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_ana_gptr), + "Error from putRing (perv_ana_gptr)"); + FAPI_DBG("Scan perv_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_pll_gptr), + "Error from putRing (perv_pll_gptr)"); + FAPI_DBG("Scan occ_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_gptr), + "Error from putRing (occ_gptr)"); + FAPI_DBG("Scan occ_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_time), + "Error from putRing (occ_time)"); + FAPI_DBG("Scan perv_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_time), + "Error from putRing (perv_time)"); + +fapi_try_exit: + FAPI_INF("p9_sbe_tp_gptr_time_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H new file mode 100644 index 00000000..2b99ade3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_initf.C +/// +/// @brief Scan initialize GPTR, TIME for PERV chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_TP_GPTR_TIME_INITF_H_ +#define _P9_SBE_TP_GPTR_TIME_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_gptr_time_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Load Scan Repair, Time and GPTR for TP Chiplet +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C new file mode 100644 index 00000000..2c351d74 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_repr_initf.C +/// +/// @brief proc sbe tp gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_gptr_time_repr_initf.H" +fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Entering ..."); + + FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H new file mode 100644 index 00000000..27ba211c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_repr_initf.H +/// +/// @brief proc sbe tp gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_ +#define _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_gptr_time_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Load Scan Repair, Time and GPTR for TP Chiplet +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C new file mode 100644 index 00000000..f1150966 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_initf.C +/// +/// @brief TP chiplet scaninits for the TP rings +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_initf.H" +#include "p9_ring_id.h" + +fapi2::ReturnCode p9_sbe_tp_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_tp_initf: Entering ..."); + + FAPI_DBG("Scan perv_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_fure), + "Error from putRing (perv_fure)"); + + FAPI_DBG("Scan occ_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_fure), + "Error from putRing (occ_fure)"); + + FAPI_DBG("Scan perv_ana_func ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_ana_func), + "Error from putRing (perv_ana_func)"); + +fapi_try_exit: + FAPI_INF("p9_sbe_tp_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H new file mode 100644 index 00000000..abf1f54c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_initf.H +/// +/// @brief TP chiplet scaninits for the TP rings +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_INITF_H_ +#define _P9_SBE_TP_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_initf_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- This doesn't include the gptr/time/repair rings, +/// -- since they are scanned in tp_chiplet_init2. +/// -- This doesn't include the net/pib/fuse rings, +/// -- since they are used by the SBE hardware itself. +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C new file mode 100644 index 00000000..7c933122 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_ld_image.C +/// +/// @brief Proc SBE load Image +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_ld_image.H" +fapi2::ReturnCode p9_sbe_tp_ld_image(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_ld_image: Entering ..."); + + FAPI_DBG("p9_sbe_tp_ld_image: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H new file mode 100644 index 00000000..e458d2be --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_ld_image.H +/// +/// @brief Proc SBE load Image +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_LD_IMAGE_H_ +#define _P9_SBE_TP_LD_IMAGE_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_ld_image_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief This procedure copies the .pibmem0 section of image from SEEPROM to the PIBMEM. +/// The pibmem0 section contains the PORE branch table (error handlers) used for the majority of the SEEPROM IPL as well as +/// performance sensitive routines such as the decompression-scan routine and the LCO loader. +/// Once the image is loaded then the error handlers are switched to +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_ld_image(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C new file mode 100644 index 00000000..53aed3bb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_repr_initf.C +/// +/// @brief Scan initialize REPR for PERV chiplet +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ + +#include "p9_sbe_tp_repr_initf.H" + +fapi2::ReturnCode p9_sbe_tp_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_tp_repr_initf: Entering ..."); + + FAPI_DBG("Scan perv_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_repr), + "Error from putRing (perv_repr)"); + + FAPI_DBG("Scan occ_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_repr), + "Error from putRing (occ_repr)"); + +fapi_try_exit: + FAPI_INF("p9_sbe_tp_repr_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H new file mode 100644 index 00000000..134fc853 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_repr_initf.C +/// +/// @brief Scan initialize REPR for PERV chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_TP_REPR_INITF_H_ +#define _P9_SBE_TP_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Scan Repair for TP Chiplet +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C new file mode 100644 index 00000000..828c855c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C @@ -0,0 +1,161 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_switch_gears.C +/// +/// @brief Switch from refclock to PLL AND adjust I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_switch_gears.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_sbe_gear_switcher.H> + + +enum P9_SBE_TP_SWITCH_GEARS_Private_Constants +{ + BACKUP_SEEPROM_MAGIC_NUM_ADDRESS = 0xD8A9029000000000, // Magic number value from Backup SEEPROM + BUS_STATUS_BUSY_POLL_COUNT = 256, + MAGIC_NUMBER = 0x584950205345504D, + NORMAL_SEEPROM_MAGIC_NUM_ADDRESS = 0xD8A9009000000000 // Magic number value from SEEPROM +}; + +fapi2::ReturnCode p9_sbe_tp_switch_gears(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_switch_gears: Entering ..."); + +#ifdef __PPE__ + + FAPI_DBG("switch from refclock to PLL speed"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0 + l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_TRY(p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting( + i_target_chip)); + + FAPI_TRY(p9_sbe_gear_switcher_i2c_stop_sequence(i_target_chip)); + + FAPI_DBG("Checking Magic number"); + FAPI_TRY(p9_sbe_tp_switch_gears_check_magicnumber(i_target_chip)); +fapi_try_exit: +#endif + + FAPI_INF("p9_sbe_tp_switch_gears: Exiting ..."); + + return fapi2::current_err; + +} + +/// @brief check for magic number +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + fapi2::buffer<uint8_t> l_read_attr = 0; + int l_timeout = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_switch_gears_check_magicnumber: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BACKUP_SEEPROM_SELECT, i_target_chip, + l_read_attr)); + + if ( l_read_attr.getBit<7>() == 1 ) + { + FAPI_DBG("Read magic number from Backup SEEPROM"); + //Setting CONTROL_REGISTER_B register value + //PIB.CONTROL_REGISTER_B = BACKUP_SEEPROM_MAGIC_NUM_ADDRESS + FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, + BACKUP_SEEPROM_MAGIC_NUM_ADDRESS)); + } + else + { + FAPI_DBG("Read magic number from SEEPROM"); + //Setting CONTROL_REGISTER_B register value + //PIB.CONTROL_REGISTER_B = NORMAL_SEEPROM_MAGIC_NUM_ADDRESS + FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, + NORMAL_SEEPROM_MAGIC_NUM_ADDRESS)); + } + + FAPI_DBG("Poll for stop command completion"); + l_timeout = BUS_STATUS_BUSY_POLL_COUNT; + + //UNTIL STATUS_REGISTER_B.BUS_STATUS_BUSY_0 == 0 + while (l_timeout != 0) + { + //Getting STATUS_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64)); + //bool l_poll_data = PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0 + bool l_poll_data = l_data64.getBit<44>(); + + if (l_poll_data == 0) + { + break; + } + + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::BUS_STATUS_BUSY0(), + "ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0"); + + FAPI_DBG("Reading the value of DATA0TO7_REGISTER_B"); + //Getting DATA0TO7_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_DATA0TO7_REGISTER_B, + l_read_reg)); //l_read_reg = PIB.DATA0TO7_REGISTER_B + + FAPI_ASSERT(l_read_reg == MAGIC_NUMBER, + fapi2::MAGIC_NUMBER_NOT_VALID(), + "ERROR: Magic number not matching"); + + FAPI_INF("p9_sbe_tp_switch_gears_check_magicnumber: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H new file mode 100644 index 00000000..a53d025f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_switch_gears.H +/// +/// @brief Switch from refclock to PLL AND adjust I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_SWITCH_GEARS_H_ +#define _P9_SBE_TP_SWITCH_GEARS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_switch_gears_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Switch from refclcok to PLL speed (leave bypass) +/// Read new I2C Bit Rate Divisor setting from mailbox +/// Adjust I2C bit rate divisor setting in I2CM B mode reg +/// Send a stop sequence on I2C +/// Poll for stop command completion +/// Check for magic number +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_switch_gears(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk b/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk new file mode 100644 index 00000000..d4b77bb7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk @@ -0,0 +1,76 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/perv/pervfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file pervfiles.mk +# +# @brief mk for including perv object files +# +########################################################################## +# Object Files +########################################################################## + +PERV-CPP-SOURCES =p9_sbe_arrayinit.C +PERV-CPP-SOURCES +=p9_sbe_attr_setup.C +PERV-CPP-SOURCES +=p9_sbe_check_master.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_init.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_initf.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_setup.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_reset.C +PERV-CPP-SOURCES +=p9_sbe_enable_seeprom.C +PERV-CPP-SOURCES +=p9_sbe_gptr_time_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_lpc_init.C +PERV-CPP-SOURCES +=p9_sbe_nest_enable_ridi.C +PERV-CPP-SOURCES +=p9_sbe_nest_initf.C +PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C +PERV-CPP-SOURCES +=p9_sbe_npll_initf.C +PERV-CPP-SOURCES +=p9_sbe_npll_setup.C +PERV-CPP-SOURCES +=p9_sbe_select_ex.C +PERV-CPP-SOURCES +=p9_sbe_startclock_chiplets.C +PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_reset.C +PERV-CPP-SOURCES +=p9_sbe_tp_enable_ridi.C +PERV-CPP-SOURCES +=p9_sbe_tp_initf.C +PERV-CPP-SOURCES +=p9_sbe_tp_ld_image.C +PERV-CPP-SOURCES +=p9_sbe_setup_evid.C +PERV-CPP-SOURCES +=p9_perv_sbe_cmn.C +PERV-CPP-SOURCES +=p9_sbe_common.C +PERV-CPP-SOURCES +=p9_sbe_check_master_stop15.C +PERV-CPP-SOURCES +=p9_hcd_cache_dcc_skewadjust_setup.C +PERV-CPP-SOURCES +=p9_sbe_setup_boot_freq.C +PERV-CPP-SOURCES +=p9_sbe_io_initf.C +PERV-CPP-SOURCES +=p9_sbe_gptr_time_initf.C +PERV-CPP-SOURCES +=p9_sbe_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_tp_gptr_time_initf.C +PERV-CPP-SOURCES +=p9_sbe_tp_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_clock_test2.C + +PERV-C-SOURCES = +PERV-S-SOURCES = + +PERV_OBJECTS += $(PERV-CPP-SOURCES:.C=.o) +PERV_OBJECTS += $(PERV-C-SOURCES:.c=.o) +PERV_OBJECTS += $(PERV-S-SOURCES:.S=.o) |
