diff options
Diffstat (limited to 'sbe/test')
67 files changed, 0 insertions, 5950 deletions
diff --git a/sbe/test/citest/autocitest b/sbe/test/citest/autocitest deleted file mode 100755 index 70c9ba51..00000000 --- a/sbe/test/citest/autocitest +++ /dev/null @@ -1,96 +0,0 @@ -#!/bin/bash -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/autocitest $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -################################################################################ -## Simics automation using run-fsp-it -################################################################################ - -## verbose is the default. -VERBOSE=" --verbose" -if [ "$1" = "--quiet" ] ; then - VERBOSE="" - shift -fi - -## -## set up -## -DRIVER="$1" ## backing tree -export bb=$DRIVER ## simulate a workon - -export SHELL="/bin/bash" ## Needed to fool workon to launch a bash - ## shell, which autosim expects. -NOWIN="--nowin" ## remote execution does not have a display - -## jenkins creates a new workspace for every compile. -## sbetest-start.sh will verify this and then export WORKSPACE_DIR for us. -SBXHOME=$SBEROOT - -if [ "$DRIVER" = "" ] ; then - echo "ERROR: you must specify a driver (backing tree) to run the tests with" - usage - exit 1 -fi - -## let's get set up -cd $SANDBOXROOT - -echo "$0" -echo "VERBOSE = $VERBOSE" -echo "NOWIN = $NOWIN" -echo "BACKING_TREE = $DRIVER" -echo "SANDBOXRC = $SANDBOXRC" -echo "SBXHOME = $SBXHOME" -echo "AUTOSIM_FFDC_XML = $AUTOSIM_FFDC_XML" -echo "current directory is " `pwd` - - -timestamp=`date +'%H:%M:%S'` -echo "$timestamp Starting SBE test..." - -# Check preconditions for run-fsp-it -# This is just workaround. It is expected -# that user already either have this file -# or tokens have been taken by klog command. -# This is just to make run-fsp-it work in user -# sandbox -if [ -z $RUNNING_UNDER_JENKINS ] -then - mkdir -p ~/private - if [ ! -f ~/private/.p ]; then - echo "Creating p file" - touch ~/private/.p - fi - - if [ ! -f ~/private/password ]; then - echo "Creating passwd file" - touch ~/private/password - echo "dummy" > ~/private/password - fi -fi - -execute_in_sandbox "run-fsp-it $NOWIN --machine $MACHINE $SBE_TEST_XML" "ppc" || exit -1 - -exit 0 - diff --git a/sbe/test/citest/build-script b/sbe/test/citest/build-script deleted file mode 100755 index 8250ad08..00000000 --- a/sbe/test/citest/build-script +++ /dev/null @@ -1,73 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/build-script $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -if [ -z $WORKSPACE ]; then - export WORKSPACE=`pwd` -fi - -if [ -z $SBEROOT ]; then - source "$WORKSPACE/env.bash" -fi - -source "$SBEROOT/sbe/test/citest/setup-env" - -# Check copyright. -#check-copyright > copyright.log 2>&1 & -#COPYRIGHT_PID=$! - - -# Build . -scl enable devtoolset-2 " bash -c \"make install\"" || exit -1 - -# Create simics sandbox. -create-sandbox > create-sandbox.log 2>&1 & -CREATESANDBOX_PID=$! - -# Check sandbox create completion. -wait $CREATESANDBOX_PID -if [ $? -eq 0 ]; then - cat create-sandbox.log -else - echo "----Sandbox creation failed." - cat create-sandbox.log - exit -1 -fi - -# Add SBE files to simics sandbox. -populate-sandbox || exit -1 - -sbetest-start.sh || exit -1 - -# Check copyright completion. -#wait $COPYRIGHT_PID -#if [ $? -eq 0 ]; then -# cat copyright.log -#else -# echo "----Copyright check failed." -# cat copyright.log -# exit -1 -#fi - diff --git a/sbe/test/citest/check-copyright b/sbe/test/citest/check-copyright deleted file mode 100755 index 68e536d4..00000000 --- a/sbe/test/citest/check-copyright +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/check-copyright $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -COPYRIGHT_CHECK=${SBEROOT}/sbe/test/citest/copyright-check.sh -COMMIT_CHECK=${SBEROOT}/sbe/tools/hooks/verify-commit - -$COPYRIGHT_CHECK || exit -1 -$COMMIT_CHECK || exit -1 diff --git a/sbe/test/citest/copyright-check.sh b/sbe/test/citest/copyright-check.sh deleted file mode 100755 index c5c9534d..00000000 --- a/sbe/test/citest/copyright-check.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/copyright-check.sh $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -# -# Front end to addCopyright - script to check for copyright block during -# Gerrit checkin. -# - -export WORKSPACE_DIR=`pwd` -export ADDCOPYRIGHT=${WORKSPACE_DIR}/sbe/tools/hooks/addCopyright - -## run git show to get a list of checked in files -CHECKINFILES=`git show --pretty=format: --name-only -n1 | tr '\n' ' '` -## use git log to determine the year of the commit. -## Since commits have their copyright updated at the time they are -## committed, a commit might have a copyright date in its prolog of -## last year. Set the DATE_OVERRIDE variable to the 'validate' to allow -## slightly-old prologs (ie. ones corresponding to the date in the msg). -export DATE_OVERRIDE=`git log -n1 --date=short | grep "Date" | sed "s/Date: *//" | sed "s/-.*//"` - -echo "========================================================================" - -echo " Checking Copyright blocks for checked-in files:" -echo " $CHECKINFILES" -echo -$ADDCOPYRIGHT validate $CHECKINFILES --copyright-check - -if [ $? -eq 0 ]; then - echo "Copyright Check passed OK, $?" - exit 0 -else - echo "ERROR: $?" - exit 1 -fi diff --git a/sbe/test/citest/create-sandbox b/sbe/test/citest/create-sandbox deleted file mode 100755 index daae3046..00000000 --- a/sbe/test/citest/create-sandbox +++ /dev/null @@ -1,73 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/create-sandbox $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -echo "Creating ODE sandbox..." - -# Ensure backing build is accessible. -if [ ! -d "$BACKING_BUILD" ]; -then - echo "Cannot access the backing build: $BACKING_BUILD" - exit -1 -fi - -# Delete existing sandbox if it exists. -if [ -d "$SANDBOXBASE" ]; -then - echo "----Removing old sandbox." - mksb -undo -auto -rc $SANDBOXRC -dir $SANDBOXROOT -sb $SANDBOXNAME -fi -if [ -d "$SANDBOXBASE" ]; -then - rm -rf $SANDBOXBASE -fi - -# Create sandbox. -mksb -rc $SANDBOXRC -dir $SANDBOXROOT -back $BACKING_BUILD -sb $SANDBOXNAME \ - -m ppc -auto || exit -1 - -# workaround scripts expect $sb variable to be populated. -export sb=$SANDBOXBASE/src - -execute_in_sandbox "ecc --inject ${SBE_IMG_OUT_LOC}/sbe_seeprom.bin --output ${SBE_IMG_OUT_LOC}/sbe_seeprom.bin.ecc --p8 " "ppc" || exit -1 - -# Run presimsetup workarounds. -echo "----Running presimsetup workarounds." -if [ -f ${CITESTPATH}/etc/workarounds.presimsetup ]; -then - ${CITESTPATH}/etc/workarounds.presimsetup || exit -1 -fi - -# Run start_simics to populate simics directories. -echo "----Setting up simics." -execute_in_sandbox "start_simics -no_start -machine $MACHINE -batch_mode" \ - "ppc" || exit -1 - -# Run postsimsetup workarounds. -echo "----Running postsimsetup workarounds." -if [ -f ${CITESTPATH}/etc/workarounds.postsimsetup ]; -then - ${CITESTPATH}/etc/workarounds.postsimsetup || exit -1 -fi - diff --git a/sbe/test/citest/etc/patches/chip.act.patch b/sbe/test/citest/etc/patches/chip.act.patch deleted file mode 100644 index 0b9cf0f0..00000000 --- a/sbe/test/citest/etc/patches/chip.act.patch +++ /dev/null @@ -1,146 +0,0 @@ -184,240c184 -< # ========================================================================== -< # Actions for p9_adu_access and p9_adu_setup procedures -< # ========================================================================== -< #If a read/write is done to the ALTD_DATA Register set the ALTD_STATUS Register so things are as expected -< CAUSE_EFFECT{ -< LABEL=[ADU Read or write to set ALTD_STATUS Register] -< #If the data register is read -< WATCH_READ=[REG(0x00090004)] -< #If the data register is written -< WATCH=[REG(0x00090004)] -< -< #Set the ALTD_STATUS Register so these bits are set: -< #FBC_ALTD_BUSY = WAIT_CMD_ARBIT = WAIT_RESP = OVERRUN_ERR = AUTOINC_ERR = COMMAND_ERR = ADDRESS_ERR = COMMAND_HANG_ERR = DATA_HANG_ERR = PBINIT_MISSING = ECC_CE = ECC_UE = ECC_SUE = 0 -< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,AND] DATA=[LITERAL(64,001FDFFF FFFF1FFF)] -< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,OR] DATA=[LITERAL(64,30000000 00000000)] -< } -< -< #If a read/write is done to the ALTD_DATA Register and the Address only bit is not set then set the DATA_DONE bit to 1 -< CAUSE_EFFECT{ -< LABEL=[ADU Read or write to set ALTD_STATUS[DATA_DONE] bit] -< #If the data register is read -< WATCH_READ=[REG(0x00090004)] -< #If the data register is written -< WATCH=[REG(0x00090004)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] -< -< #Set the DATA_DONE bit -< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] -< } -< -< #If a read/write is done to the ALTD_DATA Register and the Data only bit is not set then set the ADDR_DONE bit to 1 -< CAUSE_EFFECT{ -< LABEL=[ADU Read or write to set ALTD_STATUS[ADDR_DONE] bit] -< #If the data register is read -< WATCH_READ=[REG(0x00090004)] -< #If the data register is written -< WATCH=[REG(0x00090004)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] -< -< #Set the ADDR_DONE bit -< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] -< } -< -< #If a read is done to the ALTD_CMD Register and it sets the lock set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set -< CAUSE_EFFECT{ -< LABEL=[ADU Write to set ALTD_STATUS_BUSY] -< WATCH=[REG(0x00090001)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[11] -< -< #Set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set -< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,ON] BIT=[0] -< } -< #If a write is done to the ALD_CMD_REG to set the FBC_ALTD_START_OP bit it should turn FBC_ALTD_BUSY off -< CAUSE_EFFECT{ -< LABEL=[ADU Write to ALTD_CMD_REG to unset set ALTD_STATUS FBC_ALTD_BUSY bit] -< WATCH=[REG(0x00090001)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] ---- -> ### ADU ACTIONS - READ WRITE RESET ### -242,243c186,265 -< #Unset the ALTD_STATUS Register so the ALTD_STATUS_BUSY is unset -< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,OFF] BIT=[0] ---- -> # Reset ALTD Status Reg -> CAUSE_EFFECT { -> LABEL=[RESET FSM ALTD Status Register] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[4] #Reset FSM bit -> EFFECT: TARGET=[REG(0x00090003)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)] -> } -> -> # ADU Transaction Complete Status - Busy Bit Low -> CAUSE_EFFECT { -> LABEL=[ALTD_BUSY Status Register Clear] -> WATCH=[REG(0x00090003)] # ALTD_Status_Reg -> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AUTO INCR Mode OFF -> -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,OFF] BIT=[0] #BUSY Bit low -> } -> -> # Read without AutoIncr -> CAUSE_EFFECT{ -> LABEL=[READ Mainstore without AutoIncr] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg -> -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> -> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> } -> -> # Read with AutoIncr -> CAUSE_EFFECT{ -> LABEL=[READ Mainstore with AutoIncr] -> WATCH_READ=[REG(0x00090004)] # ALTD_Data_reg -> -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on -> -> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory -> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64,00000000 0000FFFF)] # incr addr reg by 8 -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> } -> -> # Write without AutoIncr -> CAUSE_EFFECT{ -> LABEL=[WRITE Mainstore without AutoIncr] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg -> WATCH=[REG(0x00090004)] # ALTD_Data_reg -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AutoInc bit off -> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> } -> -> # Write with AutoIncr -> CAUSE_EFFECT{ -> LABEL=[WRITE Mainstore with AutoIncr] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_reg -> WATCH=[REG(0x00090004)] # ALTD_Data_reg -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on -> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory -> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 00000000 0000FFFF)] # incr addr reg by 8 -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -265a288 -> EFFECT: TARGET=[MODULE(executeInstruction, MYCORE)] OP=[MODULECALL] DATA=[REG(MYCHIPLET, 0x00010A4F)] diff --git a/sbe/test/citest/etc/patches/patchlist.txt b/sbe/test/citest/etc/patches/patchlist.txt deleted file mode 100644 index 4fd0444a..00000000 --- a/sbe/test/citest/etc/patches/patchlist.txt +++ /dev/null @@ -1,14 +0,0 @@ -# Example Format -#Brief description of the problem or reason for patch -#-RTC: Task/Story used to remove this patch -#-CQ: Defect/Req for checking the changes into fips910 -#-Files: list of files -#-Coreq: list of associated changes, e.g. workarounds.presimsetup - -RTC: 144728 -Files : pervasive.act.patch. Currently SUET does not support FSIMBOX KW. Once - support is in, remove this patch. - -RTC: 128984 -Files: chip.act.patch. Added call for executeInstruction module call. - p9.inst.patch. Added P9 specific commands for ramming. diff --git a/sbe/test/citest/etc/patches/pervasive.act.patch b/sbe/test/citest/etc/patches/pervasive.act.patch deleted file mode 100644 index 5531bef6..00000000 --- a/sbe/test/citest/etc/patches/pervasive.act.patch +++ /dev/null @@ -1,28 +0,0 @@ -55c55 -< WATCH=[REG(0x00050018)] ---- -> WATCH=[FSIMBOX(0x18)] -57c57 -< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[12] ---- -> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[12] -59c59 -< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[0] ---- -> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[0] -67c67 -< WATCH=[REG(0x00050018)] ---- -> WATCH=[FSIMBOX(0x18)] -69c69 -< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4] ---- -> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[4] -78c78 -< WATCH=[REG(0x00050018)] ---- -> WATCH=[FSIMBOX(0x18)] -80c80 -< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4] ---- -> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[4] diff --git a/sbe/test/citest/etc/patches/powermgmt.act.patch b/sbe/test/citest/etc/patches/powermgmt.act.patch deleted file mode 100644 index efb03845..00000000 --- a/sbe/test/citest/etc/patches/powermgmt.act.patch +++ /dev/null @@ -1,1057 +0,0 @@ -43,112d42 -< ## Actions for Procedure - p9_pm_occ_control -< ## -< -< CAUSE_EFFECT { -< LABEL=[PPC405 HALT] -< WATCH=[REG(0x0006D006)] -< CAUSE: TARGET=[REG(0x0006D006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 02000000 00000000)] -< #suet PPC405_UNHALT:tc1- EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,OFF] BIT=[31] -< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31] -< } -< -< ## -< ## Actions for Procedure - p9_pm_occ_gpe_init -< ## -< -< CAUSE_EFFECT { -< LABEL=[OCC GPE0 HALT] -< WATCH=[REG(0x00060010)] -< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1] -< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2] -< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3] -< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0] -< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[OCC GPE1 HALT] -< WATCH=[REG(0x00062010)] -< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1] -< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2] -< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3] -< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0] -< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0] -< } -< -< # Upon writing the PU_OCB_PIB_OCR[DBG_HALT} bit, set the OCCLFIR_PPC405_DBGSTOPACK_BIT. -< CAUSE_EFFECT { -< LABEL=[PPC405 SAFE_HALT] -< WATCH=[REG(00x0006D002)] -< CAUSE: TARGET=[REG(0x0006D002)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00200000 00000000)] -< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31] -< } -< -< -< ## -< ## Actions for Procedure - p9_pm_occ_gpe_init -< ## -< -< CAUSE_EFFECT { -< LABEL=[OCC GPE0 HALT] -< WATCH=[REG(0x00060010)] -< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1] -< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2] -< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3] -< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0] -< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[OCC GPE1 HALT] -< WATCH=[REG(0x00062010)] -< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1] -< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2] -< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3] -< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0] -< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0] -< } -< -< -< ## -134,409c64 -< -< ## Core0 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x200F0110)] -< CAUSE: TARGET=[REG(0x200F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] -< EFFECT: TARGET=[REG(0x200F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x200F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core0 End -< -< ## Core1 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x210F0110)] -< CAUSE: TARGET=[REG(0x210F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)] -< EFFECT: TARGET=[REG(0x210F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x210F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x210F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x210F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core1 End -< -< ## Core2 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x220F0110)] -< CAUSE: TARGET=[REG(0x220F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x220F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] -< EFFECT: TARGET=[REG(0x220F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x220F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x220F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x220F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core2 End -< -< ## Core3 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x230F0110)] -< CAUSE: TARGET=[REG(0x230F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)] -< EFFECT: TARGET=[REG(0x230F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x230F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x230F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x230F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core3 End -< -< ## Core4 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x240F0110)] -< CAUSE: TARGET=[REG(0x240F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)] -< EFFECT: TARGET=[REG(0x240F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x240F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x240F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x240F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core4 End -< -< ## Core5 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x250F0110)] -< CAUSE: TARGET=[REG(0x250F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)] -< EFFECT: TARGET=[REG(0x250F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x250F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x250F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x250F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core5 End -< -< ## Core6 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x260F0110)] -< CAUSE: TARGET=[REG(0x260F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x260F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] -< EFFECT: TARGET=[REG(0x260F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x260F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x260F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x260F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core6 End -< -< ## Core7 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x270F0110)] -< CAUSE: TARGET=[REG(0x270F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)] -< EFFECT: TARGET=[REG(0x270F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x270F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x270F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x270F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core7 End -< -< ## Core8 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x280F0110)] -< CAUSE: TARGET=[REG(0x280F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)] -< EFFECT: TARGET=[REG(0x280F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x280F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x280F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core8 End -< -< ## Core9 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x290F0110)] -< CAUSE: TARGET=[REG(0x290F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)] -< EFFECT: TARGET=[REG(0x290F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x290F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x290F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x290F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core9 End -< -< ## Core10 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x2A0F0110)] -< CAUSE: TARGET=[REG(0x2A0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)] -< EFFECT: TARGET=[REG(0x2A0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2A0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2A0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2A0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core10 End -< -< ## Core11 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x2B0F0110)] -< CAUSE: TARGET=[REG(0x2B0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)] -< EFFECT: TARGET=[REG(0x2B0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2B0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2B0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2B0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core11 End -< -< ## Core12 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x2C0F0110)] -< CAUSE: TARGET=[REG(0x2C0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)] -< EFFECT: TARGET=[REG(0x2C0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2C0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2C0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2C0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core12 End -< -< ## Core13 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x2D0F0110)] -< CAUSE: TARGET=[REG(0x2D0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)] -< EFFECT: TARGET=[REG(0x2D0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2D0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2D0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2D0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core13 End -< -< ## Core14 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x2E0F0110)] -< CAUSE: TARGET=[REG(0x2E0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)] -< EFFECT: TARGET=[REG(0x2E0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2E0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2E0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2E0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core14 End -< -< ## Core15 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x2F0F0110)] -< CAUSE: TARGET=[REG(0x2F0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)] -< EFFECT: TARGET=[REG(0x2F0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2F0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2F0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x2F0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core15 End -< -< ## Core16 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x300F0110)] -< CAUSE: TARGET=[REG(0x300F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)] -< EFFECT: TARGET=[REG(0x300F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x300F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x300F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x300F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core16 End -< -< ## Core17 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x310F0110)] -< CAUSE: TARGET=[REG(0x310F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)] -< EFFECT: TARGET=[REG(0x310F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x310F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x310F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x310F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core17 End -< -< ## Core18 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x320F0110)] -< CAUSE: TARGET=[REG(0x320F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)] -< EFFECT: TARGET=[REG(0x320F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x320F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x320F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x320F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core18 End -< -< ## Core19 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x330F0110)] -< CAUSE: TARGET=[REG(0x330F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)] -< EFFECT: TARGET=[REG(0x330F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x330F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x330F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x330F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core19 End -< -< ## Core20 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x340F0110)] -< CAUSE: TARGET=[REG(0x340F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)] -< EFFECT: TARGET=[REG(0x340F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x340F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x340F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x340F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core20 End -< -< ## Core21 Start -< CAUSE_EFFECT { ---- -> CAUSE_EFFECT CHIPLETS ec { -411,478c66,89 -< WATCH=[REG(0x350F0110)] -< CAUSE: TARGET=[REG(0x350F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)] -< EFFECT: TARGET=[REG(0x350F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x350F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x350F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x350F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core21 End -< -< ## Core22 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x360F0110)] -< CAUSE: TARGET=[REG(0x360F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)] -< EFFECT: TARGET=[REG(0x360F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x360F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x360F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x360F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core22 End -< -< ## Core23 Start -< CAUSE_EFFECT { -< LABEL=[SSH_SRC_WRITE] -< WATCH=[REG(0x370F0110)] -< CAUSE: TARGET=[REG(0x370F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)] -< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)] -< EFFECT: TARGET=[REG(0x370F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x370F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x370F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< EFFECT: TARGET=[REG(0x370F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -< } -< ## Core23 End -< -< ## -< # Actions for Procedure - p9_block_wakeup_intr -< ## -< -< # Core Power Management Mode Register -< CAUSE_EFFECT { -< LABEL=[CPMMR Write OR of PPM Write Override] -< WATCH=[REG(0x290F0108)] -< CAUSE: TARGET=[REG(0x290F0108)] OP=[BIT,ON] BIT=[1] -< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,ON] BIT=[1] -< } -< -< CAUSE_EFFECT { -< LABEL=[CPMMR Write CLEAR of PPM Write Override] -< WATCH=[REG(0x290F0107)] -< CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[1] -< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[1] -< } -< -< # General Power Management Mode Register -< CAUSE_EFFECT { -< LABEL=[GPMMR Write OR of Block Wakeup Events] -< WATCH=[REG(0x290F0102)] -< CAUSE: TARGET=[REG(0x290F0102)] OP=[BIT,ON] BIT=[6] -< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[6] -< } -< -< CAUSE_EFFECT { -< LABEL=[GPMMR Write CLEAR of PPM Write Override] -< WATCH=[REG(0x290F0101)] -< CAUSE: TARGET=[REG(0x290F0101)] OP=[BIT,ON] BIT=[6] -< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[6] ---- -> WATCH=[REG(MYCHIPLET, 0x0F0110)] -> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F0110)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)] -> EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] -> } -> -> ## Action triggered when all threads are idle -> # Used for istep 16 to have hostboot properly wake up on SBE-set PSU -> # interrupt as well as to have p9_sbe_check_master_stop15.C properly -> # execute in firmware simics. -> # TODO: RTC 147787 -> CAUSE_EFFECT CHIPLETS ec { -> LABEL=[Master Winkle LPCR] -> WATCH=[IDLESTATE(MYCHIPLET,0x0)] -> # look for stop15 -> CAUSE: TARGET=[IDLESTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,0F000000)] MASK=[LITERAL(32,FF000000)] -> # Restore LPCR for wake-up options. -> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[17] -> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[49] -> # Set required C_PPM_SSHOTR register required by procedure -> EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,8BB00000 FFFFFFFF)] -514c125 -< ## Actions for p9_pm_ocb_init ---- -> # Actions for Procedure - p9_hcd_core_poweron / p9_hcd_cache_poweron -517,524c128,133 -< CAUSE_EFFECT { -< LABEL=[Channel 0 linear stream] -< WATCH=[REG(0x0006D013)] -< WATCH=[REG(0x0006D012)] -< CAUSE: TARGET=[REG(0x0006D013)] OP=[BIT,ON] BIT=[4] -< CAUSE: TARGET=[REG(0x0006D012)] OP=[BIT,ON] BIT=[5] -< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,ON] BIT=[4] -< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,OFF] BIT=[5] ---- -> CAUSE_EFFECT CHIPLETS ec cache { -> LABEL=[Power on core/cache vdd pfet then fsm is idle and sense is enabled] -> WATCH=[REG(MYCHIPLET, 0x0F011A)] -> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[0] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[42] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[0] -527,1071c136 -< CAUSE_EFFECT { -< LABEL=[Channel 1 linear stream] -< WATCH=[REG(0x0006D033)] -< WATCH=[REG(0x0006D032)] -< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] -< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[5] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[5] -< } -< -< CAUSE_EFFECT { -< LABEL=[Channel 1 circular push interupt enable] -< WATCH=[REG(0x0006D033)] -< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[3] -< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] -< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[3] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5] -< } -< -< CAUSE_EFFECT { -< LABEL=[Channel 1 circular push interrupt disable] -< WATCH=[REG(0x0006D033)] -< WATCH=[REG(0x0006D032)] -< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[3] -< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] -< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[3] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] -< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5] -< } -< -< CAUSE_EFFECT { -< LABEL=[Channel 2 linear stream] -< WATCH=[REG(0x0006D053)] -< WATCH=[REG(0x0006D052)] -< CAUSE: TARGET=[REG(0x0006D053)] OP=[BIT,ON] BIT=[4] -< CAUSE: TARGET=[REG(0x0006D052)] OP=[BIT,ON] BIT=[5] -< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,ON] BIT=[4] -< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,OFF] BIT=[5] -< } -< -< CAUSE_EFFECT { -< LABEL=[Channel 3 linear stream] -< WATCH=[REG(0x0006D073)] -< WATCH=[REG(0x0006D072)] -< CAUSE: TARGET=[REG(0x0006D073)] OP=[BIT,ON] BIT=[4] -< CAUSE: TARGET=[REG(0x0006D072)] OP=[BIT,ON] BIT=[5] -< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,ON] BIT=[4] -< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,OFF] BIT=[5] -< ## Actions for Procedure - p9_setup_evid -< ## -< -< CAUSE_EFFECT { -< LABEL=[AVSBus Write data register 0B] -< WATCH=[REG(0x0006C718)] -< CAUSE: TARGET=[REG(0x0006C718)] OP=[BIT,ON] BIT=[1] -< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[AVSBus Status register 0B] -< WATCH_READ=[REG(0x0006C716)] -< CAUSE: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,OFF] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[AVSBus Write data register 1B] -< WATCH=[REG(0x0006C738)] -< CAUSE: TARGET=[REG(0x0006C738)] OP=[BIT,ON] BIT=[1] -< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[AVSBus Status register 1B] -< WATCH_READ=[REG(0x0006C736)] -< CAUSE: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,OFF] BIT=[0] -< } -< -< ## Core 0 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x200F011A)] -< CAUSE: TARGET=[REG(0x200F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x200F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x200F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 0 End -< ## Core 1 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x210F011A)] -< CAUSE: TARGET=[REG(0x210F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x210F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x210F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 1 End -< ## Core 2 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x220F011A)] -< CAUSE: TARGET=[REG(0x220F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x220F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x220F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 2 End -< ## Core 3 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x230F011A)] -< CAUSE: TARGET=[REG(0x230F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x230F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x230F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 3 End -< ## Core 4 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x240F011A)] -< CAUSE: TARGET=[REG(0x240F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x240F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x240F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 4 End -< ## Core 5 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x250F011A)] -< CAUSE: TARGET=[REG(0x250F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x250F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x250F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 5 End -< ## Core 6 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x260F011A)] -< CAUSE: TARGET=[REG(0x260F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x260F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x260F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 6 End -< ## Core 7 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x270F011A)] -< CAUSE: TARGET=[REG(0x270F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x270F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x270F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 7 End -< ## Core 8 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x280F011A)] -< CAUSE: TARGET=[REG(0x280F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x280F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x280F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 8 End -< ## Core 9 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x290F011A)] -< CAUSE: TARGET=[REG(0x290F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x290F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x290F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 9 End -< ## Core 10 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x2a0F011A)] -< CAUSE: TARGET=[REG(0x2a0F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x2a0F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x2a0F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 10 End -< ## Core 11 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x2b0F011A)] -< CAUSE: TARGET=[REG(0x2b0F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x2b0F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x2b0F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 11 End -< ## Core 12 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x2c0F011A)] -< CAUSE: TARGET=[REG(0x2c0F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x2c0F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x2c0F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 12 End -< ## Core 13 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x2d0F011A)] -< CAUSE: TARGET=[REG(0x2d0F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x2d0F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x2d0F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 13 End -< ## Core 14 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x2e0F011A)] -< CAUSE: TARGET=[REG(0x2e0F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x2e0F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x2e0F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 14 End -< ## Core 15 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x2f0F011A)] -< CAUSE: TARGET=[REG(0x2f0F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x2f0F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x2f0F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 15 End -< ## Core 16 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x300F011A)] -< CAUSE: TARGET=[REG(0x300F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x300F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x300F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 16 End -< ## Core 17 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x310F011A)] -< CAUSE: TARGET=[REG(0x310F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x310F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x310F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 17 End -< ## Core 18 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x320F011A)] -< CAUSE: TARGET=[REG(0x320F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x320F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x320F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 18 End -< ## Core 19 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x330F011A)] -< CAUSE: TARGET=[REG(0x330F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x330F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x330F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 19 End -< ## Core 20 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x340F011A)] -< CAUSE: TARGET=[REG(0x340F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x340F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x340F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 20 End -< ## Core 21 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x350F011A)] -< CAUSE: TARGET=[REG(0x350F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x350F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x350F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 21 End -< ## Core 22 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x360F011A)] -< CAUSE: TARGET=[REG(0x360F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x360F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x360F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 22 End -< ## Core 23 Start -< -< ## -< # Actions for Procedure - p9_hcd_core_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x370F011A)] -< CAUSE: TARGET=[REG(0x370F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x370F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x370F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< # Core 23 End -< ## EQ 0 Start -< -< ## -< # Actions for Procedure - p9_hcd_cache_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x100F011A)] -< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x100F011A)] -< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[2] -< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[50] -< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[2] -< } -< -< ## EQ 0 End -< -< ## EQ 1 Start -< -< ## -< # Actions for Procedure - p9_hcd_cache_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x110F011A)] -< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x110F011A)] -< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[2] -< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[50] -< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[2] -< } -< -< ## EQ 1 End -< -< ## EQ 2 Start -< -< ## -< # Actions for Procedure - p9_hcd_cache_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x120F011A)] -< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x120F011A)] -< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[2] -< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[50] -< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[2] -< } -< -< ## EQ 2 End -< -< ## EQ 3 Start -< -< ## -< # Actions for Procedure - p9_hcd_cache_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x130F011A)] -< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x130F011A)] -< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[2] -< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[50] -< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[2] -< } -< -< ## EQ 3 End -< -< ## EQ 4 Start -< -< ## -< # Actions for Procedure - p9_hcd_cache_poweron -< ## -< -< CAUSE_EFFECT { ---- -> CAUSE_EFFECT CHIPLETS cache { -1073,1084c138,141 -< WATCH=[REG(0x140F011A)] -< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x140F011A)] -< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[2] -< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[50] -< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[2] ---- -> WATCH=[REG(MYCHIPLET, 0x0F011A)] -> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[2] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[50] -> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[2] -1087,1112d143 -< ## EQ 4 End -< -< ## EQ 5 Start -< -< ## -< # Actions for Procedure - p9_hcd_cache_poweron -< ## -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x150F011A)] -< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[0] -< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[42] -< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[0] -< } -< -< CAUSE_EFFECT { -< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] -< WATCH=[REG(0x150F011A)] -< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[2] -< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[50] -< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[2] -< } -< -< ## EQ 5 End -< diff --git a/sbe/test/citest/etc/patches/standalone.simics.patch b/sbe/test/citest/etc/patches/standalone.simics.patch deleted file mode 100644 index bdc40fd8..00000000 --- a/sbe/test/citest/etc/patches/standalone.simics.patch +++ /dev/null @@ -1,4 +0,0 @@ -52c52 -< ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64 ---- -> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "80000000_00000000" 64 diff --git a/sbe/test/citest/etc/workarounds.postsimsetup b/sbe/test/citest/etc/workarounds.postsimsetup deleted file mode 100755 index adfdfe26..00000000 --- a/sbe/test/citest/etc/workarounds.postsimsetup +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/etc/workarounds.postsimsetup $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -## Workarounds that are run after start_simics is executed for the first time -## to setup the sandbox -## - -### Example applying a patch to cec-chip files -#echo "+++ Updating something wonderful in a simics file" -#mkdir -p $sb/simu/data/cec-chip/ -#cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip -#patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $SBEROOT/src/build/citest/etc/patches/my_patch_File - -# NOTE: The below patch removes mailbox settings in standalone.simics (comes -# from HB) that cause the SBE to run in plck mode. For our CI, we need the SBE -# to be in istep mode. This patch is likely never going to be removed as long as -# we need our CI to run in istep mode. -echo "+++ Patching standalone.simics" -mkdir -p $SANDBOXBASE/obj/ppc/simu/scripts/hbfw -cp $BACKING_BUILD/obj/ppc/simu/scripts/hbfw/standalone.simics $SANDBOXBASE/obj/ppc/simu/scripts/hbfw -patch -p0 $SANDBOXBASE/obj/ppc/simu/scripts/hbfw/standalone.simics $SBEROOT/sbe/test/citest/etc/patches/standalone.simics.patch - diff --git a/sbe/test/citest/etc/workarounds.presimsetup b/sbe/test/citest/etc/workarounds.presimsetup deleted file mode 100755 index 284b0293..00000000 --- a/sbe/test/citest/etc/workarounds.presimsetup +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/etc/workarounds.presimsetup $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -#### Examples #### -#echo "+++ Some message about why you need to do this." -#mkdir -p $sb/simu/data -#egrep -v "WSALIAS DEFAULT FIPSLEVEL|WSALIAS DEFAULT SIMICSLEVEL" $BACKING_BUILD/src/simu/data/simicsInfo > $sb/simu/data/simicsInfo -#echo "WSALIAS DEFAULT FIPSLEVEL env/gfwb/simics-4.2.0/simics-4.2.83/fips/fld36/fi120201a700.42" >> $sb/simu/data/simicsInfo -#echo "WSALIAS DEFAULT SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.83/bin" >> $sb/simu/data/simicsInfo diff --git a/sbe/test/citest/populate-sandbox b/sbe/test/citest/populate-sandbox deleted file mode 100755 index 4e2e2f10..00000000 --- a/sbe/test/citest/populate-sandbox +++ /dev/null @@ -1,61 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/populate-sandbox $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -# Ensure sandbox exists (create-sandbox has been called). -if [ -z $SANDBOXBASE ]; -then - echo "SANDBOXBASE variable uninitialized.." - exit -1 -fi - -if [ ! -d "$SANDBOXBASE" ]; -then - echo "Cannot find sandbox: $SANDBOXBASE" - exit -1 -fi - -# Create test directory. -mkdir -p $SBETESTDIR || exit -1 - -# Create test directory. -mkdir -p $SBEFW_IMG_DIR || exit -1 - -# Copy sbe binaries -cp $SBEROOT/obj/*.bin $SBEFW_IMG_DIR/ || exit -1 -cp $SBEROOT/obj/simics.tar $SBEFW_DIR/ || exit -1 -# Compile sbe code in sandbox to copy binaries at right place -echo "---Setup sandbox for sbe binaries." - -execute_in_sandbox "cd $SBEFW_DIR; mk -a" \ - "ppc" || exit -1 - -execute_in_sandbox "cd $SBEFW_DIR; mk install_all" \ - "ppc" || exit -1 - - -# Copy test files. -cp -r $SBEROOT/sbe/test/* $SBETESTDIR/ || exit -1 - diff --git a/sbe/test/citest/sbetest-start.sh b/sbe/test/citest/sbetest-start.sh deleted file mode 100755 index c70cc5d7..00000000 --- a/sbe/test/citest/sbetest-start.sh +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/sbetest-start.sh $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -if [ -z $SBE_CI_ENV_SETUP ]; -then - unset $SANDBOXBASE - unset $SANDBOXNAME - source "$SBEROOT/sbe/test/citest/setup-env" -fi - -# Front end to autocitest - script to execute unit tests under simics. -# -## when jenkins runs it will create a workspace with the built code tree -## and drop us into it. -autocitest ${BACKING_BUILD} - -exit $? diff --git a/sbe/test/citest/setup-env b/sbe/test/citest/setup-env deleted file mode 100755 index a9ceea69..00000000 --- a/sbe/test/citest/setup-env +++ /dev/null @@ -1,84 +0,0 @@ -#!/bin/sh -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/citest/setup-env $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -export CITESTPATH=${SBEROOT}/sbe/test/citest -export PATH=${CITESTPATH}:${PATH} - -# If we are running under Jenkins we need to pick a random-ish sandbox name -# so that the autoipl tools do not have a /tmp name collision. -if [ -z $JOB_NAME -o -z $BUILD_NUMBER ]; -then - SBECI_SANDBOX="test_sb" -else - export RUNNING_UNDER_JENKINS=1 - SBECI_SANDBOX=`echo $JOB_NAME $BUILD_NUMBER | md5sum | head -c10` -fi - -# Setup sandbox location variables. -if [ -z $SANDBOXROOT ]; -then - export SANDBOXROOT=${SBEROOT} -fi - -if [ -z $SANDBOXNAME ] || [ "$RUNNING_UNDER_JENKINS" = "1" ]; -then - export SANDBOXNAME=${SBECI_SANDBOX} -fi - -export SANDBOXBASE=${SANDBOXROOT}/${SANDBOXNAME} - -if [ -z $SANDBOXRC ]; -then - export SANDBOXRC=${SANDBOXROOT}/sbesandboxrc -fi -# Useful utility function. -execute_in_sandbox() -{ - WORKON_CMD="workon -rc ${SANDBOXRC} -sb ${SANDBOXNAME} -m $2 " - echo $1 > ${SANDBOXBASE}/src/sandbox_execute_cmd - chmod 700 ${SANDBOXBASE}/src/sandbox_execute_cmd - - TEST="${WORKON_CMD} -c ./sandbox_execute_cmd " - echo $TEST - ${WORKON_CMD} -c ./sandbox_execute_cmd - - if [ $? -ne 0 ]; then - return 1 - fi - - rm ${SANDBOXBASE}/src/sandbox_execute_cmd -} -export -f execute_in_sandbox - -# Setup machine type. -export MACHINE=${MACHINE:-$DEFAULT_MACHINE} - -export SBETESTDIR=$SANDBOXBASE/simics/targets/p9_nimbus/sbeTest -export SBEFW_DIR=$SANDBOXBASE/src/sbei/sbfw/ -export SBEFW_IMG_DIR=$SANDBOXBASE/src/sbei/sbfw/img -export AUTOSIM_FFDC_XML=$SBETESTDIR/ffdc.xml -export SBE_TEST_XML=$SBETESTDIR/test.xml -# Indicate we setup the CI environment. -export SBE_CI_ENV_SETUP=1 diff --git a/sbe/test/ffdc.xml b/sbe/test/ffdc.xml deleted file mode 100755 index 6e2f36ff..00000000 --- a/sbe/test/ffdc.xml +++ /dev/null @@ -1,18 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - <!--Collect FFDC --> - <test> - <subtest> - <testcase> - <simcmd>sbe-trace 0</simcmd> - </testcase> - <testcase> - <simcmd>p9Proc0.sbe.ppe->ppe_state</simcmd> - </testcase> - <testcase> - <simcmd>p9Proc0.proc_fifo->upstream_hw_fifo</simcmd> - </testcase> - <testcase> - <simcmd>p9Proc0.proc_fifo->downstream_hw_fifo</simcmd> - </testcase> - </subtest> - </test> diff --git a/sbe/test/test.xml b/sbe/test/test.xml deleted file mode 100755 index 00612be3..00000000 --- a/sbe/test/test.xml +++ /dev/null @@ -1,50 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: sbe/test/test.xml $ --> -<!-- --> -<!-- OpenPOWER sbe Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> - -<integrationtest> - <platform startsimargs="--notar --norun --sim_parms -nre"> - <machine>%%machine%%</machine> - <test> - <testcase> - <simcmd>p9Proc0.pib_psu->tppsu_tpbr_interrupt_msg_available=[NIL]</simcmd> - </testcase> - <include>../simics/targets/p9_nimbus/sbeTest/testIstep.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testGeneric.xml</include> - <!-- TODO via 158768: Enable pba test case--> - <!-- include>../simics/targets/p9_nimbus/sbeTest/testPutGetMem.xml</include --> - <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testCntlInstruction.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testRegAccess.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testFifoReset.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testExecutorPutRing.xml</include> - <include>../simics/targets/p9_nimbus/sbeTest/testGetRing.xml</include> - <testcase> - <simcmd>sbe-trace 0</simcmd> - </testcase> - </test> - </platform> -</integrationtest> diff --git a/sbe/test/testAbort.py b/sbe/test/testAbort.py deleted file mode 100755 index eca8a6eb..00000000 --- a/sbe/test/testAbort.py +++ /dev/null @@ -1,58 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testAbort.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -TESTDATA = [0,0,0,2, - 0,0,0xA8,0x04 ] - -EXPDATA = [0xc0,0xde,0xa8,0x04, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x3]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testAduMem.xml b/sbe/test/testAduMem.xml deleted file mode 100644 index dde43724..00000000 --- a/sbe/test/testAduMem.xml +++ /dev/null @@ -1,19 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_ecc.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_itag.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_withEccItag.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/sbe/test/testAduMem_ecc.py b/sbe/test/testAduMem_ecc.py deleted file mode 100644 index 358d9ae9..00000000 --- a/sbe/test/testAduMem_ecc.py +++ /dev/null @@ -1,45 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -LOOP_COUNT = 1 - -GETMEMADU_TESTDATA_ECC = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xAD, #CoreChipletId/EccByte/Flags - CacheInhibit/FastMode/NoTag/Ecc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x20] # length of data - -GETMEMADU_EXPDATA_ECC = [0x00,0x00,0x00,0x24, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - # GetMemAdu with Ecc - testUtil.writeUsFifo( GETMEMADU_TESTDATA_ECC) - testUtil.writeEot( ) - - testUtil.readDsEntry ( 9 ) - testUtil.readDsFifo( GETMEMADU_EXPDATA_ECC) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testAduMem_itag.py b/sbe/test/testAduMem_itag.py deleted file mode 100644 index 33160602..00000000 --- a/sbe/test/testAduMem_itag.py +++ /dev/null @@ -1,43 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -GETMEMADU_TESTDATA_ITAG = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xB5, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/Tag/NoEcc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x40] # length of data - -GETMEMADU_EXPDATA_ITAG = [0x00,0x00,0x00,0x48, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - # GetMemAdu with Itag - testUtil.writeUsFifo( GETMEMADU_TESTDATA_ITAG ) - testUtil.writeEot( ) - - testUtil.readDsEntry ( 18 ) - testUtil.readDsFifo( GETMEMADU_EXPDATA_ITAG ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testAduMem_noEccNoItag.py b/sbe/test/testAduMem_noEccNoItag.py deleted file mode 100644 index 6f1d3350..00000000 --- a/sbe/test/testAduMem_noEccNoItag.py +++ /dev/null @@ -1,76 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -LOOP_COUNT = 1 - -PUTMEMADU_CNTLDATA = [0,0,0,0, - 0,0,0xA4,0x02, - 0,0,0x0,0xA5, #CoreChipletId/EccByte/Flags -> NoEccOverride/CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x10] # length of data - -PUTMEMADU_TESTDATA = [0xab,0xcd,0xef,0x12, - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9] - -PUTMEMADU_EXPDATA = [0x00,0x00,0x00,0x10, # length of data - 0xc0,0xde,0xa4,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - - -GETMEMADU_TESTDATA = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xA5, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x10] # length of data - -GETMEMADU_EXPDATA = [0xab,0xcd,0xef,0x12, #data - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9, - 0x00,0x00,0x00,0x10, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - #PutMemAdu Test - testUtil.writeUsFifo( PUTMEMADU_CNTLDATA ) - testUtil.writeUsFifo( PUTMEMADU_TESTDATA ) - testUtil.writeEot( ) - - testUtil.readDsFifo( PUTMEMADU_EXPDATA ) - testUtil.readEot( ) - - # GetMemAdu test - testUtil.writeUsFifo( GETMEMADU_TESTDATA ) - testUtil.writeEot( ) - - testUtil.readDsFifo( GETMEMADU_EXPDATA ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testAduMem_withEccItag.py b/sbe/test/testAduMem_withEccItag.py deleted file mode 100644 index 5980a9a4..00000000 --- a/sbe/test/testAduMem_withEccItag.py +++ /dev/null @@ -1,43 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -GETMEMADU_TESTDATA_ECC_ITAG = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xBD, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/Tag/Ecc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x40] # length of data - -GETMEMADU_EXPDATA_ECC_ITAG = [0x00,0x00,0x00,0x50, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - # GetMemAdu with Ecc with Itag test - testUtil.writeUsFifo( GETMEMADU_TESTDATA_ECC_ITAG ) - testUtil.writeEot( ) - - testUtil.readDsEntry ( 20 ) - testUtil.readDsFifo( GETMEMADU_EXPDATA_ECC_ITAG ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testAduMem_withEccWithItagReadWrite.py b/sbe/test/testAduMem_withEccWithItagReadWrite.py deleted file mode 100644 index 8e2de7a0..00000000 --- a/sbe/test/testAduMem_withEccWithItagReadWrite.py +++ /dev/null @@ -1,73 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -LOOP_COUNT = 1 - -PUTMEMADU_CNTLDATA = [0,0,0,0, - 0,0,0xA4,0x02, - 0,0x07,0x0,0xBD, #CoreChipletId/EccByteTrue/Flags -> EccOverride/CacheInhibit/FastMode/Tag/EccOverride/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x08] # length of data - -PUTMEMADU_TESTDATA = [0xab,0xcd,0xef,0x12, - 0xba,0xdc,0xfe,0x21] - -PUTMEMADU_EXPDATA = [0x00,0x00,0x00,0x0a, # length of data - 0xc0,0xde,0xa4,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - - - -GETMEMADU_TESTDATA = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xBD, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/Tag/Ecc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x08] # length of data - -GETMEMADU_EXPDATA = [0xab,0xcd,0xef,0x12, #data - 0xba,0xdc,0xfe,0x21, - 0x01,0x07,0,0, #First Byte is iTag / Second Byte is ECC - 0x00,0x00,0x00,0x0a, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - #PutMemAdu Test - testUtil.writeUsFifo( PUTMEMADU_CNTLDATA ) - testUtil.writeUsFifo( PUTMEMADU_TESTDATA ) - testUtil.writeEot( ) - - testUtil.readDsFifo( PUTMEMADU_EXPDATA ) - testUtil.readEot( ) - - # GetMemAdu test - testUtil.writeUsFifo( GETMEMADU_TESTDATA ) - testUtil.writeEot( ) - - testUtil.readDsFifo( GETMEMADU_EXPDATA ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testCntlInstruction.py b/sbe/test/testCntlInstruction.py deleted file mode 100644 index 76216a8b..00000000 --- a/sbe/test/testCntlInstruction.py +++ /dev/null @@ -1,474 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testCntlInstruction.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 1 - -#Invalid Input -INST_INVALID_TESTDATA = [0,0,0,3, - 0,0,0xa7,0x01, - 0,1,0x20,0xee] - - -INST_INVALID_EXPDATA_ERR = [0xc0,0xde,0xa7,0x01, - 0x00,0x02,0x00,0x0A, - 0x00,0x00,0x00,0x03] - -# STOP Ins -# core 0 thread 0 STOP WARN FLAG as true -INST_STOP_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x01] - -# core 0 thread 1 STOP WARN FLAG as true -INST_STOP_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x11] - -# core 0 thread 2 STOP WARN FLAG as true -INST_STOP_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x21] - -# core 0 thread 3 STOP with WARN FLAG as true -INST_STOP_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x31] - -# core 0 thread 0 STOP WARN FLAG as false -INST_STOP_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x01] - -# core 0 thread 1 STOP WARN FLAG as false -INST_STOP_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x11] - -# core 0 thread 2 STOP WARN FLAG as false -INST_STOP_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x21] - -# core 0 thread 3 STOP WARN FLAG as false -INST_STOP_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x31] - -# Stop All thread in Core0 with warn flag true -INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0xf1] - -# Stop All thread in Core0 with warn flag false -INST_STOP0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0xf1] - - -# START Ins -# core 0 thread 0 START WARN FLAG as true -INST_START_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x00] - -# core 0 thread 1 START WARN FLAG as true -INST_START_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x10] - -# core 0 thread 2 START WARN FLAG as true -INST_START_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x20] - -# core 0 thread 3 START with WARN FLAG as true -INST_START_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x30] - -# core 0 thread 0 START WARN FLAG as false -INST_START_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x00] - -# core 0 thread 1 START WARN FLAG as false -INST_START_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x10] - -# core 0 thread 2 START WARN FLAG as false -INST_START_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x20] - -# core 0 thread 3 START WARN FLAG as false -INST_START_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x30] - -# Start All thread in Core0 with warn flag true -INST_START0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0xf0] - -# Start All thread in Core0 with warn flag false -INST_START0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0xf0] - -# STEP Ins -# core 0 thread 0 STEP WARN FLAG as true -INST_STEP_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x02] - -# core 0 thread 1 STEP WARN FLAG as true -INST_STEP_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x12] - -# core 0 thread 2 STEP WARN FLAG as true -INST_STEP_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x22] - -# core 0 thread 3 STEP with WARN FLAG as true -INST_STEP_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x32] - -# core 0 thread 0 STEP WARN FLAG as false -INST_STEP_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x02] - -# core 0 thread 1 STEP WARN FLAG as false -INST_STEP_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x12] - -# core 0 thread 2 STEP WARN FLAG as false -INST_STEP_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x22] - -# core 0 thread 3 STEP WARN FLAG as false -INST_STEP_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x32] - -# Step All thread in Core0 with warn flag true -INST_STEP0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0xf2] - -# Step All thread in Core0 with warn flag false -INST_STEP0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0xf2] - -# SRESET Ins -# core 0 thread 0 SRESET WARN FLAG as true -INST_SRESET_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x03] - -# core 0 thread 1 SRESET WARN FLAG as true -INST_SRESET_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x13] - -# core 0 thread 2 SRESET WARN FLAG as true -INST_SRESET_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x23] - -# core 0 thread 3 SRESET with WARN FLAG as true -INST_SRESET_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0x33] - -# core 0 thread 0 SRESET WARN FLAG as false -INST_SRESET_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x03] - -# core 0 thread 1 SRESET WARN FLAG as false -INST_SRESET_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x13] - -# core 0 thread 2 SRESET WARN FLAG as false -INST_SRESET_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x23] - -# core 0 thread 3 SRESET WARN FLAG as false -INST_SRESET_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0x33] - -# Sreset All thread in Core0 with warn flag true -INST_SRESET0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0xf3] - -# Sreset All thread in Core0 with warn flag false -INST_SRESET0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,0,0x20,0xf3] - - -INST_EXPDATA = [0xc0,0xde,0xa7,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - -INST_EXPDATA_ERR = [0xc0,0xde,0xa7,0x01, - 0x00,0xFE,0x00,0x0A, - 0x00,0x00,0x00,0x03] - -STOP_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01, - 0x00,0xFE,0x00,0x0A, - 0xFF,0xDC,0x00,0x02, - 0x00,0xCE,0xBC,0xB2, - 0x00,0x00,0x00,0x05] - -START_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01, - 0x00,0xFE,0x00,0x0A, - 0xFF,0xDC,0x00,0x02, - 0x00,0x25,0x64,0xDB, - 0x00,0x00,0x00,0x05] - -STEP_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01, - 0x00,0xFE,0x00,0x0A, - 0xFF,0xDC,0x00,0x02, - 0x00,0x0D,0x06,0x8E, - 0x00,0x00,0x00,0x05] - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - #Try an invalid data case - testUtil.writeUsFifo( INST_INVALID_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_INVALID_EXPDATA_ERR ) - testUtil.readEot( ) - - # Control Instruction Message - Stop - testUtil.writeUsFifo( INST_STOP_0_0_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP_0_1_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP_0_2_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP_0_3_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP_0_0_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP_0_1_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP_0_2_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP_0_3_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - - #stop all thread in core0 - testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - - # Control Instruction Message - Start - testUtil.writeUsFifo( INST_START_0_0_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_START_0_1_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_START_0_2_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_START_0_3_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - - testUtil.writeUsFifo( INST_START_0_0_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_START_0_1_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_START_0_2_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_START_0_3_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - - #start all thread in core0 - testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - - # Control Instruction Message - Step - testUtil.writeUsFifo( INST_STEP_0_0_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP_0_1_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP_0_2_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP_0_3_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP_0_0_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP_0_1_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP_0_2_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP_0_3_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - - #step all thread in core0 - testUtil.writeUsFifo( INST_STEP0_ALL_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_STEP0_ALL_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) - testUtil.readEot( ) - - # Control Instruction Message - Sreset - testUtil.writeUsFifo( INST_SRESET_0_0_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET_0_1_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET_0_2_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET_0_3_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET_0_0_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET_0_1_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET_0_2_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET_0_3_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - - #step all thread in core0 - testUtil.writeUsFifo( INST_SRESET0_ALL_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( INST_SRESET0_ALL_TESTDATA_WITHOUT_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testCntlInstruction.xml b/sbe/test/testCntlInstruction.xml deleted file mode 100755 index 1231ac86..00000000 --- a/sbe/test/testCntlInstruction.xml +++ /dev/null @@ -1,7 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testCntlInstruction.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/sbe/test/testContinueMpipl.py b/sbe/test/testContinueMpipl.py deleted file mode 100755 index 37822d89..00000000 --- a/sbe/test/testContinueMpipl.py +++ /dev/null @@ -1,58 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testContinueMpipl.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -TESTDATA = [0,0,0,2, - 0,0,0xA9,0x02 ] - -EXPDATA = [0xc0,0xde,0xa9,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x3]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testContinueSbeBoot.py b/sbe/test/testContinueSbeBoot.py deleted file mode 100755 index e8ba019c..00000000 --- a/sbe/test/testContinueSbeBoot.py +++ /dev/null @@ -1,58 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testContinueSbeBoot.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -TESTDATA = [0,0,0,2, - 0,0,0xA1,0x02 ] - -EXPDATA = [0xc0,0xde,0xa1,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x3]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testEnterMpipl.py b/sbe/test/testEnterMpipl.py deleted file mode 100755 index 23686fe4..00000000 --- a/sbe/test/testEnterMpipl.py +++ /dev/null @@ -1,58 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testEnterMpipl.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -TESTDATA = [0,0,0,2, - 0,0,0xA9,0x01 ] - -EXPDATA = [0xc0,0xde,0xa9,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x3]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testExecutorMemory.py b/sbe/test/testExecutorMemory.py deleted file mode 100644 index 5bb4416a..00000000 --- a/sbe/test/testExecutorMemory.py +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/python -''' -############################################################# -# @file testExecutor.py -# @author: George Keishing <gkeishin@in.ibm.com> -# @brief Framework to test Host SBE interface on simics -# -# Created on March 29, 2016 -# ---------------------------------------------------- -# @version Developer Date Description -# ---------------------------------------------------- -# 1.0 gkeishin 29/03/16 Initial create -############################################################# -''' - -import testClass as testObj -import testRegistry as reg - -#------------------------------- -# This is a Test Expected Data -#------------------------------- -''' -This data are the values or strings that needs to be validated for the test. -''' -SBE_TEST_EXPECT_DEFAULT = "None" - -HOST_TEST_EXPECT_MAGIC = "00000000DEADBEEF" - -sbe_test_data = ( - #----------------------------------------------------------------------------------------------------- - # OP Reg Mem Length (bytes) size Test Expected Data Description - #----------------------------------------------------------------------------------------------------- - #["memRead", reg.MEM_ADDR, 0xA00000, 8, HOST_TEST_EXPECT_MAGIC, "Reading data from the address"], - ["memRead", reg.MEM_ADDR, 0x50, 8, HOST_TEST_EXPECT_MAGIC, "Reading data from the address"], - ) - -#------------------------- -# Main Function -#------------------------- -def main(): - - # Intialize the class obj instances - print "\n Initializing Registry instances ...." - regObj = testObj.registry() # Registry obj def for operation - - print "\n Execute SBE Test set [ Indirect Commands ] ...\n" - # Sim obj Target Test set - rc_test = regObj.ExecuteTestOp(testObj.simMemObj,sbe_test_data) - if rc_test != testObj.SUCCESS: - print " SBE Test data set .. [ FAILED ] .." - else: - print " SBE Test data set .. [ SUCCESS ] " - print "\n" - -if __name__=="__main__": - main() - diff --git a/sbe/test/testExecutorPSU.py b/sbe/test/testExecutorPSU.py deleted file mode 100644 index 52846ecb..00000000 --- a/sbe/test/testExecutorPSU.py +++ /dev/null @@ -1,117 +0,0 @@ -#!/usr/bin/python -''' -############################################################# -# @file testExecutor.py -# @author: George Keishing <gkeishin@in.ibm.com> -# @brief Framework to test Host SBE interface on simics -# -# Created on March 29, 2016 -# ---------------------------------------------------- -# @version Developer Date Description -# ---------------------------------------------------- -# 1.0 gkeishin 29/03/16 Initial create -############################################################# -''' - -import testPSUUtil -import testRegistry as reg - -#------------------------------- -# This is a Test Expected Data -#------------------------------- -''' -This data are the values or strings that needs to be validated for the test. -''' -SBE_TEST_EXPECT_DEFAULT = "None" - -HOST_TEST_EXPECT_DEFAULT = "None" -HOST_TEST_EXPECT_MBOX04 = "0000000000F0D101" - -''' -The test data is designed to accomodate as many as new entries a test needs -and can also increase the field in it to add new action associated with it. -''' -#--------------------- -# SBE side test data -#--------------------- -''' -Every test data entry itself represent an action associated with it's data. -The data is validated as it executes. - -The Test Expected Data if "None" signifies that this test entry is not to be -validated else it would validated against the expected value in the field. -On success returns macro SUCCESS else FAILURE - -Refer Documentation for the data used here directly. -''' - -sbe_test_data = ( - #----------------------------------------------------------------------------------------------------- - # OP Reg Value size Test Expected Data Description - #----------------------------------------------------------------------------------------------------- - ["write", reg.REG_MBOX0, "0000030100F0D101", 8, SBE_TEST_EXPECT_DEFAULT, "Writing to MBOX0 address"], - ["write", reg.REG_MBOX1, "0000000000001000", 8, SBE_TEST_EXPECT_DEFAULT, "Writing to MBOX1 address"], - ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, SBE_TEST_EXPECT_DEFAULT, "Update SBE Doorbell register to interrupt SBE"], - ) - -#--------------------- -# Host side test data -#--------------------- -''' -This Host data indicates that this will validate the SBE test set execution -if the overall test is a success or failure. - -It can have as many entries which are needed to be validated. -''' -host_test_data = ( - #---------------------------------------------------------------------------------------------------------------- - # OP Reg Value size Test Expected Data Description - #---------------------------------------------------------------------------------------------------------------- - ["read", reg.REG_MBOX4, "0000000000000000", 8, HOST_TEST_EXPECT_MBOX04, "Reading Host MBOX4 data to Validate"], - ) - -''' -User can define a function which does some task and returns SUCCESS or FAILURE. -one can simply call that function like any OP in the test data and still work. - -Define those function in testClassUtil.py context for this to work. -''' - -SAMPLE_TEST_EXPECT_FUNC = "None" -PARM_DATA = [1, 2, 3, 4] # sample 4 input paramters -sample_test_data = ( - #---------------------------------------------------------------------------------------------------------------- - # OP function Name Parameters NA Test Expected Data Description - #---------------------------------------------------------------------------------------------------------------- - ["func", "classUtilFuncSample", PARM_DATA, 0, SAMPLE_TEST_EXPECT_FUNC, "Load func and do task"], - ) - -#------------------------- -# Main Function -#------------------------- -def main(): - - # Intialize the class obj instances - print "\n Initializing Registry instances ...." - regObj = testPSUUtil.registry() # Registry obj def for operation - - print "\n Execute SBE Test set [ PSU ] ...\n" - # Sim obj Target Test set Raise Exception - rc_test = regObj.ExecuteTestOp(testPSUUtil.simSbeObj,sbe_test_data, True) - if rc_test != testPSUUtil.SUCCESS: - print " SBE Test data set .. [ Failed ] .." - else: - print " SBE Test data set .. [ OK ] " - print "\n Poll on Host side for INTR ...\n" - # Sim obj Target Test set Max timedout - rc_intr = regObj.pollingOn(testPSUUtil.simSbeObj,host_test_data,20) - if rc_intr == testPSUUtil.SUCCESS: - print " Interrupt Event Recieved .. Success !!" - else: - print " Interrupt not Recieved.. Exiting .." - - print "\n" - -if __name__=="__main__": - main() - diff --git a/sbe/test/testExecutorPutRing.py b/sbe/test/testExecutorPutRing.py deleted file mode 100644 index 59d4639e..00000000 --- a/sbe/test/testExecutorPutRing.py +++ /dev/null @@ -1,226 +0,0 @@ -#!/usr/bin/python -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testExecutorPutRing.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import testPSUUtil -import testRegistry as reg -import testUtil - -#------------------------------- -# This is a Test Expected Data -#------------------------------- -''' -This data are the values or strings that needs to be validated for the test. -''' -''' -#------------------------------------------------------------------------------------------------------------------------------ -# SBE side test data - Target - Pervasive(Core), Chiplet Id - 32, Ring ID - ec_func(224), mode - 0x0020(RING_MODE_HEADER_CHECK) -#------------------------------------------------------------------------------------------------------------------------------ -''' -sbe_test_data1 = ( - #----------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #----------------------------------------------------------------------------------------------------- - ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], - ["write", reg.REG_MBOX1, "0002002000E00020", 8, "None", "Writing to MBOX1 address"], - ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], - ) -''' -#------------------------------------------------------------------------------------------------------------------------------ -# SBE side test data - Target - Pervasive(Perv), Chiplet Id - 1, Ring ID - perv_fure(00), mode - 0x0020(RING_MODE_HEADER_CHECK) -#------------------------------------------------------------------------------------------------------------------------------ -''' -sbe_test_data2 = ( - #-------------------------------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #-------------------------------------------------------------------------------------------------------------------------- - ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], - ["write", reg.REG_MBOX1, "0002000100000020", 8, "None", "Writing to MBOX1 address"], - ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], - ) -''' -#--------------------- -# SBE side test data - Target - PROC CHIP, Chiplet Id - x, Ring ID - ob0_fure(118), mode - 0x0020(RING_MODE_HEADER_CHECK) -#--------------------- -''' -sbe_test_data3 = ( - #-------------------------------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #-------------------------------------------------------------------------------------------------------------------------- - ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], - ["write", reg.REG_MBOX1, "0000000600760020", 8, "None", "Writing to MBOX1 address"], - ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], - ) -''' -#------------------------------------------------------------------------------------------------------------------------------ -# SBE side test data - Target - EX, Chiplet Id - 32, Ring ID - ex_l3_fure(176), mode - 0x0020(RING_MODE_HEADER_CHECK) -#------------------------------------------------------------------------------------------------------------------------------ -''' -sbe_test_data4 = ( - #----------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #----------------------------------------------------------------------------------------------------- - ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], - ["write", reg.REG_MBOX1, "0001002000B00020", 8, "None", "Writing to MBOX1 address"], - ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], - ) -''' -#------------------------------------------------------------------------------------------------------------------------------ -# SBE side test data - Target - Invalid target 0x10, Chiplet Id - 32, Ring ID - ex_l3_refr_repr(248), mode - 0x0020(RING_MODE_HEADER_CHECK) -#------------------------------------------------------------------------------------------------------------------------------ -''' -sbe_test_data5 = ( - #----------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #----------------------------------------------------------------------------------------------------- - ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], - ["write", reg.REG_MBOX1, "0010002000F80020", 8, "None", "Writing to MBOX1 address"], - ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], - ) -''' -#--------------------- -# Host side test data - SUCCESS -#--------------------- -''' -host_test_data_success = ( - #---------------------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #---------------------------------------------------------------------------------------------------------------- - ["read", reg.REG_MBOX4, "0", 8, "0000000000F0D301", "Reading Host MBOX4 data to Validate"], - ) -''' -#--------------------- -# Host side test data - FAILURE -#--------------------- -''' -host_test_data_failure5 = ( - #---------------------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #---------------------------------------------------------------------------------------------------------------- - ["read", reg.REG_MBOX4, "0", 8, "0002000400F0D301", "Reading Host MBOX4 data to Validate"], - ) - -''' -#----------------------------------------------------------------------- -# Do not modify - Used to simulate interrupt on Ringing Doorbell on Host -#----------------------------------------------------------------------- -''' -host_polling_data = ( - #---------------------------------------------------------------------------------------------------------------- - # OP Reg ValueToWrite size Test Expected Data Description - #---------------------------------------------------------------------------------------------------------------- - ["read", reg.PSU_HOST_DOORBELL_REG_WO_OR, "0", 8, "8000000000000000", "Reading Host Doorbell for Interrupt"], - ) - -#------------------------- -# Main Function -#------------------------- -def main(): - # Run Simics initially - testUtil.runCycles( 10000000 ); - - # Intialize the class obj instances - regObj = testPSUUtil.registry() # Registry obj def for operation - - print "\n Execute SBE Test set1 [ Put Ring ] ...\n" - - ''' - Test Case 1 - ''' - # HOST->SBE data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data1 ) - - print "\n Poll on Host side for INTR ...\n" - #Poll on HOST DoorBell Register for interrupt - regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) - - #SBE->HOST data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) - - print "\n Execute SBE Test set2 [ Put Ring ] ...\n" - ''' - Test Case 2 - ''' - # HOST->SBE data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data2 ) - - print "\n Poll on Host side for INTR ...\n" - #Poll on HOST DoorBell Register for interrupt - regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) - - #SBE->HOST data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) - - print "\n Execute SBE Test set3 [ Put Ring ] ...\n" - ''' - Test Case 3 - ''' - # HOST->SBE data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data3 ) - - print "\n Poll on Host side for INTR ...\n" - #Poll on HOST DoorBell Register for interrupt - regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) - - #SBE->HOST data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) - - print "\n Execute SBE Test set4 [ Put Ring ] ...\n" - ''' - Test Case 4 - ''' - # HOST->SBE data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data4 ) - - print "\n Poll on Host side for INTR ...\n" - #Poll on HOST DoorBell Register for interrupt - regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) - - #SBE->HOST data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) - - print "\n Execute SBE Test set5 [ Put Ring ] ...\n" - ''' - Test Case 5 - ''' - # HOST->SBE data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data5 ) - - print "\n Poll on Host side for INTR ...\n" - #Poll on HOST DoorBell Register for interrupt - regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) - - #SBE->HOST data set execution - regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_failure5 ) - -if __name__ == "__main__": - main() - if err: - print ( "\nTest Suite completed with error(s)" ) - #sys.exit(1) - else: - print ( "\nTest Suite completed with no errors" ) - #sys.exit(0); - - diff --git a/sbe/test/testExecutorPutRing.xml b/sbe/test/testExecutorPutRing.xml deleted file mode 100755 index 9aef4cf9..00000000 --- a/sbe/test/testExecutorPutRing.xml +++ /dev/null @@ -1,31 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: sbe/test/testExecutorPutRing.xml $ --> -<!-- --> -<!-- OpenPOWER sbe Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<?xml version="1.0" encoding="UTF-8"?> - - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testExecutorPutRing.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/sbe/test/testFifoReset.py b/sbe/test/testFifoReset.py deleted file mode 100644 index 9660df2e..00000000 --- a/sbe/test/testFifoReset.py +++ /dev/null @@ -1,57 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest") -import testUtil - -err = False - -# Test data that only contains the command header -TESTDATA = [0, 0, 0, 3, - 0, 0, 0xA1, 0x01] - -# Complete test data -TESTDATA_FULL = [0, 0, 0, 3, - 0, 0, 0xA1, 0x01, - 0, 0x02, 0x00, 0x01] - -# Get capabilities command. This will ensure the DS FIFO gets full -TESTDATA_2 = [0, 0, 0, 2, - 0, 0, 0xA8, 0x02] - -def main(): - try: - testUtil.runCycles(10000000) - # Send a partial chip-op - testUtil.writeUsFifo(TESTDATA) - testUtil.resetFifo() - # Make sure both the upstream and downstrem FIFOs are clear after the reset - testUtil.waitTillUsFifoEmpty() - testUtil.waitTillDsFifoEmpty() - # Now send a complete chip-op on the upstream FIFO - testUtil.writeUsFifo(TESTDATA_FULL) - testUtil.writeEot() - testUtil.resetFifo() - # Make sure both the upstream and downstrem FIFOs are clear after the reset - testUtil.waitTillUsFifoEmpty() - testUtil.waitTillDsFifoEmpty() - # Now send a get capabilities chip-op, so that in response, the DS FIFO - # gets full before we do a reset - testUtil.writeUsFifo(TESTDATA_2) - testUtil.writeEot() - testUtil.resetFifo() - # Make sure both the upstream and downstrem FIFOs are clear after the reset - testUtil.waitTillUsFifoEmpty() - testUtil.waitTillDsFifoEmpty() - except: - print("\nTest completed with error(s), Raise error") - raise - print("\nTest completed with no errors") - -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testFifoReset.xml b/sbe/test/testFifoReset.xml deleted file mode 100644 index 672d2c5a..00000000 --- a/sbe/test/testFifoReset.xml +++ /dev/null @@ -1,36 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: sbe/test/testFifoReset.xml $ --> -<!-- --> -<!-- OpenPOWER sbe Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<?xml version="1.0" encoding="UTF-8"?> - - <!-- SBE FIFO reset Test case --> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testFifoReset.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <!-- An istep chip-op should succeed post the FIFO reset --> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalidFenced.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> diff --git a/sbe/test/testGeneric.xml b/sbe/test/testGeneric.xml deleted file mode 100755 index 5073121c..00000000 --- a/sbe/test/testGeneric.xml +++ /dev/null @@ -1,7 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - - <!-- SBE Get Capabilities Test case --> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetCapabilities.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> diff --git a/sbe/test/testGetCapabilities.py b/sbe/test/testGetCapabilities.py deleted file mode 100755 index a9287558..00000000 --- a/sbe/test/testGetCapabilities.py +++ /dev/null @@ -1,83 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testGetCapabilities.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -TESTDATA = [0,0,0,2, - 0,0,0xA8,0x02 ] - -EXPDATA1 = [0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0, - 0xa1,0x0,0x0,0x01, # istep - 0x0,0x0,0x0,0x0, - 0xa2,0x0,0x0,0x0f, #getscom/putscom/modifyscom/putscomundermask - 0x0,0x0,0x0,0x0, - 0xa3,0x0,0x0,0x1, #getring - 0x00,0x0,0x0,0x0]; - -EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc - 0x0,0x0,0x0,0x0, - 0xa5,0x0,0x0,0x03, #GetReg/PutReg - 0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0, - 0xa7,0x0,0x0,0x1, # control Instruction - 0x00,0x0,0x0,0x0]; - -EXPDATA3 = [0xa8,0x0,0x0,0x02, #getcapability - 0x0,0x0,0x0,0x0, - 0xc0,0xde,0xa8,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x3]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - # Ignore first two enteries ( major number, minor number - # and fw version) as they will keep on changing - testUtil.readDsEntry( 2 ) - testUtil.readDsFifo( EXPDATA1 ) - testUtil.readDsFifo( EXPDATA2 ) - testUtil.readDsFifo( EXPDATA3 ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testGetMem.py b/sbe/test/testGetMem.py deleted file mode 100644 index dac6b747..00000000 --- a/sbe/test/testGetMem.py +++ /dev/null @@ -1,51 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 1 - -GETMEM_TESTDATA = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0x02, - 0,0,0,0, - 0x08,0x00,0x00,0x00, - 0x00,0x00,0x00,0x80] # length of data - -GETMEM_EXPDATA = [0x00,0x00,0x00,0x80, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - # GetMem test - testUtil.writeUsFifo( GETMEM_TESTDATA ) - testUtil.writeEot( ) - # GetMem chipOp would send the read data first, - # thus, would attempt to read the expected length of data first - loop = 1 - while ( loop <= LOOP_COUNT ): - testUtil.readDsEntry ( 32 ) ## 32 entries ~ 128B PBA granule - loop += 1 - testUtil.readDsFifo( GETMEM_EXPDATA ) - testUtil.readEot( ) - - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testGetMem_expdata.py b/sbe/test/testGetMem_expdata.py deleted file mode 100644 index 78304c5a..00000000 --- a/sbe/test/testGetMem_expdata.py +++ /dev/null @@ -1,60 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 4 - -GETMEM_TESTDATA = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0x02, - 0,0,0,0, - 0x08,0x00,0x00,0x00, - 0x00,0x00,0x00,0x80] # length of data - -GETMEM_EXP_RESPHDR = [0x00,0x00,0x00,0x80, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - -GETMEM_EXP_RESPDATA = [0xAB,0xCD,0xEF,0x01, - 0xAB,0xCD,0xEF,0x02, - 0xAB,0xCD,0xEF,0x03, - 0xAB,0xCD,0xEF,0x04, - 0xAB,0xCD,0xEF,0x05, - 0xAB,0xCD,0xEF,0x06, - 0xAB,0xCD,0xEF,0x07, - 0xAB,0xCD,0xEF,0x08] - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - # GetMem test - testUtil.writeUsFifo( GETMEM_TESTDATA ) - testUtil.writeEot( ) - # GetMem chipOp would send the read data first, - # thus, would attempt to read the expected length of data first - loop = 1 - while ( loop <= LOOP_COUNT ): - testUtil.readDsFifo ( GETMEM_EXP_RESPDATA ) - loop += 1 - testUtil.readDsFifo( GETMEM_EXP_RESPHDR ) - testUtil.readEot( ) - - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testGetRing.py b/sbe/test/testGetRing.py deleted file mode 100644 index 4137108d..00000000 --- a/sbe/test/testGetRing.py +++ /dev/null @@ -1,96 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testGetRing.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 1 - -#aligned Data -GETRING_TESTDATA = [0,0,0,0x6, - 0,0,0xA3,0x01, - 0xa,0xa,0xa,0xa, # address - 0,0,0,0x40, # length of data - 0x00,0x00,0x00,0x01] - -GETRING_EXPDATA = [0,0,0,0, #data - 0,0,0,0, #data - 0,0,0,0x40, # length of data - 0xc0,0xde,0xa3,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -#Un-aligned Data -GETRING_TESTDATA1 = [0,0,0,0x6, - 0,0,0xA3,0x01, - 0xa,0xa,0xa,0xa, # address - 0,0,0,0x45, # length of data - 0x00,0x00,0x00,0x01] - -GETRING_EXPDATA1 = [0,0,0,0, #data - 0,0,0,0, #data - 0,0,0,0, #data - 0,0,0,0, #data - 0,0,0,0x45, # length of data - 0xc0,0xde,0xa3,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - # GetRing test - Aligned Data - testUtil.writeUsFifo( GETRING_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETRING_EXPDATA ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) - - # GetRing test - un-aligned Data - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( GETRING_TESTDATA1 ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETRING_EXPDATA1 ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testGetRing.xml b/sbe/test/testGetRing.xml deleted file mode 100755 index e3f240c1..00000000 --- a/sbe/test/testGetRing.xml +++ /dev/null @@ -1,30 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: sbe/test/testGetRing.xml $ --> -<!-- --> -<!-- OpenPOWER sbe Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> - - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetRing.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/sbe/test/testIstep.xml b/sbe/test/testIstep.xml deleted file mode 100644 index 0e371e79..00000000 --- a/sbe/test/testIstep.xml +++ /dev/null @@ -1,333 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: sbe/test/testIstep.xml $ --> -<!-- --> -<!-- OpenPOWER sbe Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<?xml version="1.0" encoding="UTF-8"?> - - <!-- Invalid Istep Test case --> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalid.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <!-- Positive Istep Test case --> - <testcase> - <simcmd>sbe-istep 2 2</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 3</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 4</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 5</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 6</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 7</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 8</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 9</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 10</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 11</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 12</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 13</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 14</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 15</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 16</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 2 17</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 1</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 2</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 3</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 4</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 5</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 6</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 7</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 8</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 9</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 10</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 11</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 12</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 13</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 14</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 15</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 16</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 17</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 18</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 19</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 20</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 21</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 3 22</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 1</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 2</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 3</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 4</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 5</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 6</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 7</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 8</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 9</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 10</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 11</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 12</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 13</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 14</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 15</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 16</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 17</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 18</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 19</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 20</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 21</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 22</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 23</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 24</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 25</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 26</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 27</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 28</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 29</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 30</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 31</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 32</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 33</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 4 34</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 5 1</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>sbe-istep 5 2</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <!-- Invalid Istep Test case --> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalidFenced.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> diff --git a/sbe/test/testIstepAuto.py b/sbe/test/testIstepAuto.py deleted file mode 100755 index 6bff0f99..00000000 --- a/sbe/test/testIstepAuto.py +++ /dev/null @@ -1,31 +0,0 @@ -import sys -from sim_commands import * -import imp -err = False -testUtil = imp.load_source("testUtil", os.environ['SBE_TOOLS_PATH'] + "/testUtil.py") -EXPDATA = [0xc0,0xde,0xa1,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; -# MAIN Test Run Starts Here... -#------------------------------------------------- -def sbe_istep_func( major, minor ): - try: - TESTDATA = [0,0,0,3, - 0,0,0xA1,0x01, - 0,major,0,minor ] - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) - except: - print ("\nTest completed with error(s). Raise error") - # TODO via RTC 142706 - # Currently simics commands created using hooks always return - # success. Need to check from simics command a way to return - # Calling non existant command to return failure - run_command("Command Failed"); - raise - print ("\nTest completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testIstepInvalid.py b/sbe/test/testIstepInvalid.py deleted file mode 100755 index 2d158a3a..00000000 --- a/sbe/test/testIstepInvalid.py +++ /dev/null @@ -1,58 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testIstepInvalid.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -TESTDATA = [0,0,0,3, - 0,0,0xA1,0x01, - 0,0x02,0x00,0x1] - -EXPDATA = [0xc0,0xde,0xa1,0x01, - 0x00,0x02,0x00,0x0A, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testIstepInvalidFenced.py b/sbe/test/testIstepInvalidFenced.py deleted file mode 100755 index 1d067139..00000000 --- a/sbe/test/testIstepInvalidFenced.py +++ /dev/null @@ -1,58 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testIstepInvalidFenced.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -TESTDATA = [0,0,0,3, - 0,0,0xA1,0x01, - 0,0x02,0x00,0x1] - -EXPDATA = [0xc0,0xde,0xa1,0x01, - 0x00,0x00,0x00,0x08, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testIstepSuccess.py b/sbe/test/testIstepSuccess.py deleted file mode 100755 index 8c42a504..00000000 --- a/sbe/test/testIstepSuccess.py +++ /dev/null @@ -1,34 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -TESTDATA = [0,0,0,3, - 0,0,0xA1,0x01, - 0,0x02,0x00,0x2] - -EXPDATA = [0xc0,0xde,0xa1,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( EXPDATA ) - testUtil.readEot( ) -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testModifyScom.py b/sbe/test/testModifyScom.py deleted file mode 100755 index d7e504b2..00000000 --- a/sbe/test/testModifyScom.py +++ /dev/null @@ -1,74 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - - -PUTSCOM_TESTDATA = [0,0,0,6, - 0,0,0xA2,0x02, - 0,0,0x0,0x00, - 0,0x05,0x00,0x3E, #scratch reg 7 (32-bit) - 0x00,0xff,0x00,0xff, - 0x00,0x00,0x00,0x00 ] - -PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - -MODIFYSCOM_TESTDATA = [0,0,0,7, - 0,0,0xA2,0x03, - 0,0,0x0,0x01, - 0,0,0x0,0x00, - 0,0x05,0x00,0x3E, - 0xde,0x00,0xff,0x00, - 0x00,0x00,0x00,0x00] - -MODIFYSCOM_EXPDATA = [0xc0,0xde,0xa2,0x03, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -GETSCOM4MODIFYSCOM_TESTDATA = [0,0,0,4, - 0,0,0xA2,0x01, - 0,0,0x0,0x00, - 0,0x05,0x0,0x3E] - -GETSCOM4MODIFYSCOM_EXPDATA = [0xde,0xff,0xff,0xff, - 0x00,0x00,0x00,0x00, - 0xc0,0xde,0xa2,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - testUtil.writeUsFifo( PUTSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTSCOM_EXPDATA ) - testUtil.readEot( ) - - testUtil.writeUsFifo( MODIFYSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( MODIFYSCOM_EXPDATA ) - testUtil.readEot( ) - - testUtil.writeUsFifo( GETSCOM4MODIFYSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETSCOM4MODIFYSCOM_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPSUUserUtil.py b/sbe/test/testPSUUserUtil.py deleted file mode 100644 index d2126e56..00000000 --- a/sbe/test/testPSUUserUtil.py +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/python -''' -############################################################# -# @file testClassUtil.py -# @author: George Keishing <gkeishin@in.ibm.com> -# @brief Framework utility fucntions for Host SBE -# interface on simics -# -# Created on March 29, 2016 -# ---------------------------------------------------- -# @version Developer Date Description -# ---------------------------------------------------- -# 1.0 gkeishin 29/03/16 Initial create -############################################################# -''' - -import testPSUUtil - -''' -Add your personalize functions here for execution but ensure it returns -either SUCCESS or FAILURE as an end result for generalization purpose. -''' - -########################################################################## -# Function : classUtilFuncSample -# -# @param i_paramArray : user supplied input array parameters -# -# @brief Function to do a task and returns SUCCCES or FAILURE -# -########################################################################## -def classUtilFuncSample(i_paramArray): - for input in i_paramArray: - print " classUtilFuncSample : parm: ",input - return testPSUUtil.SUCCESS diff --git a/sbe/test/testPSUUtil.py b/sbe/test/testPSUUtil.py deleted file mode 100644 index 88fd6a29..00000000 --- a/sbe/test/testPSUUtil.py +++ /dev/null @@ -1,377 +0,0 @@ -#!/usr/bin/python -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testPSUUtil.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -''' -############################################################# -# @file testClass.py -# @author: George Keishing <gkeishin@in.ibm.com> -# @brief Framework class Host SBE interface on simics -# -# Created on March 29, 2016 -# ---------------------------------------------------- -# @version Developer Date Description -# ---------------------------------------------------- -# 1.0 gkeishin 29/03/16 Initial create -############################################################# -''' - -#------------------------- -# Imports packages -#------------------------- -import time -import conf -import testUtil -import testPSUUserUtil -from sim_commands import * - -#------------------------- -# Macros constants -#------------------------- -SUCCESS = 1 -FAILURE = 0 - -#------------------------- -# SIM OBJs -#------------------------- -''' -This is a simulator obj mapped. Refer simics folks if new objects are needed. -''' -simSbeObj = conf.p9Proc0.sbe.mibo_space -simHostObj = conf.p9Proc0.p9_mem_map.host_xscom_device_mm -simMemObj = conf.system_cmp0.phys_mem - -''' -This is a base MBOX registry address from 0..7 -''' -# Register MBOX 0..3 SBE side address in order -REGDATA_SBE = [ - 0x00680500, - 0x00680510, - 0x00680520, - 0x00680530 - ] - -# Register MBOX 4..7 host side address in order -REGDATA_HOST = [ - 0x00680540, - 0x00680550, - 0x00680560, - 0x00680570 - ] - -# Supporting Class objects -''' -Base function members definitions for set,get,read, write and others needed. -Keep it simple and modular so that it can be extended as a base class. -''' -#------------------ -# Registry class -#------------------ -class registry(object): - #------------------------------ - # Set the reg data - #------------------------------ - def setRegData(self, addr, value, size): - self.regAddr = addr - self.regVal = value - self.regSize = size - - #------------------------------ - # Read Reg value set or updated - #------------------------------ - def getRegData(self): - print " Addr : ",hex(self.regAddr) - print " Value : ",self.regVal - print " Size : ",self.regSize - - #------------------------------ - # Write to a Registry - #------------------------------ - def writeToReg(self, objType): - address = self.regAddr - value = self.stringToByte(self.regVal) - size = self.regSize - print " WData : 0x%s -> Byte Data %s"% (self.regVal,value) - print " Addr :", hex(address) - print " Size : %s Bytes"% size - - self.__write(objType,address,value,size) - return - - #------------------------------ - # Write to Registry 0..3 using - # test data directly. - #------------------------------ - def writeTestData(self, data): - simObj = SIM_get_interface(simSbeObj, "memory_space") - entryCount = len(data) - size = 8 - for i in range (entryCount): - value = stringToByte(data[i]) - print "\n Writting ", hex(REGDATA_SBE[i]) - print " %x %x %x %x %x %x %x %x" % (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]) - simObj.write(None, REGDATA_SBE[regIndex], - (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]), - size) - return - - #------------------------------ - # Write using SIM object - # 4/8 Bytes data - #------------------------------ - def __write(self, Targetobj, address, value, size): - simObj = SIM_get_interface(Targetobj, "memory_space") - if int(size) == 4: - simObj.write(None, address, - (value[0],value[1],value[2],value[3]), - size) - elif int(size) == 8: - simObj.write(None, address, - (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]), - size) - print " SIM obj: Write %s bytes [ OK ] " % size - return - - #--------------------------- - # Read from a Registry - #--------------------------- - def readFromReg(self, objType): - address = self.regAddr - size = self.regSize - value = self.regVal - if int(value) !=0: - print " RData :", value - print " Addr :", hex(address) - print " Size : %s Bytes"% size - - value = self.__read(objType,address,size) - return value - - #--------------------------- - # Read from a memomry - # Max Sim interface can read 8 - # byte data at a given time - #--------------------------- - def readFromMemory(self, objType, magicNum): - # Start addr + 8 bytes - address = self.regAddr - size = self.regSize # Max it can read is 8 Bytes - value = self.regVal # Max lentgth it should read - - MaxAddr = address + value # This is the addres range it could read - print " MaxAddr Range:",hex(MaxAddr) - OffsetAddr = address - print " OffsetAddr:",hex(OffsetAddr) - - print " Memory Entries to be read : %d" % (value/8) - print " Match Magic Number : ", magicNum - - while ( OffsetAddr <= MaxAddr): - sim_data = self.__read(objType,OffsetAddr,size) - print " ", hex(OffsetAddr),self.joinListDataToHex(sim_data).upper() - OffsetAddr += 8 - - if self.validateTestMemOp(sim_data,magicNum) == True: - print " Test validated .. [ OK ]" - return SUCCESS - - return FAILURE # Failed validation - - #------------------------------ - # Read using SIM Object - #------------------------------ - def __read(self, Targetobj, address, size): - simObj = SIM_get_interface(Targetobj, "memory_space") - value = simObj.read(None, address, size, 0x0) - #print " SIM obj: Read %s bytes [ OK ] " % size - return value - - #-------------------------------- - # Prepare the byte data from the - # string and return the list set - #------------------------------- - def stringToByte(self,value): - ''' - The sim interface doesnt take the values as it is .. - it takes as byte arrays - Ex: "0000030100F0D101" - '\x00\x00\x03\x01\x00\xf0\xd1\x01' - [0, 0, 3, 1, 0, 240, 209, 1] - ''' - # Convert it to a hex string - hex_val= value.decode("hex") - # Prepare the conversion to a list of byte values - value=map(ord, hex_val) - return value - - #--------------------------------------- - # Joing the list set data to hex data - # Reverse of the stringToByte logic - #--------------------------------------- - def joinListDataToHex(self, data): - # simics> (0, 0, 3, 1, 0, 240, 209, 1) - # Join this data into hex string 0xf0d101 - bit_shift=56 - hex_val = 0x0 - for val in data: - hex_val |= int(val) << bit_shift - bit_shift -=8 - return hex(hex_val) - - #---------------------------------------------------- - # Execute the read or write operation in loop as per - # Test data set pre-defined - #---------------------------------------------------- - def ExecuteTestOp(self, testOp, test_bucket, raiseException=True): - ''' - 3 prong steps : set data, read/write data, validate - ''' - #-------------------------------------------- - for l_params in test_bucket: - #-------------------------------------------- - print " Desc : %s " % l_params[5] - print " Op : %s " % l_params[0] - if "func" == l_params[0]: - print " Func : %s " % l_params[1] - if l_params[4] != "None": - print " Expect : %s " % l_params[4] - if "func" == l_params[0]: - print " Function Params :",l_params[2] - else: - # addr, value, size - self.setRegData(l_params[1],l_params[2],l_params[3]) - - # --------------------------------------------- - # Check the Op and perform the action - # read/write - # --------------------------------------------- - if "read" == l_params[0]: - sim_data = self.readFromReg(testOp) - print " ++++++++++++++++++++++++++++++++++++++++++" - print " simics Data : ", sim_data - print " simics Hex : ", self.joinListDataToHex(sim_data).upper() - - # Validate the test data - ''' - This field in the test entry holds the data - that needs validation against sim data. - ''' - if l_params[4] != "None": - if self.validateTestOp(sim_data,l_params[4]) == True: - print " Test validated .. [ OK ]" - else: - if(raiseException == True): - raise Exception('Data mistmach'); - return FAILURE # Failed validation - else: - print " ++++++++++++++++++++++++++++++++++++++++++" - elif "write" == l_params[0]: - self.writeToReg(testOp) - elif "memRead" == l_params[0]: - # (Sim obj) (Validate) - return self.readFromMemory(testOp, l_params[4]) - elif "func" == l_params[0]: - # Func name Params - rc = self.loadFunc( l_params[1], l_params[2] ) - return rc - else: - print "\n Invalid Test Data" - if(raiseException == True): - raise Exception('Invalid Test Data'); - return FAILURE # Unknown entry op - - print "\n" - return SUCCESS - - #---------------------------------------------------- - # Validate simulator data against test data - #---------------------------------------------------- - def validateTestOp(self, sim_data, test_data): - print " Test Expects : 0x%s " % test_data - print " Expect bytes : ", self.stringToByte(test_data) - if self.compareList(self.stringToByte(test_data), sim_data, "None") == True: - print " Test ... [ OK ] " - print " ++++++++++++++++++++++++++++++++++++++++++" - return SUCCESS - else: - print " Test Failed... !!!" - print " ++++++++++++++++++++++++++++++++++++++++++" - return FAILURE - - #---------------------------------------------------- - # Validate simulator data against test data - #---------------------------------------------------- - def validateTestMemOp(self, sim_data, test_data): - if self.compareList(self.stringToByte(test_data), sim_data,"memRead") == True: - return SUCCESS - return # Return nothing to check next memory entry - - - #---------------------------------------------------- - # Compare the result vs expected list data - # byte by byte - #---------------------------------------------------- - def compareList(self, expList, resList, opType): - for i in range(0,8): - if int(expList[i]) == int(resList[i]): - #print " %s : %s " % (expList[i],resList[i]) - continue - else: - if opType != "memRead": - print " Error \t %s : %s [ Mismatch ]" % (expList[i],resList[i]) - return False # mismatch - return # Return nothing for Next Mem byte read - return True - - #---------------------------------------------------- - # A basic loop poll mechanism - #---------------------------------------------------- - def pollingOn(self, simObj, test_data, retries=20): - for l_param in test_data: - while True: - print "\n***** Polling On result - retrials left [%d] " % retries - print "\n" - testUtil.runCycles( 1000000); - test_d = (l_param,) - rc = self.ExecuteTestOp(simObj, test_d, False) - if rc == SUCCESS: - print ('Polling Successful for - ' + l_param[5]) - break - elif retries <= 0: - print " Retrials exhausted... Exiting polling" - raise Exception('Polling Failed for - ' + l_param[5]); - break - else: - retries = retries - 1 - return FAILURE - - #---------------------------------------------------- - # Load the function and execute - #---------------------------------------------------- - def loadFunc(self, func_name, i_pArray ): - rc = testPSUUserUtil.__getattribute__(func_name)(i_pArray) - return rc # Either success or failure from func - - diff --git a/sbe/test/testPutGetInScom.py b/sbe/test/testPutGetInScom.py deleted file mode 100755 index 9f39e8d1..00000000 --- a/sbe/test/testPutGetInScom.py +++ /dev/null @@ -1,83 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testPutGetInScom.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -# @TODO via RTC : 141905 -# Modify the test sequence in such a way that -# the test does not leave the Register value altered. - -# Indirect scom form 0 test case -PUTSCOM_TESTDATA = [0,0,0,6, - 0,0,0xA2,0x02, - 0x80,0x0,0x0,0x83, - 0x0D,0x01,0x0C,0x3F, - 0xde,0xca,0xff,0xee, - 0x00,0x00,0x12,0x34 ] - -PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -GETSCOM_TESTDATA = [0,0,0,4, - 0,0,0xA2,0x01, - 0x80,0x0,0x0,0x83, - 0x0D,0x01,0x0C,0x3F] - -GETSCOM_EXPDATA = [0x00,0x00,0x00,0x00, - 0x00,0x00,0x12,0x34, # Only last 16 bits will be returned - 0xc0,0xde,0xa2,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTSCOM_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( GETSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETSCOM_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPutGetMem.xml b/sbe/test/testPutGetMem.xml deleted file mode 100644 index d8939eb2..00000000 --- a/sbe/test/testPutGetMem.xml +++ /dev/null @@ -1,11 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutMem.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetMem_expdata.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/sbe/test/testPutGetRegFpr.py b/sbe/test/testPutGetRegFpr.py deleted file mode 100755 index 63cf4186..00000000 --- a/sbe/test/testPutGetRegFpr.py +++ /dev/null @@ -1,58 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -PUTREG_TESTDATA = [0,0,0,9, - 0,0,0xA5,0x02, - 0x00,0x20,0x02,0x02, # two fpr registers - 0,0,0x0,0x01, - 0,0,0x0,0x0, - 0,0,0x0,0x1, - 0,0,0x0,0x02, - 0,0,0x0,0x0, - 0,0,0x0,0x2 ] - -PUTREG_EXPDATA = [0xc0,0xde,0xa5,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -GETREG_TESTDATA = [0,0,0,5, - 0,0,0xA5,0x01, - 0x00,0x20,0x02,0x02, #two fpr registers - 0,0,0x0,0x01, - 0,0,0x0,0x02 ] - -GETREG_EXPDATA = [0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x01, - 0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x02, - 0xc0,0xde,0xa5,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTREG_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTREG_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( GETREG_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETREG_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPutGetRegGpr.py b/sbe/test/testPutGetRegGpr.py deleted file mode 100755 index ce5891e7..00000000 --- a/sbe/test/testPutGetRegGpr.py +++ /dev/null @@ -1,58 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -PUTREG_TESTDATA = [0,0,0,9, - 0,0,0xA5,0x02, - 0x00,0x20,0x00,0x02, # two gpr registers - 0,0,0x0,0x07, - 0,0,0x0,0x0, - 0,0,0x0,0x1, - 0,0,0x0,0x08, - 0,0,0x0,0x0, - 0,0,0x0,0x2 ] - -PUTREG_EXPDATA = [0xc0,0xde,0xa5,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -GETREG_TESTDATA = [0,0,0,5, - 0,0,0xA5,0x01, - 0x00,0x20,0x00,0x02, # two gpr registers - 0,0,0x0,0x07, - 0,0,0x0,0x08 ] - -GETREG_EXPDATA = [0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x01, - 0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x02, - 0xc0,0xde,0xa5,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTREG_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTREG_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( GETREG_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETREG_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPutGetRegSpr.py b/sbe/test/testPutGetRegSpr.py deleted file mode 100755 index 82f7c8d2..00000000 --- a/sbe/test/testPutGetRegSpr.py +++ /dev/null @@ -1,58 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False - -PUTREG_TESTDATA = [0,0,0,9, - 0,0,0xA5,0x02, - 0x00,0x20,0x01,0x02, # two spr registers - 0,0,0x0,0x08, - 0,0,0x0,0x0, - 0,0,0x0,0x1, - 0,0,0x0,0x09, - 0,0,0x0,0x0, - 0,0,0x0,0x2 ] - -PUTREG_EXPDATA = [0xc0,0xde,0xa5,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -GETREG_TESTDATA = [0,0,0,5, - 0,0,0xA5,0x01, - 0x00,0x20,0x01,0x02, # two spr registers - 0,0,0x0,0x08, - 0,0,0x0,0x09 ] - -GETREG_EXPDATA = [0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x01, - 0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x02, - 0xc0,0xde,0xa5,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTREG_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTREG_EXPDATA ) - testUtil.readEot( ) - testUtil.writeUsFifo( GETREG_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETREG_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPutGetScom.py b/sbe/test/testPutGetScom.py deleted file mode 100755 index bf6185ce..00000000 --- a/sbe/test/testPutGetScom.py +++ /dev/null @@ -1,119 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testPutGetScom.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -# @TODO via RTC : 141905 -# Modify the test sequence in such a way that -# the test does not leave the Register value altered. - -PUTSCOM_TESTDATA = [0,0,0,6, - 0,0,0xA2,0x02, - 0,0,0x0,0x00, - 0,0x05,0x00,0x3E, #scratch reg 7 (32-bit) - 0xde,0xca,0xff,0xee, - 0x00,0x00,0x00,0x00 ] - -PUTSCOM_TESTDATA_INVALID = [0,0,0,6, - 0,0,0xA2,0x02, - 0,0,0x0,0x00, - # TODO via RTC 152952: This address is invalid for - # Nimbus but not for Cumulus - 0x0a,0x00,0x00,0x00, - 0xde,0xca,0xff,0xee, - 0x00,0x00,0x00,0x00 ] - -PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -PUTSCOM_EXPDATA_INVALID = [0xc0,0xde,0xa2,0x02, - 0x0,0xfe,0x0,0x11, - 0x00,0x0,0x0,0x04, - 0x00,0x0,0x0,0x04]; - -GETSCOM_TESTDATA = [0,0,0,4, - 0,0,0xA2,0x01, - 0,0,0x0,0x00, - 0,0x05,0x0,0x3E] - -GETSCOM_TESTDATA_INVALID = [0,0,0,4, - 0,0,0xA2,0x01, - 0,0,0x0,0x00, - # TODO via RTC: 152952: This address is invalid for - # Nimbus but not for Cumulus - 0x0a,0x0,0x0,0x0] - -GETSCOM_EXPDATA = [0xde,0xca,0xff,0xee, - 0x00,0x00,0x00,0x00, - 0xc0,0xde,0xa2,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -GETSCOM_EXPDATA_INVALID = [0xc0,0xde,0xa2,0x01, - 0x0,0xfe,0x0,0x11, - 0x00,0x0,0x0,0x04, - 0x00,0x0,0x0,0x04]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - print ("\nStarting putscom test") - testUtil.writeUsFifo( PUTSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTSCOM_EXPDATA ) - testUtil.readEot( ) - print ("\nStarting invalid putscom test") - testUtil.writeUsFifo( PUTSCOM_TESTDATA_INVALID ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTSCOM_EXPDATA_INVALID ) - testUtil.readEot( ) - print ("\nStarting getscom test") - testUtil.writeUsFifo( GETSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETSCOM_EXPDATA ) - testUtil.readEot( ) - print ("\nStarting invalid getscom test") - testUtil.writeUsFifo( GETSCOM_TESTDATA_INVALID ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETSCOM_EXPDATA_INVALID ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPutMem.py b/sbe/test/testPutMem.py deleted file mode 100644 index 8ba710bb..00000000 --- a/sbe/test/testPutMem.py +++ /dev/null @@ -1,60 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 4 - -PUTMEM_TEST_HDR = [0,0,0,0x86, - 0,0,0xA4,0x02, - 0,0,0x0,0x02, - 0,0,0,0, - 0x08,0x00,0x00,0x00, - 0x00,0x00,0x00,0x80] - -PUTMEM_TEST_DATA = [0xAB,0xCD,0xEF,0x01, - 0xAB,0xCD,0xEF,0x02, - 0xAB,0xCD,0xEF,0x03, - 0xAB,0xCD,0xEF,0x04, - 0xAB,0xCD,0xEF,0x05, - 0xAB,0xCD,0xEF,0x06, - 0xAB,0xCD,0xEF,0x07, - 0xAB,0xCD,0xEF,0x08] - -PUTMEM_EXPDATA = [0x00,0x00,0x00,0x80, - 0xc0,0xde,0xa4,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - testUtil.writeUsFifo( PUTMEM_TEST_HDR ) - - loop = 1 - while (loop <= LOOP_COUNT): - #testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTMEM_TEST_DATA ) - loop += 1 - testUtil.writeEot( ) - - #testUtil.runCycles( 10000000 ) - testUtil.readDsFifo( PUTMEM_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPutMem_fail.py b/sbe/test/testPutMem_fail.py deleted file mode 100644 index 8e6c4cc4..00000000 --- a/sbe/test/testPutMem_fail.py +++ /dev/null @@ -1,61 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 4 - -PUTMEM_TEST_HDR = [0,0,0x00,0x86, - 0,0,0xA4,0x02, - 0,0,0x0,0x02, - 0,0,0,0, - 0x08,0x00,0x00,0x04, # Un-aligned PBA Address - 0x00,0x00,0x00,0x80] - -PUTMEM_TEST_DATA = [0xAB,0xCD,0xEF,0x01, - 0xAB,0xCD,0xEF,0x02, - 0xAB,0xCD,0xEF,0x03, - 0xAB,0xCD,0xEF,0x04, - 0xAB,0xCD,0xEF,0x05, - 0xAB,0xCD,0xEF,0x06, - 0xAB,0xCD,0xEF,0x07, - 0xAB,0xCD,0xEF,0x08] - -PUTMEM_EXPDATA = [0x00,0x00,0x00,0x00, - 0xc0,0xde,0xa4,0x02, - 0x00,0xfe,0x00,0x0a, - 0xff,0xdc,0x00,0x03, - 0x00,0x00,0x00,0x00, - 0x00,0xf8,0x82,0x19, - 0x00,0x00,0x00,0x06] - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - testUtil.writeUsFifo( PUTMEM_TEST_HDR ) - - loop = 1 - while (loop <= LOOP_COUNT): - testUtil.writeUsFifo( PUTMEM_TEST_DATA ) - loop += 1 - testUtil.writeEot( ) - - testUtil.readDsFifo( PUTMEM_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testPutScomUnderMask.py b/sbe/test/testPutScomUnderMask.py deleted file mode 100755 index 8136c68a..00000000 --- a/sbe/test/testPutScomUnderMask.py +++ /dev/null @@ -1,75 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -PUTSCOM_TESTDATA = [0,0,0,6, - 0,0,0xA2,0x02, - 0,0,0x0,0x00, - 0,0x05,0x00,0x3E, #scratch reg 7 (32-bit) - 0xff,0xff,0xff,0xff, - 0x00,0x00,0x00,0x00 ] - -PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - -PUTSCOMUMASK_TESTDATA = [0,0,0,8, - 0,0,0xA2,0x04, - 0,0,0x0,0x00, - 0,0x05,0x00,0x3E, - 0xde,0xca,0xff,0xee, - 0x00,0x00,0x00,0x00, - 0xff,0x00,0xff,0x00, - 0x00,0x00,0x00,0x00] - - -PUTSCOMUMASK_EXPDATA = [0xc0,0xde,0xa2,0x04, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -GETSCOMUMASK_TESTDATA = [0,0,0,4, - 0,0,0xA2,0x01, - 0,0,0x0,0x00, - 0,0x05,0x0,0x3E] - -GETSCOMUMASK_EXPDATA = [0xde, 0xff, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x00, - 0xc0,0xde,0xa2,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - testUtil.writeUsFifo( PUTSCOM_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTSCOM_EXPDATA ) - testUtil.readEot( ) - - testUtil.writeUsFifo( PUTSCOMUMASK_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( PUTSCOMUMASK_EXPDATA ) - testUtil.readEot( ) - - testUtil.writeUsFifo( GETSCOMUMASK_TESTDATA ) - testUtil.writeEot( ) - testUtil.readDsFifo( GETSCOMUMASK_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testRegAccess.xml b/sbe/test/testRegAccess.xml deleted file mode 100755 index 3a236345..00000000 --- a/sbe/test/testRegAccess.xml +++ /dev/null @@ -1,23 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testStopInstruction.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegGpr.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegFpr.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegSpr.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testStartInstruction.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/sbe/test/testRegistry.py b/sbe/test/testRegistry.py deleted file mode 100644 index b6119583..00000000 --- a/sbe/test/testRegistry.py +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/python -''' -############################################################# -# @file testClass.py -# @author: George Keishing <gkeishin@in.ibm.com> -# @brief Framework class Host SBE interface on simics -# -# Created on March 29, 2016 -# ---------------------------------------------------- -# @version Developer Date Description -# ---------------------------------------------------- -# 1.0 gkeishin 29/03/16 Initial create -############################################################# -''' - -# Test OP keywords for reference -''' - - read : Read from a Registry - - write : write to a Registry - - memRead : Read from a memory address block -''' - -# Registry address for direct usage -REG_MBOX0 = 0x00680500 -REG_MBOX1 = 0x00680510 -REG_MBOX2 = 0x00680520 -REG_MBOX3 = 0x00680530 -REG_MBOX4 = 0x00680540 -REG_MBOX5 = 0x00680550 -REG_MBOX6 = 0x00680560 -REG_MBOX7 = 0x00680570 - -# PSU doorbell regs -PSU_SBE_DOORBELL_REG = 0x00680600 -PSU_SBE_DOORBELL_REG_WO_AND = 0x00680610 -PSU_SBE_DOORBELL_REG_WO_OR = 0x00680620 - -PSU_HOST_DOORBELL_REG = 0x00680630 -PSU_HOST_DOORBELL_REG_WO_AND = 0x00680640 -PSU_HOST_DOORBELL_REG_WO_OR = 0x00680650 - - -# Memory space address -''' -simics> system_cmp0.phys_mem.map - Base Object Fn Offset Length -------------------------------------------------------------------------- -0x0000008000000 p9Proc0.l3_cache_ram 0 0x0 0xa00000 - width 8192 bytes -0x6030000000000 p9Proc0.lpcm 0 0x6030000000000 0xffffffff - width 4 bytes -0x603fc00000000 proc_p9chip0.mc_freeze 0 0x0 0x400000000 - target -> proc_p9chip0.xscom_memspc, width 8 bytes - -''' -MEM_ADDR = 0x0000008000000 diff --git a/sbe/test/testSbeDump.py b/sbe/test/testSbeDump.py deleted file mode 100644 index e8add7cc..00000000 --- a/sbe/test/testSbeDump.py +++ /dev/null @@ -1,111 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testSbeDump.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest") -import testUtil -err = False -#from testWrite import * - -TESTDATA = [0, 0, 0, 3, - 0, 0, 0xA1, 0x01, - 0, 0x02, 0x00, 0x2] - -EXPDATA = [0xc0, 0xde, 0xa1, 0x01] - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main(): - testUtil.runCycles(10000000) - testUtil.writeUsFifo(TESTDATA) - testUtil.writeEot() - testUtil.readDsFifo(EXPDATA) - #flush out primary and secondary status - data = testUtil.readDsEntryReturnVal() - - #flush hwp ffdc - data = testUtil.readDsEntryReturnVal() - data = testUtil.readDsEntryReturnVal() - - #start processing sbe ffdc - data = testUtil.readDsEntryReturnVal() - magicBytes = ((data[0] << 8) | data[1]) - if (magicBytes == 0xFFDC) : - print ("\nMagic Bytes Match") - else : - raise Exception('data mistmach') - packLen = ((data[2] << 8) | data[3]) - print ("\nFFDC package length = " + str(packLen)) - - data = testUtil.readDsEntryReturnVal() - fapiRc = ((data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]) - print ("\nFAPI rc = " + str(hex(fapiRc))) - - data = testUtil.readDsEntryReturnVal() - primaryStatus = ((data[0] << 8) | data[1]) - secondaryStatus = ((data[2] << 8) | data[3]) - print ("\nPrimary Status " + str(hex(primaryStatus)) + " Secondary Status "\ - + str(hex(secondaryStatus))) - - data = testUtil.readDsEntryReturnVal() - header = ((data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]) - print ("\nHeader = " + str(hex(header))) - - for i in range(0, (bin(header).count("1"))): - #read user data id - data = testUtil.readDsEntryReturnVal() - id = (data[0] << 8) | data[1] - print "User data Id ["+str(hex(id))+"]" - len = (data[2] << 8) | data[3] - #if it is trace field SBE_FFDC_TRACE_DUMP - fileName = "" - if(id == 0x0002): - fileName = "trace.bin" - print ("\nlength of trace dump " + str(len)) - #if it is trace field SBE_FFDC_ATTR_DUMP - elif(id == 0x0001): - fileName = "attr.bin" - print ("\nlength of attr dump " + str(len)) - myBin = open(fileName, 'wb') - print ("\nwriting "+fileName) - loopCount = (len ) / 4 - for j in range(0, loopCount): - data = testUtil.readDsEntryReturnVal() - myBin.write(bytearray(data)) - print("write to a file Done") - myBin.close() - #flush out distance - data = testUtil.readDsEntryReturnVal() -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testScom.xml b/sbe/test/testScom.xml deleted file mode 100755 index f7ced6fc..00000000 --- a/sbe/test/testScom.xml +++ /dev/null @@ -1,43 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: sbe/test/testScom.xml $ --> -<!-- --> -<!-- OpenPOWER sbe Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<?xml version="1.0" encoding="UTF-8"?> - - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutScomUnderMask.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testModifyScom.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetInScom.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/sbe/test/testSram.py b/sbe/test/testSram.py deleted file mode 100644 index 2ffa35ee..00000000 --- a/sbe/test/testSram.py +++ /dev/null @@ -1,106 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 1 - -PUTSRAM_OCC_CNTLDATA = [0,0,0,0x20, - 0,0,0xa4,0x04, #magic - 0,0,0,0x01, - 0xe7,0xf0,0x00,0x00, #addr - 0,0,0x01,0x00] # length - -PUTSRAM_OCC_TESTDATA = [0xab,0xcd,0xef,0x12, - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9, - 0xab,0xcd,0xef,0x12, - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9] - -PUTSRAM_OCC_EXP_CNTLDATA = [0,0,0x01,0x00, - 0xc0,0xde,0xa4,0x04, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - -GETSRAM_OCC_CNTLDATA = [0,0,0,0x5, - 0,0,0xa4,0x03, - 0,0,0,0x01, - 0xe7,0xf0,0x00,0x00, #address - 0x00,0x00,0x01,0x00] # length of data - -GETSRAM_OCC_EXP_TESTDATA = [0xab,0xcd,0xef,0x12, #data - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9, - 0xab,0xcd,0xef,0x12, - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9] - -GETSRAM_OCC_EXP_CNTLDATA = [0x00,0x00,0x01,0x00, # length - 0xc0,0xde,0xa4,0x03, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - # Put Occ Sram test - Linear - Can be tested over Normal - # Debug mode - testUtil.writeUsFifo( PUTSRAM_OCC_CNTLDATA ) - # Write 32 bytes of data 8 times => 32*8 = 256 = 0x100 - i_cnt = 0 - while i_cnt < 8: - testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA ) - i_cnt = i_cnt+1 - - testUtil.writeEot( ) - - # Read the expected data for put sram - testUtil.readDsFifo( PUTSRAM_OCC_EXP_CNTLDATA ) - testUtil.readEot( ) - - # Get Sram Linear - testUtil.writeUsFifo( GETSRAM_OCC_CNTLDATA ) - testUtil.writeEot( ) - - # Read the Expected Data for get Sram - i_cnt = 0 - while i_cnt < 8: - testUtil.readDsFifo( GETSRAM_OCC_EXP_TESTDATA ) - i_cnt = i_cnt+1 - - testUtil.readDsFifo( GETSRAM_OCC_EXP_CNTLDATA ) - testUtil.readEot( ) - - # Put Occ Sram test - Circular - Can be enabled once we get - # valid address range to read the circular data - #testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA_1 ) - #testUtil.writeEot( ) - #testUtil.readDsFifo( PUTSRAM_OCC_EXPDATA_1 ) - #testUtil.readEot( ) - #testUtil.writeUsFifo( GETSRAM_OCC_TESTDATA_1 ) - #testUtil.writeEot( ) - #testUtil.readDsFifo( GETSRAM_OCC_EXPDATA_1 ) - #testUtil.readEot( ) - - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testSram.xml b/sbe/test/testSram.xml deleted file mode 100755 index b44ddb6d..00000000 --- a/sbe/test/testSram.xml +++ /dev/null @@ -1,8 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> - - <testcase> - <!-- TODO RTC - 150091 - Add the Occ sram test case --> - <!--<simcmd>run-python-file targets/p9_nimbus/sbeTest/testSram.py</simcmd>--> - <!--<exitonerror>yes</exitonerror>--> - </testcase> - diff --git a/sbe/test/testStartInstruction.py b/sbe/test/testStartInstruction.py deleted file mode 100644 index c2f2c5da..00000000 --- a/sbe/test/testStartInstruction.py +++ /dev/null @@ -1,41 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 1 - - -# Start All thread in Core0 with warn flag true -INST_START0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0xf0] - -INST_EXPDATA = [0xc0,0xde,0xa7,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - #stop all thread in core0 - testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testStopInstruction.py b/sbe/test/testStopInstruction.py deleted file mode 100644 index 414c35b4..00000000 --- a/sbe/test/testStopInstruction.py +++ /dev/null @@ -1,41 +0,0 @@ -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 1 - - -# Stop All thread in Core0 with warn flag true -INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, - 0,0,0xa7,0x01, - 0,1,0x20,0xf1] - -INST_EXPDATA = [0xc0,0xde,0xa7,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): - testUtil.runCycles( 10000000 ) - - #stop all thread in core0 - testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG ) - testUtil.writeEot( ) - testUtil.readDsFifo( INST_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - diff --git a/sbe/test/testUtil.py b/sbe/test/testUtil.py deleted file mode 100644 index b3575625..00000000 --- a/sbe/test/testUtil.py +++ /dev/null @@ -1,171 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: sbe/test/testUtil.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import time -import conf -from sim_commands import * - -#err = False -lbus = conf.p9Proc0.proc_lbus_map -def writeUsFifo( data): - """Main test Loop""" - loopCount = len(data)/4; - for i in range (loopCount): - idx = i * 4; - writeEntry(lbus, 0x2400, (data[idx], data[idx+1], data[idx+2], data[idx+3]) ) - -def readDsFifo(data): - """Main test Loop""" - loopCount = len(data)/4; - for i in range (loopCount): - idx = i * 4; - checkEqual(readEntry(lbus, 0x2440, 4), (data[idx], data[idx+1], data[idx+2], data[idx+3])) - -def writeEot(): - write(lbus, 0x2408, (0, 0, 0, 1) ) - -def write(obj, address, value ): - """ Write to memory space """ - iface = SIM_get_interface(obj, "memory_space") - iface.write(None, address, value, 0x0) - -def readEot(): - """ Read from memory space """ - status = read(lbus, 0x2444, 4) - checkEqual( (status[3] & 0x80), 0x80 ); - read(lbus, 0x2440, 4) - -def resetFifo(): - write(lbus, 0x240C, (0, 0, 0, 1)) - return - -def readUsFifoStatus(): - status = read(lbus, 0x2404, 4) - return status - -def readDsFifoStatus(): - status = read(lbus, 0x2444, 4) - return status - -def waitTillFifoEmpty(func): - count = 0 - loop = True - while(loop is True): - status = func() - if(status[1] == 0x10): - loop = False - break - else: - count = count + 1 - runCycles(200000) - if(count > 10): - raise Exception('Timed out waiting for FIFO to get flushed') - - -def waitTillUsFifoEmpty(): - try: - waitTillFifoEmpty(readUsFifoStatus) - except: - raise Exception('US FIFO did not get empty') - - -def waitTillDsFifoEmpty(): - try: - waitTillFifoEmpty(readDsFifoStatus) - except: - raise Exception('DS FIFO did not get empty') - - -# This function will only read the entry but will not compare it -# with anything. This can be used to flush out enteries. -def readDsEntry(entryCount): - for i in range (entryCount): - readEntry(lbus, 0x2440, 4) - -def writeEntry(obj, address, value ): - - loop = 1; - count = 0; - while( loop ): - status = read(lbus, 0x2404, 4) # Address 0x2404: Upstream Fifo Status - - if( status[2] & 0x02): - count = count + 1 - runCycles(200000) - # This will cause test to fail - if(count > 10): - raise Exception('Timeout. FIFO FULL'); - else: - # write entry - write(obj, address, value) - loop = 0 - - return value -def readDsEntryReturnVal(): - data = readEntry(lbus, 0x2440, 4) - runCycles(200000) - return data -def readEntry(obj, address, size): - - """ Read from memory space """ - loop = 1; - count = 0; - value = (0,0,0,0) - while( loop ): - status = read(lbus, 0x2444, 4) # Address 0x2444: Downstream Fifo Status - - if( status[1] & 0x0F): - # read entry - value = read(lbus, address, size) - loop = 0 - else: - count = count + 1 - runCycles(200000) - # This will cause test to fail - if(count > 10): - raise Exception('Timeout. Empty FIFO'); - - return value - -def read(obj, address, size): - """ Read from memory space """ - iface = SIM_get_interface(obj, "memory_space") - value = iface.read(None, address, size, 0x0) - return value - -def runCycles( cycles ): - if (not SIM_simics_is_running()): - syscmd = "run-cycles %d"%(cycles) - ( rc, out ) = quiet_run_command( syscmd, output_modes.regular ) - if ( rc ): - print "simics ERROR running %s: %d "%( syscmd, rc ) - -def checkEqual( data, expdata ): - """ Throw exception if data is not equal """ - if( cmp(data, expdata )): - print "Eqality check failed" - print "Data:", data - print "Expected Data", expdata - raise Exception('data mistmach'); - |
