diff options
Diffstat (limited to 'pk/gpe')
| -rw-r--r-- | pk/gpe/Makefile | 50 | ||||
| -rw-r--r-- | pk/gpe/gpe.h | 35 | ||||
| -rw-r--r-- | pk/gpe/gpe_common.h | 65 | ||||
| -rw-r--r-- | pk/gpe/gpe_init.c | 122 | ||||
| -rw-r--r-- | pk/gpe/gpe_irq.h | 247 | ||||
| -rw-r--r-- | pk/gpe/gpe_irq_init.c | 106 | ||||
| -rw-r--r-- | pk/gpe/gpe_scom_handler.S | 98 | ||||
| -rw-r--r-- | pk/gpe/gpe_timebase.h | 40 | ||||
| -rw-r--r-- | pk/gpe/pk_port.h | 16 | ||||
| -rw-r--r-- | pk/gpe/pkgpefiles.mk | 33 |
10 files changed, 0 insertions, 812 deletions
diff --git a/pk/gpe/Makefile b/pk/gpe/Makefile deleted file mode 100644 index 324107dc..00000000 --- a/pk/gpe/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# This Makefile compiles all of the PK code required for the GPE port -# of PK. See the "pk.mk" file in this directory. - -#all generated files from this makefile will end up in obj/$(IMAGE_NAME)/pk -export SUB_OBJDIR = /pk - -include img_defs.mk -include pkgpefiles.mk - -ifeq "$(PK_TIMER_SUPPORT)" "1" -GPE_OBJECTS += ${GPE-TIMER-C-SOURCES:.c=.o} ${GPE-TIMER-S-SOURCES:.S=.o} -endif - -ifeq "$(PK_THREAD_SUPPORT)" "1" -GPE_OBJECTS += ${GPE-THREAD-C-SOURCES:.c=.o} ${GPE-THREAD-S-SOURCES:.S=.o} -endif - -ifeq "$(GPE_ASYNC_SUPPORT)" "1" -GPE_OBJECTS += ${GPE-ASYNC-C-SOURCES:.c=.o} ${GPE-ASYNC-S-SOURCES:.S=.o} -endif - -OBJS := $(addprefix $(OBJDIR)/, $(GPE_OBJECTS)) - -libpk.a: kernel ppe42 trace gpe - $(AR) crs $(OBJDIR)/libpk.a $(OBJDIR)/*.o - -.PHONY: clean gpe kernel ppe42 trace -gpe: $(OBJS) - -trace: - $(MAKE) -I $(IMAGE_SRCDIR) -C ../trace - -kernel: - $(MAKE) -I $(IMAGE_SRCDIR) -C ../kernel - -ppe42: - $(MAKE) -I $(IMAGE_SRCDIR) -C ../ppe42 - - -$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) - -$(OBJDIR): - mkdir -p $(OBJDIR) - -clean: - rm -fr $(OBJDIR) - -ifneq ($(MAKECMDGOALS),clean) -include $(OBJS:.o=.d) -endif diff --git a/pk/gpe/gpe.h b/pk/gpe/gpe.h deleted file mode 100644 index 3b8e634e..00000000 --- a/pk/gpe/gpe.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __GPE_H__ -#define __GPE_H__ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2014 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp.h -/// \brief The GPE environment for PK. - -// This is a 'circular' reference in PK, but included here to simplify PGAS -// programming. - -#ifndef HWMACRO_GPE -#define HWMACRO_GPE -#include "ppe42.h" -#endif - -#include "ocb_register_addresses.h" -#include "gpe_common.h" - -/* -#include "pcbs_register_addresses.h" -#include "pcbs_firmware_registers.h" - -#include "tod_register_addresses.h" -#include "tod_firmware_registers.h" - -#include "plb_arbiter_register_addresses.h" -#include "plb_arbiter_firmware_registers.h" - -*/ - -#endif /* __GPE_H__ */ diff --git a/pk/gpe/gpe_common.h b/pk/gpe/gpe_common.h deleted file mode 100644 index 043a4802..00000000 --- a/pk/gpe/gpe_common.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __GPE_COMMON_H__ -#define __GPE_COMMON_H__ - -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2014 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file gpe_common.h -/// \brief Common header for GPE -/// -/// This header is maintained as part of the PK port for GPE, but needs to be -/// physically present in the PMX area to allow dropping PMX code as a whole -/// to other teams. - -// -*- WARNING: This file is maintained as part of PK. Do not edit in -*- -// -*- the PMX area as your edits will be lost. -*- - -#ifndef __ASSEMBLER__ -#include <stdint.h> -#endif - -#include "occhw_common.h" - -/// Each GPE instance has it's own interrupt status register these macros -/// are added for convenience in accessing the correct register -#define GPE_GISR0(instance_id) (OCB_G0ISR0 + (instance_id * 8)) -#define GPE_GISR1(instance_id) (OCB_G0ISR1 + (instance_id * 8)) - -#ifdef __ASSEMBLER__ -/// This macro contains GPE specific code for determining what IRQ caused the -/// external exception handler to be invoked by the PPE - -/// Check for interrupts pending in status register 0 while the IRQ is -/// computed. The IRQ is expected to be stored in r4. If no IRQ is -/// pending then load the phantom irq # (EXTERNAL_IRQS). -/// -/// r1, r2, r3, and r13 must not be modified. All other registers may be used. -/// - .macro hwmacro_get_ext_irq - - _lwzi %r5, %r5, GPE_GISR0(APPCFG_OCC_INSTANCE_ID) - cntlzw %r4, %r5 - cmpwible %r4, 31, call_external_irq_handler #branch if irq is lt or eq to 31 - - ## No IRQ pending in interrupt set 0. Try set 1. - ## Note: irq # will be 64 (EXTERNAL_IRQS) if no bits were set in either register - - _lwzi %r6, %r6, GPE_GISR1(APPCFG_OCC_INSTANCE_ID) - cntlzw %r4, %r6 - addi %r4, %r4, 32 - - .endm - - -/// Redirect the .hwmacro_irq_cfg_bitmaps macro to call our macro that is common for both -/// GPE's and the 405 inside the OCC complex. This is called from the ppe42_exceptions.S -/// file. - .macro .hwmacro_irq_cfg_bitmaps - .occhw_irq_cfg_bitmaps - .endm -#endif /* __ASSEMBLER__ */ - -#endif /* __GPE_COMMON_H__ */ diff --git a/pk/gpe/gpe_init.c b/pk/gpe/gpe_init.c deleted file mode 100644 index b32c875b..00000000 --- a/pk/gpe/gpe_init.c +++ /dev/null @@ -1,122 +0,0 @@ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2014 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file gpe_init.c -/// \brief PK initialization for GPE -/// -/// The entry points in this routine are used during initialization. This -/// code space can be deallocated and reassigned after application -/// initialization if required. - -#include "pk.h" -#include "ocb_register_addresses.h" - -/// GPE environment initial setup. -/// -/// This is setup common to all GPE HW Macro applications. This setup takes place -/// during boot, before main() is called. - -void -__hwmacro_setup(void) -{ - uint64_t oirrA; - uint64_t oirrB; - uint64_t oirrC; - uint64_t owned_actual; - uint64_t reverse_polarity; - - //verify that this code is running on the correct GPE instance (one time check) - if((mfspr(SPRN_PIR) & PIR_PPE_INSTANCE_MASK) != APPCFG_OCC_INSTANCE_ID) - { - //APPCFG_OCC_INSTANCE_ID does not match actual instance ID! - PK_PANIC(OCCHW_INSTANCE_MISMATCH); - } - -#if (APPCFG_OCC_INSTANCE_ID == OCCHW_IRQ_ROUTE_OWNER) - //If this instance is the owner of the interrupt routting registers - //then write the routing registers for all OCC interrupts. - //This instance must be the first instance to run within the OCC - //This will be done while all external interrupts are masked. - PKTRACE("Initializing External Interrupt Routing Registers"); - out32(OCB_OIMR0_OR, 0xffffffff); - out32(OCB_OIMR1_OR, 0xffffffff); - out32(OCB_OIRR0A, (uint32_t)(g_ext_irqs_routeA >> 32)); - out32(OCB_OIRR1A, (uint32_t)g_ext_irqs_routeA); - out32(OCB_OIRR0B, (uint32_t)(g_ext_irqs_routeB >> 32)); - out32(OCB_OIRR1B, (uint32_t)g_ext_irqs_routeB); - out32(OCB_OIRR0C, (uint32_t)(g_ext_irqs_routeC >> 32)); - out32(OCB_OIRR1C, (uint32_t)g_ext_irqs_routeC); -#endif - - //Determine from the routing registers which irqs are owned by this instance - //NOTE: If a bit is not set in the routeA register, it is not owned by a GPE - - oirrA = ((uint64_t)in32(OCB_OIRR0A)) << 32; - oirrA |= in32(OCB_OIRR1A); - oirrB = ((uint64_t)in32(OCB_OIRR0B)) << 32; - oirrB |= in32(OCB_OIRR1B); - oirrC = ((uint64_t)in32(OCB_OIRR0C)) << 32; - oirrC |= in32(OCB_OIRR1C); - - //All interrupts routed to a GPE will have a bit set in routeA - owned_actual = oirrA; - - //wittle it down by bits in the routeB register -#if APPCFG_OCC_INSTANCE_ID & 0x2 - owned_actual &= oirrB; -#else - owned_actual &= ~oirrB; -#endif - - //wittle it down further by bits in the routeC register -#if APPCFG_OCC_INSTANCE_ID & 0x1 - owned_actual &= oirrC; -#else - owned_actual &= ~oirrC; -#endif - - //Panic if we don't own the irqs we were expecting - //NOTE: we don't panic if we are given more IRQ's than expected - if((owned_actual & g_ext_irqs_owned) != g_ext_irqs_owned) - { - //IRQ's were not routed to us correctly. - PK_PANIC(OCC_IRQ_ROUTING_ERROR); - } - - //Mask all external interrupts owned by this instance - //(even the ones given to us that we weren't expecting) - out32(OCB_OIMR0_OR, (uint32_t)(owned_actual >> 32)); - out32(OCB_OIMR1_OR, (uint32_t)owned_actual); - - //Set the interrupt type for all interrupts owned by this instance - out32(OCB_OITR0_CLR, (uint32_t)(g_ext_irqs_owned >> 32)); - out32(OCB_OITR1_CLR, (uint32_t)g_ext_irqs_owned); - out32(OCB_OITR0_OR, (uint32_t)(g_ext_irqs_type >> 32)); - out32(OCB_OITR1_OR, (uint32_t)g_ext_irqs_type); - - //Set the interrupt polarity for all interrupts owned by this instance - out32(OCB_OIEPR0_CLR, (uint32_t)(g_ext_irqs_owned >> 32)); - out32(OCB_OIEPR1_CLR, (uint32_t)g_ext_irqs_owned); - out32(OCB_OIEPR0_OR, (uint32_t)(g_ext_irqs_polarity >> 32)); - out32(OCB_OIEPR1_OR, (uint32_t)g_ext_irqs_polarity); - - //clear the status of all external interrupts owned by this instance - out32(OCB_OISR0_CLR, ((uint32_t)(g_ext_irqs_owned >> 32))); - out32(OCB_OISR1_CLR, ((uint32_t)g_ext_irqs_owned)); - - //set the status for interrupts that have reverse polarity - reverse_polarity = ~g_ext_irqs_polarity & g_ext_irqs_owned; - out32(OCB_OISR0_OR, ((uint32_t)(reverse_polarity >> 32))); - out32(OCB_OISR1_OR, ((uint32_t)reverse_polarity)); - - //Unmask the interrupts owned by this instance that are to be enabled by default - out32(OCB_OIMR0_CLR, (uint32_t)(g_ext_irqs_enable >> 32)); - out32(OCB_OIMR1_CLR, (uint32_t)g_ext_irqs_enable); - - //Wait for the last out32 operation to complete - sync(); - -} diff --git a/pk/gpe/gpe_irq.h b/pk/gpe/gpe_irq.h deleted file mode 100644 index 3b018916..00000000 --- a/pk/gpe/gpe_irq.h +++ /dev/null @@ -1,247 +0,0 @@ -#ifndef __GPE_IRQ_H__ -#define __GPE_IRQ_H__ - -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2014 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file occhw_irq.h -/// \brief GPE-OCCHW Interrupt handling for PK -/// -/// The OCCHW interrupt controller supports a maximum of 64 interrupts, split -/// into 2 x 32-bit non-cascaded interrupt controllers with simple OR -/// combining of the interrupt signals. -/// -/// The OCB interrupt controller allows interrupt status to be set directly by -/// software, as well as providing a mode that causes an enabled pending -/// interrupt to trigger an Unconditional Debug Event. The OCB interrupt -/// controller contains a 'mask' register, unlike other 405 interrupt -/// controllers that have an 'enable' register. The OCCHW mask and status -/// registers also have atomic CLR/OR function so that it is never necessary -/// to enter a critical section to enable/disable/clear interrupts and -/// interrupt status. - -#include "occhw_common.h" -#include "ocb_register_addresses.h" -#include "ppe42.h" - -#ifndef __ASSEMBLER__ - -/// Enable an interrupt by clearing the mask bit. - -UNLESS__PPE42_IRQ_CORE_C__(extern) -inline void -pk_irq_enable(PkIrqId irq) -{ - out32(OCCHW_OIMR_CLR(irq), OCCHW_IRQ_MASK32(irq)); -} - - -/// Disable an interrupt by setting the mask bit. - -UNLESS__PPE42_IRQ_CORE_C__(extern) -inline void -pk_irq_disable(PkIrqId irq) -{ - out32(OCCHW_OIMR_OR(irq), OCCHW_IRQ_MASK32(irq)); -} - - -/// Clear interrupt status with an CLR mask. Only meaningful for -/// edge-triggered interrupts. - -UNLESS__PPE42_IRQ_CORE_C__(extern) -inline void -pk_irq_status_clear(PkIrqId irq) -{ - out32(OCCHW_OISR_CLR(irq), OCCHW_IRQ_MASK32(irq)); -} - - -/// Get IRQ status as a 0 or non-0 integer - -UNLESS__PPE42_IRQ_CORE_C__(extern) -inline int -pk_irq_status_get(PkIrqId irq) -{ - return (in32(OCCHW_OISR(irq)) & OCCHW_IRQ_MASK32(irq)) != 0; -} - - -/// Set or clear interrupt status explicitly. - -UNLESS__PPE42_IRQ_CORE_C__(extern) -inline void -pk_irq_status_set(PkIrqId irq, int value) -{ - if (value) { - out32(OCCHW_OISR_OR(irq), OCCHW_IRQ_MASK32(irq)); - } else { - out32(OCCHW_OISR_CLR(irq), OCCHW_IRQ_MASK32(irq)); - } -} - - -#endif /* __ASSEMBLER__ */ - -/// \page occhw_irq_macros OCCHW IRQ API Assembler Macros -/// -/// These macros encapsulate the PK API for the OCCHW interrupt -/// controller. These macros require 2 scratch registers in addition to the \c -/// irq parameter register passed into the handler from PK interrupt -/// dispatch. These macros also modify CR0. -/// -/// \arg \c rirq A register that holds the \c irq parameter passed to -/// the handler from PK interrupt dispatch. This register is not -/// modified. -/// \arg \c rmask A scratch register - At the end of macro execution this -/// register contains the 32-bit mask form of the irq. -/// -/// \arg \c raddr A scratch register - At the end of macro execution this -/// register holds the address of the interrupt -/// controller facility that implements the action. -/// -/// \arg \c imm An immediate (0/non-0) value for certain macros. -/// -/// Forms: -/// -/// \b _pk_irq_enable \a rirq, \a rmask, \a raddr - Enable an \c irq. \n -/// \b _pk_irq_disable \a rirq, \a rmask, \a raddr - Disable an \c irq. \n -/// \b _pk_irq_status_clear \a rirq, \a rmask, \a raddr - Clear \c irq -/// interrupt status. \n -/// \b _pk_irq_status_set \a rirq, \a rmask, \a raddr, \a imm - Set \c irq status -/// with an immediate (0/non-0) value. \n -/// -/// \todo Once the logic design is locked down, revisit whether these macros -/// (and C-code versions) can be implemented without branching. This could be -/// done in theory by converting bit 26 into the byte offset between addresses -/// in interupt controller 0 and interrupt controller 1 - assuming the -/// distances are all the same power-of-two. -/// -/// \cond - -// IRQ numbers are in the range 0..63. IRQs are converted to the 32-bit -// residue used to compute the mask. CR0 is set as a test of IRQ > 32 - the -// register \c raddr is used as scratch for these computations. Hopefully the -// local labels 888 and 999 are unique enough. - -// Register names must be compared as strings - e.g., %r0 is not -// a symbol, it is converted to "0" by the assembler. - -#ifdef __ASSEMBLER__ - - .macro .two_unique, ra, rb - .ifnc \ra, \rb - .exitm - .endif - .error "Both register arguments must be unique" - .endm - - - .macro .three_unique, ra, rb, rc - .ifnc \ra, \rb - .ifnc \rb, \rc - .ifnc \ra, \rc - .exitm - .endif - .endif - .endif - .error "All three register arguments must be unique" - .endm - - - .macro _occhw_irq_or_mask, rirq:req, rmask:req - .two_unique \rirq, \rmask - lis \rmask, 0x8000 - srw \rmask, \rmask, \rirq - .endm - - .macro _occhw_irq_clr_mask, rirq:req, rmask:req - .two_unique \rirq, \rmask - _occhw_irq_or_mask \rirq, \rmask - .endm - - - .macro _pk_irq_enable, rirq:req, rmask:req, raddr:req - .three_unique \rirq, \rmask, \raddr - - andi. \raddr, \rirq, 0x20 - clrlwi \raddr, \rirq, 27 - _occhw_irq_clr_mask \raddr, \rmask - bne- 888f - _stwi \rmask, \raddr, OCB_OIMR0_CLR - b 999f -888: - _stwi \rmask, \raddr, OCB_OIMR1_CLR -999: - eieio - .endm - - - .macro _pk_irq_disable, rirq:req, rmask:req, raddr:req - .three_unique \rirq, \rmask, \raddr - - andi. \raddr, \rirq, 0x20 - clrlwi \raddr, \rirq, 27 - _occhw_irq_or_mask \raddr, \rmask - bne- 888f - _stwi \rmask, \raddr, OCB_OIMR0_OR - b 999f -888: - _stwi \rmask, \raddr, OCB_OIMR1_OR -999: - eieio - .endm - - - .macro _pk_irq_status_clear, rirq:req, rmask:req, raddr:req - .three_unique \rirq, \rmask, \raddr - - andi. \raddr, \rirq, 0x20 - clrlwi \raddr, \rirq, 27 - _occhw_irq_clr_mask \raddr, \rmask - bne- 888f - _stwi \rmask, \raddr, OCB_OISR0_CLR - b 999f -888: - _stwi \rmask, \raddr, OCB_OISR1_CLR -999: - eieio - .endm - - - .macro _pk_irq_status_set, rirq:req, rmask:req, raddr:req, imm:req - .three_unique \rirq, \rmask, \raddr - - andi. \raddr, \rirq, 0x20 - clrlwi \raddr, \rirq, 27 - - .if \imm - _occhw_irq_or_mask \raddr, \rmask - bne- 888f - _stwi \rmask, \raddr, OCB_OISR0_OR - b 999f -888: - _stwi \rmask, \raddr, OCB_OISR1_OR - - .else - - _occhw_irq_clr_mask \raddr, \rmask - bne- 888f - _stwi \rmask, \raddr, OCB_OISR0_CLR - b 999f -888: - _stwi \rmask, \raddr, OCB_OISR1_CLR - .endif - -999: - eieio - .endm - -#endif /* __ASSEMBLER__ */ - -/// \endcond - -#endif /* __GPE_IRQ_H__ */ diff --git a/pk/gpe/gpe_irq_init.c b/pk/gpe/gpe_irq_init.c deleted file mode 100644 index 061d5d10..00000000 --- a/pk/gpe/gpe_irq_init.c +++ /dev/null @@ -1,106 +0,0 @@ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2015 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file gpe_irq_init.c -/// \brief OCCHW IRQ initialization code for PK -/// -/// The entry points in this file are initialization rotines that could be -/// eliminated/deallocated by the application to free up storage if they are -/// no longer needed after initialization. - -#include "pk.h" - -/// Define the polarity and trigger condition for an interrupt. -/// -/// It is up to the application to take care of any side effects that may -/// occur from programming or reprogramming the interrupt controller. For -/// example, changing edge/level sensitivity or active level may set or clear -/// interrupt status in the controller. -/// -/// Note that PK allows this API to be called from any context, and changes -/// to the interrupt controller are made from a critical section. -/// -/// Return values other then PK_OK (0) are errors; see \ref pk_errors -/// -/// \retval 0 Successful completion -/// -/// \retval -PK_INVALID_ARGUMENT_IRQ_SETUP One or more arguments are invalid, -/// including an invalid \a irq, or invalid \a polarity or \a trigger parameters. - -int -pk_irq_setup(PkIrqId irq, - int polarity, - int trigger) -{ - PkMachineContext ctx; - - if (PK_ERROR_CHECK_API) { - PK_ERROR_IF(!OCCHW_IRQ_VALID(irq) || - !OCCHW_IRQ_OWNED(irq) || - !((polarity == PK_IRQ_POLARITY_ACTIVE_HIGH) || - (polarity == PK_IRQ_POLARITY_ACTIVE_LOW)) || - !((trigger == PK_IRQ_TRIGGER_LEVEL_SENSITIVE) || - (trigger == PK_IRQ_TRIGGER_EDGE_SENSITIVE)), - PK_INVALID_ARGUMENT_IRQ_SETUP); - } - - pk_critical_section_enter(&ctx); - - if (polarity == PK_IRQ_POLARITY_ACTIVE_HIGH) { - out32(OCCHW_OIEPR_OR(irq), OCCHW_IRQ_MASK32(irq)); - } else { - out32(OCCHW_OIEPR_CLR(irq), OCCHW_IRQ_MASK32(irq)); - } - - if (trigger == PK_IRQ_TRIGGER_EDGE_SENSITIVE) { - out32(OCCHW_OITR_OR(irq), OCCHW_IRQ_MASK32(irq)); - } else { - out32(OCCHW_OITR_CLR(irq), OCCHW_IRQ_MASK32(irq)); - } - - pk_critical_section_exit(&ctx); - - return PK_OK; -} - - -/// (Re)define the IRQ handler and priority for an interrupt. -/// Return values other then PK_OK (0) are errors; see \ref pk_errors -/// -/// Note that PK allows this API to be called from any context, and changes -/// to the interrupt controller are made from a critical section. -/// -/// \retval 0 Successful completion -/// -/// \retval -PK_INVALID_ARGUMENT_IRQ_HANDLER One or more arguments are -/// invalid, including an invalid \a irq, a null (0) \a handler, -/// or invalid \a priority. - -int -pk_irq_handler_set(PkIrqId irq, - PkIrqHandler handler, - void *arg) -{ - PkMachineContext ctx; - - if (PK_ERROR_CHECK_API) { - PK_ERROR_IF(!OCCHW_IRQ_VALID(irq) || - (handler == 0), - PK_INVALID_ARGUMENT_IRQ_HANDLER); - } - - pk_critical_section_enter(&ctx); - - __ppe42_irq_handlers[irq].handler = handler; - __ppe42_irq_handlers[irq].arg = arg; - - pk_critical_section_exit(&ctx); - - return PK_OK; -} - - - diff --git a/pk/gpe/gpe_scom_handler.S b/pk/gpe/gpe_scom_handler.S deleted file mode 100644 index 44daa52b..00000000 --- a/pk/gpe/gpe_scom_handler.S +++ /dev/null @@ -1,98 +0,0 @@ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2015 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file gpe_scom_handler.S -/// \brief Interrupt handler code for SCOM requests from the ppc405 -/// - - .nolist -#include "pk.h" -#include "occhw_shared_data.h" - .list - - ## This function handles requests from the ppc405 to perform a getscom - ## or putscom operation. - ## - ## The ppc405 must supply a request in the following format: - ## - ## bytes : Content - ## ------------------- - ## 0-3 : Status - ## 4-7 : cmd/address (bit 0 is r/!w bit) - ## 8-15 : data (supplied by ppc405 on writes) - ## - ## Register Usage: - ## - ## r3: SRAM base address - ## r4: SCOM address - ## r5: MSR manipulation - ## d5: SCOM data - ## - ## NOTE: getscom requires 2 IC lines and 1 DC line - ## putscom requires 3 IC lines and 1 DC line - ## Both require the same number of instructions (16) - .align 5 - .global gpe_scom_handler -gpe_scom_handler: - - ## Load the hardcoded base address of the scom request - _liwa %r3, OSD_GPE_SCOM_ADDR - - ## Load the scom address from SRAM - lwz %r4, OCCHW_SCOM_ADDR_OFFSET(%r3) - - ## Mask all SIB errors - mfmsr %r7 - _oriwa %r5, %r7, MSR_SEM - mtmsr %r5 - - ## Check bit 0 of the scom address to determine if this - ## is a getscom or a putscom request - bb0wi %r4, 0, _do_putscom #branch if bit 0 is 0 - -_do_getscom: - ## the cmd bit was set, which means we're doing a getscom. - ## need to clear the bit first. - clrbwi %r4, %r4, 0 - - ## do the getscom - lvd %d5, 0(%r4) - - ## store the data into the request in SRAM - stvd %d5, OCCHW_SCOM_DATA_OFFSET(%r3) - -_get_scom_status: - - ## status is in the MSR, copy it to the scom request in SRAM - mfmsr %r5 - stw %r5, OCCHW_SCOM_STATUS_OFFSET(%r3) - - ## clear the IPI_SCOM interrupt: - ## first, load the bit we want to clear into a register - _liwa %r3, OCCHW_IRQ_MASK32(OCCHW_IRQ_IPI_SCOM) - - ## then, store it to the OISR0_CLR address - _stwi %r3, %r4, OCB_OISR0_CLR - - ## restore the MSR as it was before we changed it - mtmsr %r7 - - ## return - blr - -_do_putscom: - - ## load data from the request - lvd %d5, OCCHW_SCOM_DATA_OFFSET(%r3) - - ## do the putscom - stvd %d5, 0(%r4) - - b _get_scom_status - - - - diff --git a/pk/gpe/gpe_timebase.h b/pk/gpe/gpe_timebase.h deleted file mode 100644 index 648a3dcd..00000000 --- a/pk/gpe/gpe_timebase.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef __GPE_TIMEBASE_H__ -#define __GPE_TIMEBASE_H__ - -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2015 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file gpe_timebase.h -/// \brief support for using the OCB 32 bit timebase register -/// -/// The OCB timebase register is a 32 bit count-up register that is shared -/// by all GPE's in the OCC complex. - -#include "pk.h" - -#ifndef __ASSEMBLER__ - -#ifdef APPCFG_USE_EXT_TIMEBASE -static inline -uint32_t pk_timebase32_get(void) -{ - return in32(OCB_OTBR); -} - -#else -//assembly function is defined in ppe42_timebase.S -uint32_t pk_timebase32_get(void); - -#endif /* APPCFG_USE_EXT_TIMEBASE */ - -#else - - .macro _pk_timebase32_get rT, rA - _lwzi \rT, \rA, OCB_OTBR - .endm -#endif /* __ASSEMBLER__ */ - -#endif /* __GPE_TIMEBASE_H__ */ diff --git a/pk/gpe/pk_port.h b/pk/gpe/pk_port.h deleted file mode 100644 index 410f4356..00000000 --- a/pk/gpe/pk_port.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __PK_PORT_H__ -#define __PK_PORT_H__ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2014 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pk_port.h -/// \brief The top-level GPE environment header for PK. - -#define HWMACRO_GPE - -#include "ppe42.h" -#include "gpe_timebase.h" -#endif /* __PK_PORT_H__ */ diff --git a/pk/gpe/pkgpefiles.mk b/pk/gpe/pkgpefiles.mk deleted file mode 100644 index d7025b92..00000000 --- a/pk/gpe/pkgpefiles.mk +++ /dev/null @@ -1,33 +0,0 @@ -# @file pkgpefiles.mk -# -# @brief mk for including gpe object files -# -# @page ChangeLogs Change Logs -# @section pkgpefiles.mk -# @verbatim -# -# -# Change Log ****************************************************************** -# Flag Defect/Feature User Date Description -# ------ -------------- ---------- ------------ ----------- -# -# @endverbatim -# -########################################################################## -# Object Files -########################################################################## - -GPE-C-SOURCES = gpe_init.c gpe_irq_init.c -GPE-S-SOURCES = gpe_scom_handler.S - -GPE-TIMER-C-SOURCES = -GPE-TIMER-S-SOURCES = - -GPE-THREAD-C-SOURCES = -GPE-THREAD-S-SOURCES = - -GPE-ASYNC-C-SOURCES = -GPE-ASYNC-S-SOURCES = - -GPE_OBJECTS += $(GPE-C-SOURCES:.c=.o) $(GPE-S-SOURCES:.S=.o) - |
