diff options
| -rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H | 12 | ||||
| -rw-r--r-- | src/import/generic/memory/lib/utils/shared/mss_generic_consts.H | 3 |
2 files changed, 9 insertions, 6 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index 5f089691..fd1a284c 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -69,11 +69,11 @@ enum attr_eff_engine_fields TSV_8H_SUPPORT = 6, PSTATES = 7, MRAM_SUPPORT = 8, - HEIGHT_3DS = 9, - SPD_CL_SUPPORTED = 10, + SPD_CL_SUPPORTED = 9, + ADDRESS_MIRROR = 10, // Dispatcher set to last enum value - ATTR_EFF_DISPATCHER = SPD_CL_SUPPORTED, + ATTR_EFF_DISPATCHER = ADDRESS_MIRROR, }; /// @@ -103,6 +103,7 @@ enum ffdc_codes READ_CRCT_ENDIAN = 0x0005, READ_TRAINING_RESPONSE_STRUCT = 0x0006, + SET_EXP_DRAM_ADDRESS_MIRRORING = 0x1040, SET_BYTE_ENABLES = 0x1041, SET_NIBBLE_ENABLES = 0x1042, SET_TAA_MIN = 0x1043, @@ -112,9 +113,8 @@ enum ffdc_codes SET_VREF_DQ_TRAIN_RANGE = 0x1047, SET_PSTATES = 0x1048, SET_MRAM_SUPPORT = 0x1049, - SET_3DS_HEIGHT = 0x1050, - SET_SPD_CL_SUPPORTED = 0x1051, - SET_SERDES_FREQ = 0x1052, + SET_SPD_CL_SUPPORTED = 0x1050, + SET_SERDES_FREQ = 0x1051, }; /// diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 27fb04dc..dd09fe94 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -222,6 +222,9 @@ enum generic_ffdc_codes SET_CAC_DELAY_B = 0x1077, EFD_CA_LATENCY_MODE = 0x1080, EFD_CA_PL_MODE = 0x1081, + SET_COL_ADDR_BITS = 0x1082, + SET_ROW_ADDR_BITS = 0x1083, + SET_3DS_HEIGHT = 0x1084, // Power thermal functions |
