diff options
-rw-r--r-- | src/hwpf/target.C | 29 | ||||
-rw-r--r-- | src/sbefw/app/power/chipop_table.C | 7 | ||||
-rw-r--r-- | src/sbefw/app/power/sbecmdmpipl.C | 15 | ||||
-rw-r--r-- | src/sbefw/core/sberegaccess.H | 9 |
4 files changed, 45 insertions, 15 deletions
diff --git a/src/hwpf/target.C b/src/hwpf/target.C index c2dca699..fb7d97f1 100644 --- a/src/hwpf/target.C +++ b/src/hwpf/target.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2019 */ +/* Contributors Listed Below - COPYRIGHT 2012,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -131,6 +131,7 @@ extern fapi2::ReturnCode bool l_proc_chip_mem_to_use_set = false; fapi2::buffer<uint8_t> l_proc_chip_mem_to_use_attr = 0; uint8_t isSpMode = 0; + bool isHostOpal = true; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_riskLvl)); //Getting SCRATCH_REGISTER_8 register value @@ -239,20 +240,34 @@ extern fapi2::ReturnCode FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, isMpIpl)); l_tempReg.extractToRight<3, 1>(isSpMode); - FAPI_DBG("Upating ATTR_IS_SP_MODE based on Scratch_reg3:%d",isSpMode); - FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_SP_MODE, l_chipTarget, isSpMode)); + l_tempReg.extractToRight<15, 1>(isHostOpal); + FAPI_INF("isSpMode=%d and isHostOpal=%d ",isSpMode,isHostOpal); + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_SP_MODE,l_chipTarget, isSpMode)); l_tempReg.extractToRight<28, 4>(l_riskLvl); } - //Update the HRMOR value based on system is FSP/BMC based. - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SP_MODE, l_chipTarget, isSpMode)); - if(!isSpMode && !SBE::isSimicsRunning()) + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SP_MODE,l_chipTarget, isSpMode)); + //If its BMC based system force the HRMOR to be 0xF8000000ull for both + //OPAL and PHYP payload + if( (isSpMode == false) && !SBE::isSimicsRunning()) { - FAPI_DBG("Set up ATTR_HOSTBOOT_HRMOR_OFFSET in SPless mode"); + FAPI_INF("FSP Less system HRMOR set as=0x%.8x",HRMOR_FOR_SPLESS_MODE); uint64_t hrmor = HRMOR_FOR_SPLESS_MODE; FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, FAPI_SYSTEM, hrmor)); } + //If FSP based system and payload is of the type OPAL then set the HRMOR + //as 0xF8000000ull + if(( isSpMode == true) && (!SBE::isSimicsRunning())) + { + if( isHostOpal == true) + { + FAPI_INF("OPAL based system HRMOR set as=0x%.8x",HRMOR_FOR_SPLESS_MODE); + uint64_t tempHRMOR = HRMOR_FOR_SPLESS_MODE; + FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, + FAPI_SYSTEM,tempHRMOR )); + } + } if ( l_scratch8Reg.getBit<3>() ) { diff --git a/src/sbefw/app/power/chipop_table.C b/src/sbefw/app/power/chipop_table.C index 37c6daae..513f344c 100644 --- a/src/sbefw/app/power/chipop_table.C +++ b/src/sbefw/app/power/chipop_table.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2019 */ +/* Contributors Listed Below - COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -206,10 +206,9 @@ CMD_ARR( {sbeCollectDumpMpipl, SBE_CMD_MPIPL_COLLECT_DUMP, - HARDWARE_FENCED_STATE|SBE_FENCE_AT_ISTEP| - SBE_FENCE_AT_RUNTIME|SBE_FENCE_AT_DUMPING, - // Only allowed State is MPIPL + HARDWARE_FENCED_STATE|SBE_FENCE_AT_DUMPING, } + ) ////////////////////////////////////////////////////////////// diff --git a/src/sbefw/app/power/sbecmdmpipl.C b/src/sbefw/app/power/sbecmdmpipl.C index 792cd6c4..0016e242 100644 --- a/src/sbefw/app/power/sbecmdmpipl.C +++ b/src/sbefw/app/power/sbecmdmpipl.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -311,9 +311,22 @@ uint32_t sbeCollectDumpMpipl(uint8_t *i_pArg) respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE, SBE_SEC_GENERIC_FAILURE_IN_EXECUTION); ffdc.setRc(fapiRc); + rc = fapiRc; break; } + + //Core and Cache stop Clock + SBE_ERROR(SBE_FUNC "Stop clocks for all Core and cache "); + fapiRc = stopClockS0(); + if(fapiRc != FAPI2_RC_SUCCESS) + { + rc = SBE_SEC_S0_STOP_CLOCK_FAILED; + SBE_ERROR(SBE_FUNC "Failed in Core/Cache StopClock S0 Interface"); + break; + } + }while(0); + // Create the Response to caller // If there was a FIFO error, will skip sending the response, // instead give the control back to the command processor thread diff --git a/src/sbefw/core/sberegaccess.H b/src/sbefw/core/sberegaccess.H index b2d7e1d7..c5cc7296 100644 --- a/src/sbefw/core/sberegaccess.H +++ b/src/sbefw/core/sberegaccess.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -293,10 +293,13 @@ class SbeRegAccess uint64_t iv_fspAttached : 1; uint64_t iv_collectFFDC : 1; uint64_t iv_sendFFDC : 1; - uint64_t iv_mbx3DontCare1 : 5; + uint64_t iv_mbx3Reserved1 : 5; // Already occupied bits, not used by SBE uint64_t iv_disableScomFiltering : 1; uint64_t iv_disableInvalidScomAddrCheck : 1; - uint64_t iv_mbx3DontCare2 : 19; + uint64_t iv_mbx3Reserved2 : 2; // Already occupied bits, not used by SBE + uint64_t iv_hostAsOPAL:1; + uint64_t iv_mbx3Unused1 : 12; // Free bits available for future use. + uint64_t iv_mbx3Reserved3 : 4; // Already occupied bits, not used by SBE uint64_t iv_mbx3Unused : 32; }; uint64_t iv_mbx3; |